JP2005236431A - Frequency synthesizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency synthesizer for realizing both high-speed frequency switching and satisfactory C/N characteristics. <P>SOLUTION: The frequency synthesizer is provided with a variable resistor 11 provided between the output terminal of a charge pump 3 and one end of a fixed capacitance constituting a low-pass filter 4, and variably setting a plurality of values in response to a switch control signal SWC; and a variable resistor switching time control circuit 12 for outputting a switch control signal for controlling a switching width and a switching time of the variable resistor, so that a loop gain is increased at the time of switching a frequency of the frequency synthesizer and then is gradually decreased. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a frequency synthesizer, and more particularly to a technique for speeding up a frequency synthesizer.

  FIG. 12 shows a block configuration of the frequency synthesizer. First, the phase difference between the reference signal (Fref) output from the crystal oscillator 1 and the signal (Fdiv) obtained by dividing the output signal (fo) of the voltage controlled oscillator 5 by the variable frequency divider 6 is a frequency phase comparator. 2, and a voltage pulse having a pulse width corresponding to the phase difference is sent from the frequency phase comparator 2 to the charge pump 3. Depending on the output signal of the frequency phase comparator 2, the charge pump 3 is in a state of current discharge, suction, or high impedance, and outputs a charge pump output current.

  This charge pump output current is smoothed and voltage-converted by the low-pass filter 4 to become a control voltage of the voltage controlled oscillator 5. The output signal fo of the voltage controlled oscillator 5 is fed back to the frequency phase comparator 2 as a variable frequency divider output signal Fdiv whose frequency is divided by the variable frequency divider 6. Therefore, the output signal fo of the voltage controlled oscillator 5 is expressed by the following equation (1), where M is the frequency division ratio of the variable frequency divider 6 and fref is the frequency of the reference signal Fref.

fo = M × fref (1)
In general, the loop gain G of the frequency synthesizer is set such that the gain of the frequency phase comparator 2 is KPFD, the gain of the charge pump 3 is KCP, the gain of the low-pass filter 4 is KLPF, and the gain of the voltage controlled oscillator 5 is KVCO. Then, it is represented by the following formula (2).

G = (KPFD × KCP × KLPF × KVCO) (2)
Here, if the loop gain G of the frequency synthesizer is large, the time until the frequency of the output signal settles to a constant value with a desired accuracy (hereinafter referred to as frequency switching time) is fast, but the PLL out-of-band noise The carrier ratio (hereinafter referred to as C / N) is deteriorated. Conversely, if the loop gain G of the frequency synthesizer is small, C / N is good, but the frequency switching time is delayed.
Japanese Patent Laid-Open No. 7-212228

  In the conventional frequency synthesizer, when the M value which is the frequency division ratio of the variable frequency divider 6 is changed, the frequency switching time of the frequency of the output signal of the voltage controlled oscillator 5 is the frequency synthesizer represented by the above equation (2). Therefore, in order to perform frequency switching at high speed, it is necessary to increase the loop gain G of the frequency synthesizer. However, since C / N is proportional to the loop gain G of the frequency synthesizer, in order to obtain good C / N, the loop gain G of the frequency synthesizer must be reduced. For this reason, there is a problem that it is difficult to achieve both high-speed frequency switching and good C / N characteristics.

  The present invention has been made in view of such problems, and an object thereof is to provide a frequency synthesizer that achieves both high-speed frequency switching and good C / N characteristics.

In order to achieve the above object, a first frequency synthesizer according to the present invention is provided between an output end of a charge pump and one end of a fixed capacitor constituting a low-pass filter, and a plurality of frequency synthesizers according to a resistance control signal. A variable resistor that outputs a resistance control signal that controls the switching width and switching time of the variable resistor so that the loop gain is increased when the frequency of the frequency synthesizer is switched and then gradually decreased. And a time control circuit.

  In other words, at the time of frequency pull-in, in order to increase the loop gain, a signal is input from the charge pump not only to the input terminal of the low-pass filter but also to the fixed capacitor constituting the low-pass filter that takes time to charge and discharge. The frequency pull-in is completed at high speed, and the resistance value of the variable resistor provided between the output end of the charge pump and one end of the fixed capacitor is set smoothly from zero to infinity, and the loop gain is set. Gradually lower.

  In order to achieve the above object, the second frequency synthesizer according to the present invention is provided between the output end of the charge pump and one end of the fixed capacitor constituting the low-pass filter, and a plurality of frequency synthesizers according to the capacitance control signal. A variable capacitor that variably sets the capacitance value, and a capacity control that controls the switching range and switching time of the variable capacitance so that the capacitance value of the variable capacitor is reduced and then gradually increased when switching the frequency of the frequency synthesizer And a variable capacitance switching time control circuit that outputs a signal.

  That is, at the time of frequency pull-in, in order to increase the loop gain, a signal is input from the charge pump not only to the input terminal of the low-pass filter but also to the fixed capacitor that takes time to charge and discharge, so that the frequency is high-speed. Pull-in is completed, and at the same time, the capacitance value of the variable capacitor provided between the output end of the charge pump and the fixed capacitor is variably set from a small value to a large value, and the loop gain is lowered.

  In order to achieve the above object, a third frequency synthesizer according to the present invention includes a first variable frequency divider that divides a reference signal from an oscillator and outputs a first divided signal, and a variable frequency divider. A second variable frequency divider that divides the frequency-divided signal from the frequency divider and outputs a second frequency-divided signal, and the first variable frequency divider and the second variable frequency divider when the frequency synthesizer switches the frequency. A frequency division ratio switching time control circuit for controlling the switching width and switching time of the frequency division ratio of the first variable frequency divider and the second variable frequency divider is provided so as to gradually increase the frequency division ratio. It has a configuration.

  That is, as compared with the conventional case, the first and second variable frequency dividers are provided on the input side to the frequency phase comparator, and at the time of the frequency pull-in, both frequency division ratios are set to be small and after the lock is detected or for a certain period of time. After that, the setting is changed so as to increase the frequency division ratio. In this manner, the frequency division ratio is increased stepwise, and the loop gain is lowered while maintaining the lock.

  In order to achieve the above object, a fourth frequency synthesizer according to the present invention has a variable gain voltage control so that the gain of the variable gain voltage control oscillator is increased and then gradually decreased when the frequency of the frequency synthesizer is switched. It has a configuration including a gain switching time control circuit for controlling the gain switching width and switching time of the transmitter.

  That is, at the time of frequency pull-in, in order to increase the loop gain, the sensitivity (gain) of the variable gain voltage control oscillator is increased to complete the frequency pull-in at the same time, and at the same time the sensitivity of the variable gain voltage control oscillator is decreased. Smoothly variably set to a value to lower the loop gain.

  According to the present invention, it is possible to provide a frequency synthesizer that achieves both high-speed frequency switching and good C / N characteristics.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit block diagram showing a configuration example of a frequency synthesizer according to the first embodiment of the present invention. In FIG. 1, the frequency synthesizer according to the present embodiment is provided between the output end of the charge pump 3 and one end of a fixed capacitor constituting the low-pass filter 4 in addition to the configuration of the conventional frequency synthesizer shown in FIG. A variable resistor 11 that can variably set a plurality of values according to a resistance control signal (hereinafter referred to as switch control signal SWC), and a variable resistor switching time control circuit 12 that controls a switching width and switching time of the variable resistor 11. It is composed of

The variable resistor 11 is composed of n resistors 13 and n switches 14 connected in parallel to both ends of the resistor 13, respectively, and according to switch control signals SWC (SW1, SW2,..., SW2n). 2 The value can be variably set in ⁿ steps.

The variable resistance switching time control circuit 12 receives an N frequency divider 15 that divides the reference signal from the crystal oscillator 1 by N, and a clock signal output from the N frequency divider 15, and receives the switching width of the variable resistance 11. From a 2 ⁿ counter 16 that outputs a switch control signal SWC that controls the switching time, and a switch control signal detector 17 that detects the state of the switch control signal SWC and initializes the N frequency divider 15 according to the detection result. The switch control signal SWC can be switched from the moment of channel switching.

  Next, the operation of the frequency synthesizer configured as described above according to the present embodiment will be described.

When the channel switching power save cancel signal PSoff is input to the variable resistance switching time control circuit 12, the logic “H” level is output from all of the output terminals Q1 to Q2 ⁿ of the 2 ⁿ counter 16 that have been stopped until then. The As a result, the switch control signal SWC that is the output signal of the 2 ⁿ counter 16 controls all the n switches 14 of the variable resistor 11 to be ON, and the resistance value of the variable resistor 11 becomes approximately zero.

At the same time, the switch control signal SWC is detected by the switch control signal detector 17, and the N frequency divider 15 that has been stopped is operated, and the N frequency divider 15 receives the reference from the crystal oscillator 1. A signal having a frequency 1 / N of the signal is output. As a result, the 2 ⁿ counter 16 using the signal of the frequency as a clock signal starts to operate.

  The frequency synthesizer controlled as described above is used not only for the input terminal of the low-pass filter 4 from the output terminal of the charge pump but also for the fixed capacitor that takes time to charge and discharge via the variable resistor 11. Therefore, the low-pass filter gain (KLPF) becomes high, and the frequency can be pulled in at high speed.

Further, the switch control signal S which is an output signal of the 2 ⁿ counter 16 which has started down-counting.
The WC controls the n switches 14 of the variable resistor 11 and gradually increases the resistance value of the variable resistor 11 little by little. At this time, the switching time interval is switched at a cycle of a signal having a frequency that is 1 / N of the reference signal from the crystal oscillator 1 by the N frequency divider 15. After lapse of time (reference period signal) × N × 2 ^n, all of the output terminals Q1-Q2 ⁿ of 2 ⁿ counter 16 outputs a logical "L" level.

As a result, the switch control signal SWC makes the resistance value of the variable resistor 11 almost infinite, and at the same time, the N frequency divider 15 is reset by the signal detected by the switch control signal detector 17, and the N frequency divider The frequency of the clock signal that is 15 output signals becomes zero. As a result, the 2 ⁿ counter 16 for which the clock supply has been stopped also stops. This state is maintained until a new channel switching power save cancel signal PSoff is input to the variable resistance switching time control circuit 12.

(Second Embodiment)
FIG. 2 is a circuit block diagram showing a configuration example of a frequency synthesizer according to the second embodiment of the present invention. 2 that have the same configuration or function as those in FIG. 1 referred to in the description of the first embodiment are denoted by the same reference numerals.

In the first embodiment, the variable resistor 11 is composed of n resistors 13 and n switches 14 connected in parallel to both ends of the resistor 13, respectively, and the output end of the charge pump 3 and the low frequency range In the present embodiment, the variable resistor 11 is switched between 2 ⁿ stages in accordance with the switch control signal SWC and the voltage or current capability can be varied in accordance with the switch control signal SWC. The charge pump 20 is different in that it is provided between the output end of the frequency phase comparator 2 and one end of the fixed capacitor constituting the low-pass filter 4. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

The capacity switching charge pump 20 is composed of a charge pump having a voltage or current capacity of 1 times, a charge pump having a voltage or current capacity of 2 times, ..., a charge pump having a voltage or current capacity of 2 ⁿ times, Switches SW1, SW2,..., SW that are ON / OFF controlled by a switch control signal SWC are connected in series.

  Note that the operation of the frequency synthesizer according to the present embodiment is equivalent to the operation of the frequency synthesizer according to the first embodiment, and thus description thereof is omitted.

(Third embodiment)
FIG. 3 is a circuit block diagram showing a configuration example of a frequency synthesizer according to the third embodiment of the present invention. 3, parts having the same configuration or function as those in FIG. 2 referred to in the description of the second embodiment are denoted by the same reference numerals.

  In the present embodiment, the configuration of the capacity switching charge pump 20 and the configuration of the variable resistance switching time control circuit 12 are different from those of the second embodiment.

  The variable resistor 11 is provided between the output end of the frequency phase comparator 2 and one end of the fixed capacitor constituting the low-pass filter 4, and is proportional to the current value I output from the variable resistor switching time control circuit 12. The capacity switching charge pump 20 can continuously set the output current capacity variably.

  The variable resistance switching time control circuit 12 includes a voltage / current (V → I) conversion circuit 21, an internal capacitor 22, a constant current source 23, and a switch 14. The switch 14 is turned on at the moment of channel switching. Thus, the charge charged in the internal capacitor 22 can be discharged.

  Next, the operation of the frequency synthesizer configured as described above according to the present embodiment will be described.

When the channel switching power save cancel signal PSoff is input to the variable resistance switching time control circuit 12, the switch 14 is turned ON for a moment to discharge the internal capacitor 22. Further, the output current of the V → I conversion circuit 21 that outputs a current value inversely proportional to the voltage value charged in the internal capacitor 22 has a maximum value. Thereby, in proportion to the current value output from the variable resistance switching time control circuit 12, the output current of the capacity switching charge pump 20 capable of variably setting the output current capacity continuously becomes maximum.

  The frequency synthesizer controlled as described above takes time to charge and discharge from the output end of the charge pump 20 through the variable resistor 11 from the output end of the frequency phase comparator 2 as well as the input end of the low-pass filter 4. Since the signal can be input to the fixed capacitor of the low-pass filter 4 as well, the low-pass filter gain (KLPF) is increased and the frequency can be pulled in at high speed.

  Thereafter, the internal capacitor 22 is charged by the constant current source 23, and the voltage between the terminals of the internal capacitor 22 continuously increases. As a result, the output of the V → I conversion circuit 21 that outputs a current value inversely proportional to the voltage value. The current decreases continuously.

  Eventually, charging of the internal capacitor 22 proceeds by the constant current source 23, and the voltage between the terminals of the internal capacitor 22 further increases. As a result, the V → I conversion circuit 21 that outputs a current value inversely proportional to the voltage value. Output current becomes zero. This state is maintained thereafter until a new channel switching power save cancel signal PSoff is input to the variable resistance switching time control circuit 12.

(Fourth embodiment)
FIG. 4 is a circuit block diagram showing a configuration example of a frequency synthesizer according to the fourth embodiment of the present invention. 4, parts having the same configuration or function as those in FIG. 1 referred to in the description of the first embodiment are denoted by the same reference numerals.

In this embodiment, in addition to the configuration of the first embodiment, the lock detection circuit 24 that detects that the frequency synthesizer is locked, and the channel switching starts, and the lock detection signal LDsignal from the lock detection circuit 24 is detected. Then, the lock control signal detector 26 for switching the value of the switch control signal SWC output from the 2 ⁿ counter 16 of the variable resistance switching time control circuit 12 is provided.

  Next, the operation of the frequency synthesizer configured as described above according to the present embodiment will be described.

When the channel switching power save cancel signal PSoff is input to the variable resistance switching time control circuit 12, all of the output terminals Q1 to Q2 ⁿ of the 2 ⁿ counter 16 that have been stopped output a logic “H” level. . As a result, the switch control signal SWC that is the output signal of the 2 ⁿ counter 16 controls all the n switches 14 of the variable resistor 11 to be ON, and the resistance value of the variable resistor 11 becomes approximately zero.

The lock detection circuit 24 detects the lock of the frequency synthesizer and outputs the lock detection signal LDsignal. At the same time, the switch control signal SWC is detected by the switch control signal detector 17 and has been stopped until then. 15 operates, and the N frequency divider 15 outputs a signal having a frequency 1 / N of the reference signal from the crystal oscillator 1. As a result, the 2 ⁿ counter 16 using the signal of the frequency as a clock signal starts to operate.

The frequency synthesizer controlled as described above is not limited to the low-pass filter 4 that takes time to charge and discharge from the output end of the charge pump 3 through the variable resistor 11 as well as the input end of the low-pass filter 4. Since a signal can also be input to the fixed capacitor, the low-pass filter gain (KLPF) is increased, and the frequency can be pulled in at high speed.

Further, the switch control signal S which is an output signal of the 2 ⁿ counter 16 which has started down-counting.
The WC controls the n switches 14 of the variable resistor 11 and gradually increases the resistance value of the variable resistor 11 little by little. At this time, the switching time interval is switched at a cycle of a signal having a frequency that is 1 / N of the reference signal from the crystal oscillator 1 by the N frequency divider 15. After lapse of time (reference period signal) × N × 2 ^n, all of the output terminals Q1-Q2 ⁿ of 2 ⁿ counter 16 outputs a logical "L" level.

As a result, the switch control signal SWC makes the resistance value of the variable resistor 11 almost infinite, and at the same time, the N frequency divider 15 is reset by the signal detected by the switch control signal detector 17, and the N frequency divider The frequency of the clock signal that is 15 output signals becomes zero. As a result, the 2 ⁿ counter 16 for which the clock supply has been stopped also stops. This state is maintained until a new channel switching power save cancel signal PSoff is input to the variable resistance switching time control circuit 12.

(Fifth embodiment)
FIG. 5 is a circuit block diagram showing a configuration example of a frequency synthesizer according to the fifth embodiment of the present invention. 5, parts having the same configuration or function as those in FIG. 1 referred to in the description of the first embodiment are denoted by the same reference numerals.

  In the first embodiment, the variable resistor 11 and the variable resistor switching time control circuit 12 are used, but in this embodiment, the variable capacitor 28 and the variable capacitor switching time control circuit 29 are used instead. The configuration of the variable capacitance switching time control circuit 29 is the same as that of the variable resistance switching time control circuit 12.

  The variable capacitor 28 is provided between the output end of the charge pump 3 and one end of the fixed capacitor constituting the low-pass filter 4, and is connected between the n capacitors 22 and one end of the capacitor and the ground potential. N switches 14 and a variable capacitance switch 27 provided between the output end of the charge pump 3 and the other end of the capacitor 22.

The variable capacitor 28 can be variably set in 2 ⁿ stages by the capacitor 22 and the switch 14 in accordance with a switch control signal SWC that is a capacitor control signal from the variable capacitor switching time control circuit 29.

  Next, the operation of the frequency synthesizer configured as described above according to the present embodiment will be described.

First, when the channel switching power save cancel signal PSoff is input to the variable capacitor switching time control circuit 29, the variable capacitor switch 27 of the variable capacitor 28 is turned ON, and the output terminal of the 2 ⁿ counter 16 that has been stopped until then. All of Q1 to Q2 ⁿ output a logic “H” level. As a result, the switch control signal SWC that is the output signal of the 2 ⁿ counter 16 controls all n switches 14 of the variable capacitor 28 to be OFF, and the capacitance value of the variable capacitor 28 becomes a small value.

At the same time, the switch control signal SWC is detected by the switch control signal detector 17, and the N frequency divider 15 that has been stopped is operated. The N frequency divider 15 receives the reference signal from the crystal oscillator 1. 1 / N is output. As a result, the 2 ⁿ counter 16 using the signal of the frequency as a clock signal starts to operate.

  The frequency synthesizer controlled as described above is not limited to the low-pass filter 4, which takes time to charge and discharge from the output end of the charge pump 3 through the variable capacitor 28 as well as the input end of the low-pass filter 4. Since a signal can also be input to the fixed capacitor, the low-pass filter gain (KLPF) is increased, and the frequency can be pulled in at high speed.

Further, the switch control signal S which is an output signal of the 2 ⁿ counter 16 which has started down-counting.
The WC controls the n switches 14 of the variable capacitors 28, and gradually increases the capacitance value of the variable capacitors 28 little by little. At this time, the switching time interval is switched at a cycle of a signal having a frequency that is 1 / N of the reference signal from the crystal oscillator 1 by the N frequency divider 15.

(Period of reference signal) × N × 2 ⁿ after elapse of time The output terminals Q1 to Q2 ⁿ of the 2 ⁿ counter 16
All output a logic "L" level. As a result, the switch control signal SWC increases the capacitance value of the variable capacitor 28, and at the same time, the N frequency divider 15 is reset by the signal detected by the switch control signal detector 17, and the N frequency divider The frequency of the clock signal output from 15 becomes zero. As a result, the 2 ⁿ counter 16 for which the clock supply has been stopped also stops. This state is maintained until a new channel switching power save cancel signal PSoff is input to the variable capacitance switching time control circuit 29.

(Sixth embodiment)
FIG. 6 is a circuit block diagram showing a configuration example of a frequency synthesizer according to the sixth embodiment of the present invention.

  In addition to the configuration of the conventional frequency synthesizer shown in FIG. 12, the frequency synthesizer according to the present embodiment has a variable capacitor 28 whose capacitance value changes according to the voltage value of the capacitance control signal, a switching width and a switching time of the variable capacitor 28. And a variable capacitance switching time control circuit 29 for outputting a capacitance control signal for controlling the control.

  The capacitance value of the variable capacitor 28 continuously changes in proportion to the voltage value of the capacitance control signal output from the variable capacitance switching time control circuit 29.

  The variable capacitance switching time control circuit 29 is composed of an internal capacitor 22, a constant current source 23, and a switch 14. At the moment of channel switching, the switch 14 is turned on to charge the internal capacitor 22 with charge. It can be discharged.

  Next, the operation of the frequency synthesizer configured as described above according to the present embodiment will be described.

  When the channel switching power save cancel signal PSoff is input to the variable capacitance switching time control circuit 29, the switch 14 is turned on for a moment to discharge the internal capacitance 22, and the voltage value of the capacitance control signal is minimized. Accordingly, the capacitance value of the variable capacitor 28 that can continuously change the capacitance value in proportion to the voltage value of the capacitance control signal output from the variable capacitance switching time control circuit 29 is also minimized.

  The frequency synthesizer controlled as described above is not limited to the low-pass filter 4, which takes time to charge and discharge from the output end of the charge pump 3 through the variable capacitor 28 as well as the input end of the low-pass filter 4. Since a signal can also be input to the capacitor, the low-pass filter gain (KLPF) is increased, and the frequency can be pulled in at high speed.

Thereafter, the internal capacitor 22 is charged by the constant current source 23, the voltage between the terminals of the internal capacitor 22 increases continuously, and the capacitance value of the variable capacitor 28 also increases continuously. Eventually, charging of the internal capacitor 22 proceeds by the constant current source 23, and the voltage between the terminals of the internal capacitor 22 is further increased. As a result, the voltage value of the capacity control signal becomes maximum, and the capacity of the variable capacitor 28 is increased. The value is maximized. This state is then maintained until a new channel switching power save cancel signal PSoff is input to the variable capacitance switching time control circuit 29.

(Seventh embodiment)
FIG. 7 is a circuit block diagram showing a configuration example of a frequency synthesizer according to the seventh embodiment of the present invention. In FIG. 7, parts having the same configuration or function as those in FIG. 5 referred to in the description of the fifth embodiment are denoted by the same reference numerals.

In the present embodiment, in addition to the configuration of the fifth embodiment, the lock detection circuit 24 that detects that the frequency synthesizer is locked, and the channel switching starts, and the lock detection signal LDsignal from the lock detection circuit 24 is detected. Then, the lock control signal detector 26 that switches the value of the switch control signal SWC output from the 2 ⁿ counter 16 of the variable capacitance switching time control circuit 29 is provided.

  Next, the operation of the frequency synthesizer configured as described above according to the present embodiment will be described.

When the channel switching power save cancel signal PSoff is input to the variable capacitance switching time control circuit 29, all of the output terminals Q1 to Q2 ⁿ of the 2 ⁿ counter 16 that have been stopped output a logic “H” level. . As a result, the switch control signal SWC that is the output signal of the 2 ⁿ counter 16 controls all the n switches 14 of the variable capacitors 28 to be OFF, and the variable capacitors 28 have a small value.

The lock detection circuit 24 detects the lock of the frequency synthesizer and outputs the lock detection signal LDsignal. At the same time, the switch control signal SWC is detected by the switch control signal detector 17 and has been stopped until then. 15 operates, and the N frequency divider 15 outputs a signal having a frequency 1 / N of the reference signal from the crystal oscillator 1. As a result, the 2 ⁿ counter 16 using the signal of the frequency as a clock signal starts to operate.

  The frequency synthesizer controlled as described above is not limited to the low-pass filter 4, which takes time to charge and discharge from the output end of the charge pump 3 through the variable capacitor 28 as well as the input end of the low-pass filter 4. Since a signal can also be input to the fixed capacitor, the low-pass filter gain (KLPF) is increased, and the frequency can be pulled in at high speed.

Further, the switch control signal S which is an output signal of the 2 ⁿ counter 16 which has started down-counting.
The WC controls the n switches 14 of the variable capacitor 28, and gradually increases the capacitance value of the variable capacitor 28 little by little. At this time, the switching time interval is switched at a cycle of a signal having a frequency that is 1 / N of the reference signal from the crystal oscillator 1 by the N frequency divider 15. After lapse of time (reference period signal) × N × 2 ^n, all of the output terminals Q1-Q2 ⁿ of 2 ⁿ counter 16 outputs a logical "L" level.

As a result, the switch control signal SWC increases the capacitance value of the variable capacitor, and at the same time, the N frequency divider 15 is reset by the signal detected by the switch control signal detector 17, and the N frequency divider 15 The frequency of the output clock signal is zero. As a result, the 2 ⁿ counter 16 for which the clock supply has been stopped also stops. This state is maintained until a new channel switching power save cancel signal PSoff is input to the variable capacitance switching time control circuit 29.

(Eighth embodiment)
FIG. 8 is a circuit block diagram showing a configuration example of a frequency synthesizer according to the eighth embodiment of the present invention. In FIG. 8, parts having the same configuration or function as those in FIG. 1 referred to in the description of the first embodiment are denoted by the same reference numerals.

  The frequency synthesizer according to the present embodiment includes a first variable frequency divider 30 that divides a reference signal output from the crystal oscillator 1 and a variable frequency divider in addition to the configuration of the conventional frequency synthesizer shown in FIG. A second variable frequency divider 31 that divides the frequency-divided signal of 6, and a variable gain phase comparator 32 including the frequency phase comparator 2, and a first variable frequency divider 30 and a second variable frequency divider. A frequency division ratio switching time control circuit 33 for controlling the frequency division ratio switching width 31 and the switching time. The configuration of the frequency division ratio switching time control circuit 33 is the same as that of the variable resistance switching time control circuit 12 shown in FIG.

  Next, the operation of the frequency synthesizer configured as described above according to the present embodiment will be described.

When the channel switching power save cancel signal PSoff is input to the frequency division ratio switching time control circuit 33, all the output terminals Q1 to Q2 ⁿ of the 2 ⁿ counter 16 that have been stopped so far output a logic “H” level. To do. As a result, the frequency division ratio of the first variable frequency divider 30 and the second variable frequency divider 31 is 1 (= 2 ⁰⁾ by the switch control signal SWC that is the output signal of the 2 ⁿ counter 16.
)become.

At the same time, the switch control signal SWC is detected by the switch control signal detector 17, and the N frequency divider 15 that has been stopped is operated, and the N frequency divider 15 receives the reference from the crystal oscillator 1. A signal having a frequency 1 / N of the signal is output. As a result, the 2 ⁿ counter 16 using the signal of the frequency as a clock signal starts to operate.

  In the frequency synthesizer controlled as described above, the gain (KPFD) of the variable gain phase comparator 32 becomes high, and the frequency can be pulled in at high speed.

Further, the switch control signal S which is an output signal of the 2 ⁿ counter 16 which has started down-counting.
The WC controls the frequency division ratio of the first variable frequency divider 30 and the second variable frequency divider 31 to increase the frequency division ratio gradually and smoothly. At this time, the switching time interval is switched at a cycle of a signal having a frequency that is 1 / N of the reference signal from the crystal oscillator 1 by the N frequency divider 15.

(Period of reference signal) × N × 2 ⁿ after elapse of time The output terminals Q1 to Q2 ⁿ of the 2 ⁿ counter 16
All output a logic "L" level. As a result, the switch control signal SWC results in the maximum frequency division ratio of the first variable frequency divider 30 and the second variable frequency divider 31 being 2 ⁿ , which is simultaneously detected by the switch control signal detector 17. The N divider 15 is reset by the received signal, and the frequency of the output signal of the N divider 15 becomes zero. As a result, the clock supply is stopped 2 ⁿ
The counter 16 also stops. This state is maintained until a new channel switching power save cancel signal PSoff is input to the frequency division ratio switching time control circuit 33.

(Ninth embodiment)
FIG. 9 is a circuit block diagram showing a configuration example of a frequency synthesizer according to the ninth embodiment of the present invention. 9, parts having the same configuration or function as those in FIG. 8 referred to in the description of the eighth embodiment are denoted by the same reference numerals.

The frequency synthesizer according to the present embodiment has a lock detection circuit 24 and a lock detection signal detector 26 in addition to the configuration of the frequency synthesizer according to the eighth embodiment shown in FIG.
It has the composition provided with. When the channel switching starts and the lock synthesizer detects that the frequency synthesizer is locked and the lock control signal detector 26 detects the lock detection signal LDsignal, the value of the switch control signal SWC can be switched.

  Next, the operation of the frequency synthesizer configured as described above according to the present embodiment will be described.

When the channel switching power save cancel signal PSoff is input to the frequency division ratio switching time control circuit 33, all the output terminals Q1 to Q2 ⁿ of the 2 ⁿ counter 16 that have been stopped so far output a logic “H” level. . As a result, the frequency division ratio of the first variable frequency divider 30 and the second variable frequency divider 31 is 1 (= 2 ⁰⁾ by the switch control signal SWC that is the output signal of the 2 ⁿ counter 16.
)become.

The lock detection circuit 24 detects the lock of the frequency synthesizer and outputs the lock detection signal LDsignal. At the same time, the lock control signal detector 26 operates, and the switch control signal SWC is detected by the switch control signal detector 17, The N frequency divider 15 that has been stopped is operated, and the N frequency divider 15 outputs a signal having a frequency that is 1 / N of the reference signal from the crystal oscillator 1. As a result, the 2 ⁿ counter 16 using the signal of the frequency as a clock signal starts to operate.

  In the frequency synthesizer controlled as described above, the gain (KPFD) of the variable gain phase comparator 32 becomes high, and the frequency can be pulled in at high speed.

Further, the switch control signal S which is an output signal of the 2 ⁿ counter 16 which has started down-counting.
The WC controls the frequency division ratio of the first variable frequency divider 30 and the second variable frequency divider 31 to increase the frequency division ratio gradually and smoothly. At this time, the switching time interval is switched at a cycle of a signal having a frequency that is 1 / N of the reference signal from the crystal oscillator 1 by the N frequency divider 15.

(Period of reference signal) × N × 2 ⁿ after elapse of time The output terminals Q1 to Q2 ⁿ of the 2 ⁿ counter 16
All output a logic "L" level. As a result, the switch control signal SWC results in the maximum frequency division ratio of the first variable frequency divider 30 and the second variable frequency divider 31 being 2 ⁿ , which is simultaneously detected by the switch control signal detector 17. The N divider 15 is reset by the received signal, and the frequency of the output signal of the N divider 15 becomes zero. As a result, the clock supply is stopped 2 ⁿ
The counter 16 also stops. This state is maintained until a new channel switching power save cancel signal PSoff is input to the frequency division ratio switching time control circuit 33.

(Tenth embodiment)
FIG. 10 is a circuit block diagram showing a configuration example of a frequency synthesizer according to the tenth embodiment of the present invention. 10, parts having the same configuration or function as those in FIG. 1 referred to in the description of the first embodiment are denoted by the same reference numerals.

  In the present embodiment, the variable resistor 11 in the first embodiment is deleted, a variable gain voltage control oscillator 34 is provided in place of the voltage controlled oscillator 5, and a variable gain is switched in place of the variable resistance switching time control circuit 12. A gain switching time control circuit 35 for controlling the gain switching width and switching time of the voltage controlled oscillator 34 is provided. The gain switching time control circuit 35 has the same configuration as the variable resistance switching time control circuit 12.

  Next, the operation of the frequency synthesizer configured as described above according to the present embodiment will be described.

When the channel switching power save cancel signal PSoff is input to the variable gain voltage controlled oscillator switching time control circuit 35, the output terminal Q of the 2 ⁿ counter 16 that has been stopped until then is output.
1 to Q2 ⁿ all output a logic “H” level. As a result, the switch control signal SWC, which is the output signal of the 2 ⁿ counter 16, increases the gain of the variable gain voltage controlled oscillator 34.

At the same time, the switch control signal SWC is detected by the switch control signal detector 17, and the N frequency divider 15 that has been stopped is operated. The N frequency divider 15 receives the reference signal from the crystal oscillator 1. 1 / N is output. As a result, the 2 ⁿ counter 16 using the signal of the frequency as a clock signal starts to operate.

  In the frequency synthesizer controlled as described above, the gain (KVCO) of the variable gain voltage controlled oscillator 34 is increased, and the frequency can be pulled in at high speed.

Further, the switch control signal S which is an output signal of the 2 ⁿ counter 16 which has started down-counting.
The WC smoothly decreases the gain of the variable gain voltage controlled oscillator 34. At this time, the switching time interval is switched at a cycle of a signal having a frequency that is 1 / N of the reference signal from the crystal oscillator 1 by the N frequency divider 15.

(Period of reference signal) × N × 2 ⁿ after elapse of time The output terminals Q1 to Q2 ⁿ of the 2 ⁿ counter 16
All output a logic "L" level. As a result, the switch control signal SWC minimizes the gain of the variable gain voltage control oscillator 34, and at the same time, the N frequency divider 15 is reset by the signal detected by the switch control signal detector 17, and the N frequency division is performed. The frequency of the output signal of the device 15 becomes zero. As a result, the 2 ⁿ counter 16 for which the clock supply has been stopped also stops.
This state is maintained until a new channel switching power save cancel signal PSoff is input to the gain switching time control circuit 35.

(Eleventh embodiment)
FIG. 11 is a circuit block diagram showing a configuration example of a frequency synthesizer according to the eleventh embodiment of the present invention. In FIG. 11, parts having the same configuration or function as those in FIG. 10 referred to in the description of the tenth embodiment are denoted by the same reference numerals.

  The frequency synthesizer according to the present embodiment has a configuration including a lock detection circuit 24 and a lock detection signal detector 26 in addition to the configuration of the frequency synthesizer according to the tenth embodiment shown in FIG. . When the channel switching starts and the lock synthesizer detects that the frequency synthesizer is locked and the lock control signal detector 26 detects the lock detection signal LDsignal, the value of the switch control signal SWC can be switched.

  Next, the operation of the frequency synthesizer configured as described above according to the present embodiment will be described.

When the channel switching power save cancel signal PSoff is input to the gain switching time control circuit 35, all the output terminals Q1 to Q2 ⁿ of the 2 ⁿ counter 16 that have been stopped so far output a logic “H” level. As a result, the switch control signal SWC, which is the output signal of the 2 ⁿ counter 16, increases the gain of the variable gain voltage controlled oscillator 34.

The lock detection circuit 24 detects the lock of the frequency synthesizer and outputs the lock detection signal LDsignal. At the same time, the lock control signal detector 26 operates, and the switch control signal SWC is detected by the switch control signal detector 17, The N frequency divider 15 that has been stopped is operated, and the N frequency divider 15 outputs a signal having a frequency that is 1 / N of the reference signal from the crystal oscillator 1. As a result, the 2 ⁿ counter 16 using the signal of the frequency as a clock signal starts to operate.

  In the frequency synthesizer controlled as described above, the gain (KVCO) of the variable gain voltage control oscillator 32 becomes high, and the frequency can be pulled in at high speed.

Further, the switch control signal S which is an output signal of the 2 ⁿ counter 16 which has started down-counting.
The WC smoothly decreases the gain of the variable gain voltage controlled oscillator 34. At this time, the switching time interval is switched at a cycle of a signal having a frequency that is 1 / N of the reference signal from the crystal oscillator 1 by the N frequency divider 15.

(Period of reference signal) × N × 2 ⁿ after elapse of time The output terminals Q1 to Q2 ⁿ of the 2 ⁿ counter 16
All output a logic "L" level. As a result, the switch control signal SWC minimizes the gain of the variable gain voltage control oscillator 34, and at the same time, the N frequency divider 15 is reset by the signal detected by the switch control signal detector 17, and the N frequency division is performed. The frequency of the output signal of the device 15 becomes zero. As a result, the 2 ⁿ counter 16 for which the clock supply has been stopped also stops.
This state is maintained until a new channel switching power save cancel signal PSoff is input to the gain switching time control circuit 35.

  The frequency synthesizer according to the present invention has an advantage that both high-speed frequency switching and good C / N characteristics can be achieved, and is useful for applications such as mobile communication devices.

1 is a circuit block diagram showing a configuration example of a frequency synthesizer according to a first embodiment of the present invention. The circuit block diagram which shows the example of 1 structure of the frequency synthesizer concerning the 2nd Embodiment of this invention The circuit block diagram which shows the example of 1 structure of the frequency synthesizer concerning the 3rd Embodiment of this invention The circuit block diagram which shows the example of 1 structure of the frequency synthesizer concerning the 4th Embodiment of this invention The circuit block diagram which shows the example of 1 structure of the frequency synthesizer concerning the 5th Embodiment of this invention The circuit block diagram which shows the example of 1 structure of the frequency synthesizer concerning the 6th Embodiment of this invention The circuit block diagram which shows one structural example of the frequency synthesizer which concerns on the 7th Embodiment of this invention The circuit block diagram which shows the example of 1 structure of the frequency synthesizer concerning the 8th Embodiment of this invention The circuit block diagram which shows the example of 1 structure of the frequency synthesizer concerning the 9th Embodiment of this invention The circuit block diagram which shows the example of 1 structure of the frequency synthesizer concerning the 10th Embodiment of this invention The circuit block diagram which shows the example of 1 structure of the frequency synthesizer concerning the 11th Embodiment of this invention A circuit block diagram showing a configuration example of a conventional frequency synthesizer

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Crystal oscillator 2 Frequency phase comparator 3 Charge pump 4 Low-pass filter 5 Voltage control oscillator 6 Variable frequency divider 11 Variable resistance 12 Variable resistance switching time control circuit 13 Resistance 14 Switch 15 N frequency divider 16 2 ⁿ counter 17 switch Control signal detector 20 Capability switching charge pump 21 V → I conversion circuit 22 Internal capacitance 23 Constant current source 24 Lock detection circuit 26 Lock detection signal detector 27 Variable capacitance switch 28 Variable capacitance 29 Variable capacitance switching time control circuit 30 First Variable frequency divider 31 Second variable frequency divider 32 Variable gain phase comparator 33 Dividing ratio switching time control circuit 34 Variable gain voltage controlled oscillator 35 Gain switching time control circuit

Claims (24)

An oscillator that generates a reference signal, a frequency phase comparator that compares the phase of the reference signal and a signal obtained by dividing the output signal, and outputs a phase difference signal, and generates a charge pump current according to the phase difference signal A charge pump, a low-pass filter configured by a fixed resistor and a fixed capacitor for smoothing and voltage converting the charge pump current and outputting a control voltage signal, and the output having a frequency corresponding to the control voltage signal A frequency synthesizer that forms a PLL loop with a voltage controlled oscillator that generates a signal and a variable frequency divider that divides the output signal,
A variable resistor provided between an output terminal of the charge pump and one end of a fixed capacitor constituting the low-pass filter, and variably setting a plurality of values according to a resistance control signal;
A variable resistance switching time control circuit that outputs the resistance control signal for controlling the switching width and switching time of the variable resistor so that the loop gain is increased at the time of frequency switching of the frequency synthesizer and then gradually decreased. This is a frequency synthesizer. In order to change the resistance value in 2 ⁿ steps according to the resistance control signal, the variable resistor is n
The frequency synthesizer according to claim 1, further comprising n resistors and n switches connected in parallel to both ends of the resistors. The frequency synthesizer according to claim 1, wherein the variable resistor changes a voltage or current capability in 2 ⁿ steps according to the resistance control signal.   The frequency synthesizer according to claim 1, wherein the variable resistor continuously changes the voltage or current capability in accordance with the resistance control signal. The variable resistance switching time control circuit is:
An N divider for dividing the reference signal from the oscillator by N;
A 2 ⁿ counter that receives a clock signal output from the N divider and outputs a switch control signal as the resistance control signal for controlling the switching width and switching time of the variable resistor;
4. The frequency synthesizer according to claim 1, further comprising: a switch control signal detector that detects a state of the switch control signal and activates the N frequency divider according to a detection result. 5.   6. The frequency synthesizer according to claim 5, wherein the switch control signal detector switches a frequency division ratio of the N frequency divider during frequency switching.   The frequency synthesizer according to claim 1, wherein the variable resistance switching time control circuit variably sets the value of the resistance control signal using charging / discharging of an internal capacitor.   5. The variable resistance switching time control circuit according to claim 4, wherein the value of the resistance control signal is continuously variably set using charging / discharging of an internal capacitor, and the charging / discharging speed is switched during frequency switching. Frequency synthesizer.   9. The variable resistance switching time control circuit according to claim 6, further comprising a lock detection circuit that detects that the frequency synthesizer is locked, and wherein the variable resistance switching time control circuit operates after the lock detection circuit detects lock. 10. Frequency synthesizer. An oscillator that generates a reference signal, a frequency phase comparator that compares the phase of the reference signal and a signal obtained by dividing the output signal, and outputs a phase difference signal, and generates a charge pump current according to the phase difference signal A charge pump, a low-pass filter configured by a fixed resistor and a fixed capacitor for smoothing and voltage converting the charge pump current and outputting a control voltage signal, and the output having a frequency corresponding to the control voltage signal A frequency synthesizer that forms a PLL loop with a voltage controlled oscillator that generates a signal and a variable frequency divider that divides the output signal,
A variable capacitor provided between the output end of the charge pump and one end of a fixed capacitor constituting the low-pass filter, and variably setting a plurality of capacitance values according to a capacitance control signal;
Variable capacitance switching for outputting the capacitance control signal for controlling the switching width and switching time of the capacitance value of the variable capacitor so that the capacitance value of the variable capacitor is reduced at the time of frequency switching of the frequency synthesizer and then gradually increased. A frequency synthesizer comprising a time control circuit. In order to change the capacitance value in 2 ⁿ steps according to the capacitance control signal, the variable capacitance is n
The frequency synthesizer according to claim 10, further comprising: a plurality of capacitors and n switches connected in series between the capacitors and the ground potential. The frequency synthesizer according to claim 10, wherein the variable capacitor has a configuration in which a capacitance value is changed by changing a voltage value of the capacitance control signal in 2 ⁿ steps.   The frequency synthesizer according to claim 10, wherein the variable capacitor has a configuration in which a capacitance value is changed by continuously changing a voltage value of the capacitance control signal. The variable capacitance switching time control circuit is
An N divider for dividing the reference signal from the oscillator by N;
A 2 ⁿ counter that receives a clock signal output from the N frequency divider and outputs a switch control signal as the capacitance control signal for controlling the switching width and switching time of the capacitance value of the variable capacitor;
The frequency synthesizer according to any one of claims 10 to 12, further comprising a switch control signal detector that detects a state of the switch control signal and activates the N frequency divider in accordance with a detection result.   15. The frequency synthesizer according to claim 14, wherein the switch control signal detector switches a frequency division ratio of the N frequency divider during frequency switching.   The frequency synthesizer according to claim 10, wherein the variable capacity switching time control circuit variably sets the value of the capacity control signal using charging / discharging of an internal capacity.   14. The variable capacity switching time control circuit continuously variably sets the voltage value of the capacity control signal using charging / discharging of an internal capacity, and switches the charging / discharging speed during frequency switching. Frequency synthesizer.   18. The frequency according to claim 15, further comprising: a lock detection circuit that detects that the frequency synthesizer is locked, wherein the variable capacitance switching time control circuit operates after the lock detection circuit detects lock. synthesizer. An oscillator that generates a reference signal, a frequency phase comparator that compares the phases of the first divided signal and the second divided signal and outputs a phase difference signal, and a charge pump current corresponding to the phase difference signal A charge pump that generates a low-pass filter that is composed of a fixed resistor and a fixed capacitor and smoothes and converts the charge pump current to output a control voltage signal, and has a frequency according to the control voltage signal A voltage-controlled oscillator that generates the output signal; a variable frequency divider that divides the output signal; and a first variable divider that divides a reference signal from the oscillator and outputs the first divided signal. A frequency synthesizer that forms a PLL loop with a frequency divider and a second variable frequency divider that divides the frequency-divided signal from the variable frequency divider and outputs the second frequency-divided signal;
The first variable frequency divider and the second variable frequency divider are configured to gradually increase a frequency division ratio between the first variable frequency divider and the second variable frequency divider when switching the frequency of the frequency synthesizer. A frequency synthesizer comprising a frequency division ratio switching time control circuit for controlling a frequency division ratio switching width and switching time of a frequency divider. The frequency division ratio switching time control circuit includes:
An N divider for dividing the reference signal from the oscillator by N;
In response to a clock signal output from the N frequency divider, a switch control signal for controlling a switching width and a switching time of a frequency division ratio of the first variable frequency divider and the second variable frequency divider. 2 ⁿ counter to output,
20. The frequency synthesizer according to claim 19, further comprising: a switch control signal detector that detects a state of the switch control signal and activates the N frequency divider according to a detection result.   21. The frequency synthesizer according to claim 19 or 20, further comprising: a lock detection circuit that detects that the frequency synthesizer is locked, and the frequency division ratio switching time control circuit operates after the lock detection circuit detects lock. An oscillator that generates a reference signal, a frequency phase comparator that compares the phase of the reference signal and a signal obtained by dividing the output signal, and outputs a phase difference signal, and generates a charge pump current according to the phase difference signal A charge pump, a low-pass filter configured by a fixed resistor and a fixed capacitor for smoothing and voltage converting the charge pump current and outputting a control voltage signal, and the output having a frequency corresponding to the control voltage signal A frequency synthesizer that forms a PLL loop with a variable gain voltage controlled oscillator that generates a signal and a variable frequency divider that divides the output signal,
A gain switching time for controlling the gain switching width and switching time of the variable gain voltage control oscillator so that the gain of the variable gain voltage control oscillator is increased and then gradually decreased when the frequency of the frequency synthesizer is switched. A frequency synthesizer comprising a control circuit. The gain switching time control circuit includes:
An N divider for dividing the reference signal from the oscillator by N;
A 2 ⁿ counter that receives a clock signal output from the N divider and outputs a switch control signal for controlling a gain switching width and a switching time of the variable gain voltage controlled oscillator;
The frequency synthesizer according to claim 22, further comprising: a switch control signal detector that detects a state of the switch control signal and activates the N frequency divider according to a detection result.   24. The frequency synthesizer according to claim 22, further comprising a lock detection circuit that detects that the frequency synthesizer is locked, and the gain switching time control circuit operates after the lock detection circuit detects lock.

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