JP2009188811A - Central station device of pon system, reception method, and clock data reproducing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock data reproducing circuit which can follow an input signal, accompanying frequency variation, with high precision at high speed. <P>SOLUTION: The clock data reproducing circuit includes a voltage controlled type oscillator 55 which outputs a clock signal Sc at an oscillation frequency corresponding to a control voltage Vc, a phase comparator 52 which outputs a rise signal Su or a down signal Sd, corresponding to a phase differential between an input signal (receive data) RD and a clock signal Sc, a charge pump 53 which generates a charge pump current Ip corresponding to the rise signal Su or the down signal Sd, a loop filter 54 which generates a control voltage Vc corresponding to the charge pump current Ip, and a control unit 58 which switches the charge pump 53, the loop filter 54 or both of these operation parameters based on the phase differential. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a station side device of a PON (Passive Optical Network) system connected to a plurality of home side devices through an optical fiber network, and a reception method and a clock data recovery circuit suitably used for the station side device.

The PON system refers to an optical communication system that performs optical branching in a P2MP (Point to Multi Point) connection mode without power. The station side device as an aggregation station and the home side installed in a plurality of subscriber homes The apparatus is connected by an optical fiber network that branches from a single optical fiber to a plurality of optical fibers via an optical coupler (see, for example, Patent Documents 1 and 2).
In this PON system, an NRZ (Non-Return to Zero) optical signal obtained by directly or externally modulating a light source such as a semiconductor laser is transmitted to transmit / receive information.

The optical signal transmitted by the station side device is a signal obtained by multiplexing a plurality of wavelengths, and each home side device can receive only a signal addressed to itself.
Conversely, the transmission from the home side apparatus is adjusted in timing, and the optical signal received by the station side apparatus is time-division multiplexed. That is, upstream burst communication from each home device to the station device is managed by the station device in a time-sharing manner to prevent signal collision.
And the intensity of the optical signal from each home-side device to the station-side device varies greatly due to disturbances such as transmission distance, optical fiber bending radius, external temperature, etc. It is necessary to receive correctly.

Therefore, the PON side receiving unit of the station side device includes an amplifier such as a transimpedance amplifier (TIA), a limiting amplifier (LIA), and the like, and the signal intensity is equalized by this amplifier.
In addition, the PON side receiving unit of the station side device has a clock and data recovery (CDR) circuit in the next stage of the amplifier, and in this recovery circuit, a clock synchronized with the data rate on the transmitting side is extracted. The data is reproduced using this clock.

The data rate in this case varies depending on the communication form and system used, and each communication system is standardized. For example, the data rate in GE-PON (Gigabit Ethernet PON) is 1.25 Gbps.
Incidentally, the input signal to the clock data recovery circuit output from the amplifier contains noise and jitter. Therefore, when this input signal is processed as it is, the bit error rate (BER) becomes very high, and reliable communication cannot be established.

That is, when the rate of the clock reproduced here is different from the input data rate, the reproduced rate is different from the transmission data on the transmission side, and communication is not established. For this reason, the clock signal generated by the clock data recovery device is required to be synchronized with the input data with high accuracy.
Therefore, in the clock data recovery circuit used for the station side device of the PON system, the clock having the same speed as the data is recovered from the random data including noise and jitter, and the data is sampled by using the recovered clock. Playback is to be performed.

The clock data recovery circuit generally includes a PLL circuit that recovers a clock and data by a phase synchronization method, and this circuit includes a phase comparator (PD: Phase Detector), a charge pump (CP: Charge Pump), and a low pass. A loop filter composed of a filter (LPF: Low Pass Filter), a voltage-controlled oscillator (VCO), and a divider.
Of these, the phase comparator compares the phase of the input data with the phase of the clock output by the oscillator, outputs an up signal if the phase of the oscillator is delayed, and a down signal if it is advanced Is output.

The charge pump outputs a charge pump current based on these up signals or down signals, and changes the control voltage input to the oscillator via the loop filter. The voltage controlled oscillator changes the oscillation frequency by increasing or decreasing the control voltage, and changes so that the rate of the input data and the generation clock of the oscillation frequency approaches.
Thus, in the PLL clock data recovery circuit, the frequency of the generated clock is controlled by the feedback control so as to be phase-synchronized with the input data, thereby enabling data recovery (Patent Document 3).

Japanese Patent Laying-Open No. 2004-64749 (FIG. 4) Japanese Patent Laying-Open No. 2004-289780 (FIG. 31) JP 2000-349627 A

As described above, the upstream burst communication from each home side device to the station side device is managed in a time division manner by the station side device in order to prevent signal collision, so the PON receiver of the station side device is the home side Each apparatus receives a burst signal whose intensity is greatly different and whose frequency is disturbed.
Therefore, in the clock data recovery circuit, it is necessary to assume a case where the frequency of input data to the circuit changes to a different frequency. Even in such a case, the clock frequency generated by the clock data recovery circuit is It must follow the changes in the input signal quickly.

  In this way, when the time (settling time) required until the error between the input clock and the oscillation frequency of the voltage controlled oscillator becomes Δflock or less when the frequency offset Δfoffset is added to the input signal is ts, It is known that it is represented by the formula (1).

Equation (1) assumes the case of a low-pass filter having a circuit configuration in which a resistor and a capacitor are connected in series (see the filter circuit portion in FIG. 5), Rp is the resistance of the low-pass filter, and Ip is the charge pump current. , Kvco is the gain of the voltage controlled oscillator, and M is the frequency division ratio.
As apparent from the above equation (1), it can be seen that the settling time ts until the frequency difference is almost eliminated becomes shorter as the resistance Rp and the charge pump current Ip of the low-pass filter are larger.

On the other hand, when a binary output charge pump is used, the control voltage of the voltage controlled oscillator oscillates with a certain width (ripple width), but this ripple width is the time after the frequency of the input data changes. It becomes smaller as time passes.
A useful parameter for determining whether or not the ripple converges quickly is, for example, a damping factor ζ (zeta), and this value is known to be expressed by the following equation (2).

In equation (2), when the value of the damping factor ζ is generally about 0.7 to 1.0, the ripple convergence time is shortened and a behavior without extra ripple is obtained. It can be seen that the larger the resistance Rp and the charge pump current Ip of the filter, the larger the ripple and the harder it is to converge.
In this way, paying attention to the above formulas (1) and (2), in order to shorten the settling time ts, the larger the resistance Rp and the charge pump current Ip of the low-pass filter, the more effective. From the viewpoint of suppressing excessive ripple of the control voltage with respect to the controlled oscillator, it is counterproductive, and the two are in a trade-off relationship.

  For this reason, for example, assuming the case of a clock data recovery circuit mounted on the station side device of the PON system, a low pass is set so as to shorten the settling time ts as much as possible so as to follow the upstream burst signal of each home side device at high speed. Even if the resistance value of the filter and other internal parameters are set, this time, the convergence time of the ripple of the control voltage input to the oscillator becomes long, and depending on the home device, the time that cannot accurately follow the upstream burst signal is long. As a result, the follow-up performance with respect to the upstream burst signal deteriorates.

In view of the above problems, an object of the present invention is to provide a clock data recovery circuit capable of following an input signal accompanied by a frequency change with high speed and high accuracy.
In addition, the present invention provides a station-side device capable of following an uplink burst signal time-division multiplexed for each home-side device at high speed and with high accuracy, and a time-division multiplexing reception method. With the goal.

A first clock data recovery circuit according to the present invention (Claim 1) corresponds to a voltage-controlled oscillator that outputs a clock signal at an oscillation frequency corresponding to a control voltage, and a delay or advance of the phase of the clock signal with respect to the input signal. And a phase comparator that outputs an up signal or a down signal, a charge pump that generates a charge pump current corresponding to the up signal or the down signal, and a loop filter that generates a control voltage corresponding to the charge pump current In the data recovery circuit,
A control unit is provided that switches the operation parameters of the charge pump or the loop filter or both based on the phase difference between the input signal and the clock signal.

  According to the first clock data recovery circuit having the above configuration, the control unit changes the operation parameters of the charge pump and the loop filter based on the phase difference between the input signal and the clock signal. By changing the operation parameter after receiving the input signal, it is possible to perform control to achieve both shortening of the settling time and early convergence of the ripple of the control voltage. Can follow up at high speed and with high accuracy.

Specifically, the control unit may employ a switch that switches the charge pump current to a smaller value when the phase difference is within a predetermined range than when the phase difference is not (Claim 2).
In addition, when the loop filter generates a control voltage by integrating a charge pump current with a resistor and a capacitor connected in series, the control unit is configured such that the phase difference is within a predetermined range. May switch the resistance of the loop filter to a smaller value than otherwise (Claim 3).

In this case, when the phase difference is not within the predetermined range, the charge pump current and the resistance of the loop filter are set to be large, thereby shortening the settling time.
Further, when the phase difference is within a predetermined range, the charge pump current and the loop filter resistance are set to be small, thereby achieving control voltage ripple suppression.

A second clock data recovery circuit according to the present invention (claim 4) includes a voltage controlled oscillator that outputs a clock signal at an oscillation frequency corresponding to a control voltage, and a delay or advance of the phase of the clock signal with respect to the input signal. A phase comparator that outputs an up signal or a down signal correspondingly, a charge pump that generates a charge pump current corresponding to the up signal or the down signal, and a loop filter that generates a control voltage corresponding to the charge pump current In the clock data recovery circuit,
A control unit that switches the operation parameter of the charge pump or the loop filter or both of them corresponding to the transmission source of the input signal is provided.

  According to the second clock data recovery circuit having the above-described configuration, the control unit changes the operation parameters of the charge pump and the loop filter in accordance with the transmission source of the input signal. Later, by changing the operation parameter for each transmission source, it is possible to perform control to achieve both shortening of the settling time and early convergence of the ripple of the control voltage. In contrast, high-speed and high-precision tracking can be achieved.

Specifically, the control unit stores the change timing of the charge pump current for each transmission source, and receives the input signal from the specific transmission source at the change timing corresponding to the charge signal. What switches a pump electric current is employable (Claim 5).
Further, when the loop filter generates a control voltage by integrating a charge pump current with a resistor and a capacitor connected in series, the control unit sets the change timing of the resistance of the loop filter. It may be stored for each transmission source, and when the input signal from the specific transmission source is received, the resistance of the loop filter may be switched at a change timing corresponding thereto (Claim 6).

  In this case, for example, by setting the charge pump current and loop filter resistance before the change timing to a large value, and setting the charge pump current and loop filter resistance after the change timing to a small value, the settling time can be reduced. Control in which shortening and control voltage ripple suppression are compatible can be performed for each transmission source.

The station-side device of the present invention (Claim 7) is a station-side device that receives an uplink burst signal transmitted from a home-side device in a time division multiplexing manner.
A clock data recovery circuit that recovers a clock and data from an upstream burst signal transmitted by a home-side device, and a settling time in the recovery circuit is shortened at the beginning of reception in the time slot of the upstream burst signal, and then the recovery And a control unit that switches operation parameters of the reproducing circuit so that ripple of the control voltage for the oscillator constituting the circuit is suppressed.

The reception method according to the present invention (claim 8) is a reception method for receiving burst signals from different transmission sources in a time division multiplexing manner, and the clock data recovery circuit is initially received in the time slot of the burst signal. The operation parameter of the reproduction circuit is switched so that the settling time at the time becomes shorter and thereafter the ripple of the control voltage for the oscillator constituting the reproduction circuit is suppressed.
According to the above-mentioned station side apparatus and reception method, since the settling time in the reproduction circuit is shortened at the beginning of reception and the operation parameters are switched so that the ripple of the control voltage is suppressed thereafter, the settling time is shortened and the control voltage is reduced. It is possible to achieve both ripple suppression.

As described above, according to the clock data recovery circuit of the present invention, it is possible to follow an input signal accompanied by a frequency change with high speed and high accuracy.
Accordingly, by adopting the reproduction circuit as a station-side device of the PON system, a station-side device and a receiving method capable of following an upstream burst signal having a different frequency for each home-side device with high speed and high accuracy. Can be realized.

[Overall configuration of PON system]
FIG. 1 is a schematic configuration diagram of a PON system according to an embodiment of the present invention.
In FIG. 1, the station side device 1 is installed as a central station for a plurality of home side devices 2 to 4. The home side devices 2 to 4 are respectively installed in the subscriber homes of the PON system.
A single optical fiber 5 (trunk line), which is a transmission line connected to the station-side device 1, is branched into a plurality of optical fibers (branch lines) 7 to 9 via an optical coupler 6, and the light configured thereby Home devices 2 to 4 are connected to the ends of the branched optical fibers 7 to 9 of the fiber network, respectively.

Furthermore, the station side device 1 is connected to the host network 11, and the home side devices 2 to 4 are connected to the respective user networks 12 to 14.
In FIG. 1, three home-side devices 2 to 4 are shown, but it is possible to connect 32 home-side devices by branching, for example, 32 from one optical coupler 6. In FIG. 1, only one optical coupler 6 is used, but more home-side devices can be connected to the station-side device 1 by providing a plurality of optical couplers in a column.

In FIG. 1, data is transmitted at a wavelength λ <b> 1 in the upstream direction from each home side device 2 to 4 to the station side device 1. Conversely, data is transmitted at the wavelength λ2 in the downstream direction from the station side device 1 to the home side devices 2-4. For example, as a standard of GE-PON which is an example of PON, there is a Clause 60 of IEEE standard 802.3ah-2004. In this case, the wavelengths λ1 and λ2 in the upstream and downstream directions should be in the following ranges. Can do.
1260nm ≦ λ1 ≦ 1360nm
1480 nm ≦ λ2 ≦ 1500 nm

Further, in the present embodiment, it is assumed that the uplink communication transmission rate L [Gbps] in the home side devices 2, 3, 4 is one type, and the value of L is 1, for example.
On the other hand, the transmission rate D [Gbps] of the downlink communication in the station side device 1 is also one type, and the value of D is 1, for example.

[Configuration of station side equipment]
FIG. 2 is a block diagram illustrating an outline of the internal configuration of the station-side device 1.
In FIG. 2, a frame to be transmitted in the downstream direction from the upper network 11 is received by the upper-side receiving unit 101 and once sent to the downstream buffer 102. The downlink buffer 102 passes the frame to the subsequent PON side transmission unit 103 based on an instruction from the management communication processing unit 108.

The PON side transmission unit 103 includes a physical layer encoding unit 105, an electro-optical conversion element 106, and a transmission scheduler 107.
The physical layer encoding unit 105 encodes the frame from the downlink buffer 102 by a predetermined method and outputs the frame to the electro-optical conversion element 106 as a serial bit signal.
The transmission scheduler 107 outputs the bit data to the physical layer encoding unit 105 at the transmission timing determined by the management communication processing unit 108, and controls the transmission timing of the downlink signal.

The electro-optical conversion element 106 converts the encoded bit data (electric signal) into an optical signal, and the converted downstream optical signal (wavelength λ2 and transmission rate D [Gbps]) is multiplexed / demultiplexed. It is transmitted to the home side devices 2 to 4 via the unit 104.
On the other hand, optical signals (wavelength λ1 and transmission rate L [Gbps]) transmitted from the home side devices 2 to 4 (FIG. 1) in the upstream direction pass through the multiplexing / demultiplexing unit 104 and are received by the PON side receiving unit 109. Is done.

The PON side receiving unit 109 includes a photoelectric conversion element 110, an amplifier 111, a clock data reproducing unit 112, a physical layer decoding unit 113, and a frame reproducing unit 114.
Among these, the photoelectric conversion element 110 is a semiconductor light receiving element such as a photodiode or an avalanche photodiode, and outputs an electrical signal corresponding to the amount of received light.
The amplifier 112 amplifies and outputs the electrical signal, and the output signal is input to the clock data recovery unit 112 at the subsequent stage.

The clock data reproduction unit 112 reproduces a timing component (clock) and data in synchronization with the electrical signal received from the amplifier 111. Details of the reproducing unit 112 will be described later.
The physical layer decoding unit 113 decodes the code applied to the reproduced data. The frame reproduction unit 114 detects a frame boundary from the decoded data and restores, for example, an Ethernet (registered trademark) frame.

The frame type determination unit 115 reads the header portion of the frame reproduced by the frame reproduction unit 114 to determine whether the received upstream frame is a data frame or for media access control with the home side devices 2 to 4. It is determined whether it is a control frame.
Examples of the control frame include an MPCP (Multi-point Control Protocol) frame specific to the PON system, an OAM (Operations, Administration and Maintenance) frame for equipment maintenance management, and the like.

The station-side device 1 is a grant that is a control frame that instructs the home-side devices 2 to 4 to transmit the uplink data transmission start time and the transmission permission amount, and the home-side devices 2 to 4 A report that is a control frame for notifying a value related to the amount of accumulated direction data is a kind of the MPCP frame.
If the determination result is a data frame, the frame type determination unit 115 stores this in the data queue of the uplink buffer 116. The upstream data frame stored in the data queue is sent to the higher-level transmission unit 117, and after performing predetermined processing such as header information change in the transmission unit 117, it is transmitted to the higher-level network 11. .

On the other hand, if the determination result is a control frame such as a report, the frame type determination unit 115 accumulates this in the control queue of the uplink buffer 116. The control frames stored in this control queue are sent to the management communication processing unit 108.
The management communication processing unit 108 sends the control frame to the dynamic band allocation unit 118 or the OAM processing unit 119 corresponding to the type of the control frame.

For example, if the control frame is a report that is a kind of MPCP frame, the management communication processing unit 108 sends the report to the dynamic bandwidth allocation unit 118. Based on the bandwidth request in the report, the dynamic bandwidth allocation unit 118 executes a predetermined bandwidth allocation algorithm and generates a grant as control information.
The management communication processing unit 108 temporarily accumulates the grant in the control queue of the downlink buffer 102, and instructs the transmission scheduler 107 of the PON side transmission unit 103 to transmit the grant. It is transmitted in the downlink direction via the wave unit 104.

The management communication processing unit 108 also transfers the grant to the reception scheduler 120 of the PON side reception unit 109. The reception scheduler 120 stores the LLIDs of the home side devices 2 to 4, and has a burst timing determination function for the next reception based on the LLID.
That is, the reception scheduler 120 specifies the timing for receiving the uplink burst signal received from each of the home side devices 2 to 4 based on the grant, and the clock data recovery unit 112 and the physical layer decoding unit of the PON side reception unit 109 113 operates in accordance with the reception time specified by the reception scheduler 120.

Further, when the control frame is an OAM frame, the management communication processing unit 108 sends the OAM frame to the OAM processing unit 119, and the OAM processing unit 119 performs predetermined processing (for example, failure notification) according to the contents of the OAM frame. Loopback test and link monitoring).
The management communication processing unit 108 once accumulates the OAM frame in the control queue of the downlink buffer 102 and instructs the transmission scheduler 107 of the PON side transmission unit 103 to transmit the OAM frame, thereby the OAM frame Is transmitted in the downstream direction via the multiplexing / demultiplexing unit 104.

[Configuration of home-side equipment]
FIG. 3 is a block diagram illustrating an outline of the internal configuration of the home apparatus 2.
In FIG. 3, an optical signal transmitted in the downstream direction from the station side device 1 (FIG. 1) passes through the multiplexing / demultiplexing unit 201 and is converted into an electrical signal by the optical receiving unit 202. Furthermore, this electrical signal Is received by the PON side receiving unit 204.

The PON-side receiving unit 204 reads the header portion (including the preamble portion) of the received frame, and means that the frame is addressed to itself (here, addressed to itself or a device in the user network 12 under its control). ).
As a result of the determination, if it is addressed to itself, the frame is taken in. If not, the frame is discarded. For example, a logical link identifier (LLID) described in IEEE standard 802.3ah-2004 can be given as an example of header information for performing the above destination determination.

Furthermore, the PON side receiving unit 204 determines whether the received frame is a data frame or a control frame such as a grant by reading the header portion of the frame. As a result of the determination, if it is a data frame, the PON side receiving unit 204 sends this to the data relay processing unit 207.
The data relay processing unit 207 performs predetermined relay processing such as transmission control for the user network side transmission unit 208, and the processed frame is transmitted from the user network side transmission unit 208 to the user network 12.

As a result of the determination, if the frame is a grant, the PON side receiving unit 204 transfers this to the control signal processing unit 206. The control signal processing unit 206 instructs the data relay processing unit 207 on the transmission timing and transmission amount in the upstream direction based on the grant.
On the other hand, the frame from the user network 12 is received by the user network side receiving unit 209 and transferred to the data relay processing unit 207. The transferred frame is temporarily stored in the buffer memory in the data relay processing unit 207, and the data amount is notified to the control signal processing unit 206.

The control signal processing unit 206 performs transmission control on the PON side transmission unit 205 and outputs the frame stored in the buffer memory to the PON side transmission unit 205 at a predetermined timing, and in the notified buffer memory. A report is generated on the basis of the data storage amount and output to the PON side transmission unit 205.
The output of the PON side transmission unit 203 is converted into an optical signal by the optical transmission unit 203, and is transmitted in the upstream direction through the multiplexing / demultiplexing unit 201 as a signal having a wavelength λ1 and a transmission rate L [Gbps].

[Clock data recovery unit of station side device]
[First embodiment: CDR with charge pump current variable corresponding to phase difference]
FIG. 4 is a functional block diagram showing the clock data recovery unit 112 of the first embodiment. FIG. 5 is a circuit configuration diagram of the clock data recovery unit 112.
As shown in FIGS. 4 and 5, the reproduction unit 112 includes a clock data reproduction circuit 51 that reproduces a clock and data from an upstream signal composed of a serial signal. The reproduction circuit 51 generates a clock signal with high accuracy. In order to reproduce, it is constituted by a PLL circuit that reproduces a clock and data by a phase synchronization method.

As shown in the figure, the clock data recovery circuit 51 of the present embodiment includes a phase comparator 52, a charge pump 53, a loop filter 54, from the front stage side (left side in FIG. 4) to the rear stage side (right side in FIG. 4). A voltage controlled oscillator (VCO or VCXO) 55 and a frequency divider 56 are provided.
An input signal (received data RD) from the amplifier 111 of the PON side receiving unit 109 is input to the phase comparator 52 of the clock data recovery circuit 51. The phase comparator 52, together with the charge pump 53, the loop filter 54, the oscillator 55, and the frequency divider 56, constitutes a phase locked loop that recovers the clock and data of the upstream signal.

That is, the phase comparator 52 compares the phase of the reception data RD with the phase of the clock signal Sc (the frequency obtained by dividing the clock signal CL) of the subsequent-stage oscillator 55, and based on the comparison result, the up signal Su or A down signal Sd is output. In this case, the up signal Su is output when the phase of the output clock signal Sc is behind the phase of the reception data RD, and the down signal Sd is output when the phase is advanced.
Note that the phase comparator 52 includes a retimer circuit 57 including a D flip-flop and the like for outputting the data signal DS from the reception data RD to the outside.

The charge pump 53 generates a charge pump current Ip corresponding to the up signal Su or the down signal Sd from the phase comparator 52.
The loop filter 54 includes a resistor Rp and a capacitor Cp connected in series, and outputs a control voltage Vc by integrating the charge pump current Ip generated by the charge pump 53, and an oscillator based on the control voltage Vc. 55 is charged.
The power control type oscillator 55 controls the oscillation frequency according to the control voltage Vc from the loop filter 54, and oscillates and outputs a plurality of clock signals (multiphase clock signals) CL having a predetermined phase difference, for example. .

The frequency of the oscillation signal CL output from the oscillator 55 is multiplied by a predetermined ratio by the frequency divider 56, and the multiplied clock signal Sc is fed back to the phase comparator 52.
As described above, the phase comparator 52 compares the phase of the input signal RD and the phase of the multiplied clock signal Sc, and outputs the up signal Su or the down signal Sd corresponding to the phase difference, Feedback control (phase lock loop) is performed by the phase synchronization method.

By the way, as is clear from the above formulas (1) and (2), when the charge pump current Ip of the charge pump 53 and the resistance Rp of the loop filter 54 are increased, the settling time ts required for stabilizing the frequency difference is shortened. However, the damping factor ζ indicating the degree of convergence of the control voltage Vc of the oscillator 55 increases, and the ripple of the control voltage Vc becomes difficult to converge.
Conversely, if the charge pump current Ip and the resistance Rp of the loop filter 54 are reduced, the damping factor ζ is reduced and the ripple of the control voltage Vc is likely to converge, but the settling time ts is increased.

  Accordingly, when the phase difference detected by the phase comparator 52 (the phase difference between the input signal RD and the clock signal Sc) is relatively large, the charge pump current Ip and the resistance Rp of the loop filter 54 are set to be larger and settling is performed. If the time ts is shortened and then the phase difference becomes relatively small, the settling time ts can be shortened by switching the current Ip and the resistance Rp to a smaller value to make the ripple of the control voltage Vc easier to converge. And the early convergence of the ripple, and it is considered that the input signal RD accompanied by the frequency change can be followed at high speed and with high accuracy.

Therefore, the clock data recovery circuit 51 of the present embodiment includes a charge pump current control unit 58 that switches the charge pump current Ip generated by the charge pump 53 in accordance with the magnitude of the phase difference detected by the phase comparator 52. Yes.
As shown in FIG. 5, the charge pump 53 of the regeneration circuit 51 can switch a pair of current sources 59 and 60 connected in parallel by a switch. By this switching, two types of charge pump current values Ip1, Ip2 (Ip1> Ip2) can be output.

  The charge pump current control unit 58 includes an adder 61 that adds the up signal Su and the inverted signal of the down signal Sd of the phase comparator 52, and a pair of comparators 62 connected to the output side of the adder 61, 63 and an AND circuit 64 connected to the output side of the comparators 62 and 63, and based on the output value of the AND circuit 64, one of the two types of current sources 59 and 60 of the charge pump 53 is provided. Switch one side.

Specifically, the up signal Su output from the phase comparator 52 and the inverted signal of the down signal Sd are added by the adder 61 and input to the subsequent comparators 62 and 63, respectively. Each of the comparators 62 and 63 outputs a high signal when the addition result is equal to or smaller than a predetermined threshold (V +) and equal to or larger than the predetermined threshold (V−).
Furthermore, the AND circuit 64 outputs High only when the two comparators 62 and 63 output High at the same time, whereby the addition result in the adder 61 falls within a certain range. Only, the AND circuit 64 outputs High.

When the AND circuit 64 outputs High, the value of the charge pump current Ip of the charge pump 53 is changed by the switch from the larger value Ip1 to Ip2.
Note that the capacitor 66 inserted in the subsequent stage of the adder 61 shown in FIG. 5 is provided to prevent the discrimination of the comparators 62 and 63 from becoming unstable due to noise at the time of pulse input.

  As described above, in the circuit configuration shown in FIG. 5, only when the phase difference in the phase comparator 52 becomes small enough that the addition signal of the adder 64 falls within the predetermined range set by the comparators 62 and 63. The charge pump current Ip is changed from the larger value Ip1 to the smaller value Ip2. That is, the charge pump current Ip is reduced only when the phase difference is sufficiently small, and the frequency ripple of the control voltage Vc of the oscillator 55 is suppressed.

Here, FIG. 6 is a time chart showing the relationship between the phase difference and the addition signal, and this time chart shows the following timings 1) to 5) in order from the top.
1) Input signal RD to the phase comparator 52
2) Clock signal Sc from the oscillator 55
3) Up signal Su output from the phase comparator 55
4) Down signal Sd output from the phase comparator 55
5) Addition signal of up signal and inverted signal of down signal

The phase comparator 52 detects a phase difference and outputs two signals Su and Sd that are up and down. The up signal Su and the down signal Sd are both “1” or “0” signal outputs, but up and down cannot simultaneously output “1”.
When the phase difference detected by the phase comparator 52 is large, the output of “1”, which is either up or down, is dominant for a certain period of time until the phase difference becomes small. After that, when the phase difference becomes sufficiently small, the up and down pulse widths become comparable.

In the case of FIG. 6A, the clock generated in the CDR loop, that is, the clock signal Sc generated by the voltage-controlled oscillator 55 is delayed in phase with respect to the input signal RD. The up signal Su is output for the corresponding time.
In this case, the down signal Sd is not ideally generated, but a pulse signal is actually output. Therefore, in this case, when the “up signal Su” and the “inverted signal of the down signal Sd” are added, it is understood that the up signal Su is dominant.

On the other hand, in the case of FIG. 5B, since the phase difference is sufficiently small, both the up signal Su and the down signal Sd are pulsed, and the added signal after addition as described above is also pulsed. It becomes a waveform.
Thus, since the magnitude of the addition signal of the up signal Su and the inverted signal of the down signal Sd corresponds to the magnitude of the phase difference of the clock signal Sc with respect to the input signal RD, the addition is performed as in the present embodiment. If the signal is a determination target, this is equivalent to switching the charge pump current Ip in accordance with the magnitude of the phase difference.

Furthermore, in the circuit configuration shown in FIG. 5, a switch 65 that is turned on when the reception timing tr of the upstream burst signal is notified from the management communication processing unit 108 is provided on the output side of the adder 61.
Therefore, a series of operations for changing the charge pump current Ip based on the output value of the phase comparator 52 is not performed except when an upstream burst signal is received.

  For this reason, in the time slot of the upstream burst signal transmitted from each of the home side devices 2, 3, 4, the charge pump current Ip is set to a larger value Ip 1 in the initial reception, and the settling time of the regeneration circuit 51 When ts becomes short and then the sum signal falls within a predetermined range and the phase difference becomes small, the charge pump current Ip is switched to a smaller value Ip2, and the control voltage Vc for the oscillator 55 constituting the regeneration circuit 51 is changed. Ripple is suppressed.

  As described above, according to the clock data recovery circuit 51 of the present embodiment, the charge pump 53 is charged based on the magnitude of the phase difference detected by the phase comparator 52 (specifically, the addition signal equivalent thereto). A control unit 58 for switching the pump current Ip is provided, and when the phase difference is within a predetermined range, the charge pump current Ip of the charge pump 53 is switched to Ip2 to a smaller value than usual. The settling time ts can be shortened by setting a larger value, and then the charge pump current Ip can be switched to a smaller value to achieve early convergence of the ripple, enabling high-speed and high-accuracy even for an input signal RD accompanied by a frequency change. Can follow.

[Modification of First Embodiment]
FIG. 7 is a circuit configuration diagram showing a modification of the clock data recovery unit 112 of the first embodiment.
In the regeneration circuit 51 shown in FIG. 7, instead of the adder 61 that adds the inverted signal of the up signal Su and the down signal Sd as the charge pump current control unit 58, the up signal Su and the down signal Sd within a predetermined period are added. A digital counter 67 that counts the number of pulses is used.

The digital counter 67 counts the number of each of the up signal Su and the down signal Sd, which are digital signals, and the number of up and down pulses becomes approximately the same within a certain time (for example, 100 pulses). Only when the charge pump current Ip is changed, a signal for changing the charge pump current Ip (switching from Ip1 to Ip2) is output.
The reason is that, as shown in FIG. 6, only when the phase difference is sufficiently small, the time lengths of the up signal Su and the down signal Sd are equal and the number of pulses in a certain period is the same.

In addition, the digital counter 67 receives the following operation signal from the management communication processing unit 108, thereby corresponding to the reception timing of the upstream burst signal.
1) Reset signal that prevents the digital counter from operating except during burst reception 2) Immediately after the start of burst reception, the number of pulses sufficient to compare the number of up / down pulses has not been counted yet. , A delay signal for turning on the switch after the counter 67 by delaying by a time corresponding to 100 pulses

[Second embodiment: CDR with variable resistance corresponding to phase difference]
FIG. 8 is a functional block diagram showing the clock data recovery unit 112 of the second embodiment. FIG. 9 is a circuit configuration diagram of the clock data recovery unit 112.
4 and 5 (first embodiment) and FIG. 8 and FIG. 9 (second embodiment), as is clear, in the second embodiment, the variable parameter of the operation parameter based on the phase difference is charged. This is different from the first embodiment in that the resistance Rp of the loop filter 54 is used instead of the pump current Ip.

That is, the clock data recovery circuit 51 of this embodiment includes a resistance control unit 68 that switches the internal resistance Rp of the loop filter 54 in accordance with the phase difference detected by the phase comparator 52.
As shown in FIG. 9, the loop filter 54 of the regeneration circuit 51 includes a resistor 69 connected in series to the capacitor Cp and a resistor 70 connected in parallel to the resistor 69. Can be switched by a switch, and by this switching, the resistance value Rp of the loop filter 54 can be switched between two types of values.

  The resistance control unit 68 adds an adder 61 that adds the up signal Su and the inverted signal of the down signal Sd of the phase comparator 52, and a pair of comparators 62 and 63 connected to the output side of the adder 61. And an AND circuit 64 connected to the output side of the comparators 62 and 63. Based on the output value of the AND circuit 64, the conduction of the resistor 70 of the loop filter 54 is switched, and the setting of the smaller internal resistance value is made. Switch to a value.

Thus, the clock data recovery circuit 51 of this embodiment has the same operating principle as that of the first embodiment except that the variable parameter is the resistance Rp.
That is, the larger the resistance Rp of the loop filter 54 is, the shorter the settling time ts can be shortened (see the above equation (1)). Therefore, when the addition signal of the up / down signal converges near “0”, the switch of the resistor 70 is turned off. The resistance value of the loop filter 54 is set to a smaller value.

[Modification of Second Embodiment]
FIG. 10 is a circuit configuration diagram showing a modification of the clock data recovery unit 112 of the second embodiment.
In the reproduction circuit 51 shown in FIG. 10, the number of pulses of the up signal Su and the down signal Sd within a certain period is used as the resistance control unit 68 instead of the adder 61 that adds the inverted signal of the up signal Su and the down signal Sd. Is used.
Since the configuration and operation of the digital counter 67 are the same as those in the modification of the first embodiment (FIG. 7), detailed description thereof is omitted.

[Third embodiment: CDR with variable operation parameters corresponding to reception timing]
FIG. 11 is a functional block diagram showing the clock data recovery unit 112 of the third embodiment. FIG. 12 is a circuit configuration diagram of the clock data recovery unit 112.
The third embodiment is different from the first and second embodiments in that the charge pump current Ip is changed without using the output value of the phase comparator 52.

  That is, in the present embodiment, as shown in FIGS. 11 and 12, the signal line from the management communication processing unit 108 is directly connected to the charge pump 53, and the charge pump is used by using the signal from this signal line. The switch for switching the current value Ip of 53 is controlled. Therefore, the regeneration circuit 51 of this embodiment does not include the charge pump current control unit 58 used in the first embodiment.

In the PON system, the station side device 1 in the communication process with each of the home side devices 2 to 4 makes a round trip time (RTT) from when it transmits a signal until it receives the signals from the home side devices 2 to 4. ) Is measured, and using this, the transmission distance between each of the home side devices 2 to 4 and the station side device 1 can be grasped.
If this transmission distance is known, the attenuation amount of the optical fiber received by the optical signals transmitted from the home devices 2 to 4 can be specified. That is, as the transmission distance is longer, the received intensity of the optical signal is attenuated, so that the BER can be estimated.

For this reason, in this embodiment, a reference table (LUT) 71 regarding the transmission distance of the home side devices 2 to 3 and the change timing of the charge pump current Ip is stored in advance in the management communication processing unit 108.
Since the reference table 71 requires a longer settling time for a home device with a longer transmission distance, the charge pump current Ip starts to change more slowly, and conversely, a home device with a shorter transmission distance locks earlier. It is determined so that the change start of the current Ip is accelerated.

Then, the management communication processing unit 108 identifies the change timing of the charge pump current Ip corresponding to the home side devices 2 to 4 of the transmission source of the uplink burst signal that is sequentially received from the reference table 71, and changes the change through the signal line. The timing is notified to the charge pump 53.
Therefore, in the present embodiment, the management communication processing unit 108 outside the clock data recovery circuit 51 shortens the settling time ts at the beginning of reception, and then the ripple of the control voltage Vc for the oscillator 55 constituting the recovery circuit 51. Is controlled as a control unit that switches the charge pump current Ip, which is an operation parameter of the regeneration circuit 51, thereby simultaneously satisfying fast settling time ts and suppression of frequency ripple.

[Modification of Third Embodiment]
FIG. 13 is a circuit configuration diagram showing a modification of the clock data recovery unit 112 of the third embodiment.
In the regeneration circuit 51 shown in FIG. 13, the same control mechanism as in FIG. 12 is adopted, but the operating parameter is changed not by the charge pump current Ip but by the resistance Rp of the loop filter 54. It is different from the case of. Therefore, in this case, the reference table 71 of the management communication processing unit 108 is a table relating to the transmission distance of each of the home side devices 2 to 4 and the change timing of the resistance Rp.

The above embodiments are all examples and do not limit the scope of the present invention.
The technical scope of the present invention is shown not by the embodiments but by the claims, and includes modifications within the scope equivalent to the configurations of the claims.
For example, in each of the above-described embodiments, the case where only one of the charge pump current Ip and the resistor Rp is changed is exemplified, but a circuit configuration in which both of them are changed at the same time may be employed.

1 is a schematic configuration diagram of a PON system according to an embodiment of the present invention. It is a block diagram which shows the internal structure of the station side apparatus which comprises the said PON system. It is a block diagram which shows the internal structure of the home side apparatus which comprises the said PON system. It is a functional block diagram which shows the clock data reproduction | regeneration part of 1st Embodiment. It is a circuit block diagram of the lock data reproduction | regeneration part of 1st Embodiment. It is a time chart which shows the relationship between a phase difference and an addition signal. It is a circuit block diagram which shows the modification of the clock data reproduction | regeneration part of 1st Embodiment. It is a functional block diagram which shows the clock data reproduction | regeneration part of 2nd Embodiment. It is a circuit block diagram of the clock data reproduction | regeneration part of 2nd Embodiment. It is a circuit block diagram which shows the modification of the clock data reproduction | regeneration part of 2nd Embodiment. It is a functional block diagram which shows the clock data reproduction | regeneration part of 3rd Embodiment. It is a circuit block diagram of the lock data reproducing part of 3rd Embodiment. It is a circuit block diagram which shows the modification of the clock data reproduction | regeneration part of 3rd Embodiment.

DESCRIPTION OF SYMBOLS 1 Station side apparatus 2-4 Home side apparatus 5, 7-9 Optical fiber 51 Clock data reproduction circuit 52 Phase comparator 53 Charge pump 54 Loop filter 55 Voltage control type oscillator 58 Charge pump electric current control part (control part)
68 Resistance control unit (control unit)
108 Management communication processing unit (control unit)
112 Clock data recovery unit RD Received data (input signal)
Sc clock signal (after multiplication)
CL clock signal (before multiplication)
DS Data signal Su Up signal Sd Down signal Ip Charge pump current (operation parameter)
Rp resistance (operating parameter)
Vc control voltage

Claims (8)

A clock data recovery circuit that recovers a clock and data from an input signal,
A voltage controlled oscillator that outputs a clock signal at an oscillation frequency corresponding to the control voltage; and
A phase comparator that outputs an up signal or a down signal in response to a delay or advance of the phase of the clock signal relative to the input signal;
A charge pump for generating a charge pump current corresponding to the up signal or the down signal;
A loop filter that generates a control voltage corresponding to the charge pump current;
A controller that switches the operation parameters of the charge pump or the loop filter or both based on the magnitude of the phase difference between the input signal and the clock signal;
A clock data recovery circuit comprising:   2. The clock data recovery circuit according to claim 1, wherein when the phase difference is within a predetermined range, the control unit switches the charge pump current of the charge pump to a smaller value than when the phase difference is not within the predetermined range. The loop filter generates a control voltage by integrating a charge pump current with a resistor and a capacitor connected in series,
3. The clock data recovery circuit according to claim 1, wherein when the phase difference is within a predetermined range, the control unit switches the resistance of the loop filter to a smaller value than when the phase difference is not within the predetermined range. A clock data recovery circuit that recovers a clock and data from an input signal,
A voltage controlled oscillator that outputs a clock signal at an oscillation frequency corresponding to the control voltage; and
A phase comparator that outputs an up signal or a down signal in response to a delay or advance of the phase of the clock signal relative to the input signal;
A charge pump for generating a charge pump current corresponding to the up signal or the down signal;
A loop filter that generates a control voltage corresponding to the charge pump current;
A control unit that switches operation parameters of the charge pump or the loop filter or both in accordance with the source of the input signal;
A clock data recovery circuit comprising: The control unit stores the change timing of the charge pump current for each transmission source,
5. The clock data recovery circuit according to claim 4, wherein when the input signal is received from the specific transmission source, the charge pump current is switched at a change timing corresponding to the input signal. The loop filter generates a control voltage by integrating a charge pump current with a resistor and a capacitor connected in series,
The control unit stores the change timing of the resistance of the loop filter for each transmission source,
6. The clock data recovery circuit according to claim 4, wherein when receiving an input signal from the specific transmission source, the resistance of the loop filter is switched at a change timing corresponding to the input signal. A station-side device that configures a PON system together with a plurality of home-side devices connected in P2MP form via an optical fiber, and receives an upstream burst signal transmitted from the home-side device in a time-division multiplexing method,
A clock data recovery circuit for recovering a clock and data from an upstream burst signal transmitted by the home side device;
In the time slot of the upstream burst signal, the operation of the regenerative circuit is performed so that the settling time in the regenerative circuit is shortened at the beginning of reception, and thereafter the ripple of the control voltage for the oscillator constituting the regenerative circuit is suppressed. A control unit for switching parameters;
A station-side device comprising: A reception method for receiving burst signals from different transmission sources in a time division multiplexing manner,
In the time slot of the burst signal, the settling time in the clock data recovery circuit is shortened at the beginning of reception, and then the operation of the recovery circuit is controlled so that the ripple of the control voltage for the oscillator constituting the recovery circuit is suppressed. A time division multiplexing reception method characterized by switching parameters.