JP5588814B2 - Burst receiver, burst reception control method, and system - Google Patents

Description

  The present invention provides a burst receiver that selects an appropriate gain and prevents bit error rate deterioration of a data part due to gain switching even when a burst signal having a different rise time Ton for each ONU is received. The present invention relates to a receiver and a control method thereof.

[Dissemination of optical access networks]
In recent years, with the spread of the Internet, the demand for high-speed networks has increased, and ADSL (Asymmetric Digital Subscriber Line), B-PON (Broadband PON), E-PON (Ethernet PON), and G-PON (Gigabit Capable). PON) is spreading. In particular, the PON system connects one fiber from the OLT when connecting between an accommodation station (OLT: Optical Line Terminal) placed in a station and a network unit (ONU: Optical Network Unit) placed in each user's home. And branch using an optical splitter to connect each user. For this reason, the installation cost of the fiber is low, and since it is possible to perform high-speed communication because optical transmission is used, it is in widespread use all over the world.

[PON system]
Among the PON systems, a TDM-PON system that uses light of different wavelengths for downstream transmission from the OLT to the ONU and downstream transmission from the ONU to the OLT and time-divides the signal for each ONU is widely used. This TDM-PON system is adopted in B-PON, E-PON, G-PON, and 10G-EPON.

[Burst receiver]
In the TDM-PON system, in uplink transmission, the intensity of an optical signal is a burst signal that varies greatly. The reason why the intensity of the optical signal varies greatly is that the distance between the OLT and the ONU varies from one ONU to another, and as a result, the amount of optical loss generated in the optical fiber varies from one ONU to another. In addition, the burst signal is time-division multiplexed with the optical signal from each ONU in the upstream transmission, and the time when any ONU is transmitting and the time when any ONU is not transmitted occurs. Because. The OLT needs to include a burst receiver that receives the burst signal.

[Wide dynamic range, need to shorten synchronization time]
As an index for measuring the performance of a burst receiver, there are a dynamic range and a synchronization time.
The dynamic range represents a range of strong and weak signals that can be received, and a larger range is more desirable. The synchronization time is the time required for receiver gain adjustment, threshold adjustment, clock data recovery, etc. with respect to the burst signal. The value of this synchronization time is small in order to increase the bandwidth utilization efficiency of communication. Desirable.
[Example of upstream burst signal configuration]
The configuration of the upstream burst signal will be described using 10G-EPON as an example (see Non-Patent Document 1 Clause 76). The uplink burst signal includes a Ton area, a SyncPattern area, a BurstDelimiter area, a Data area, an EndOfBurstDelimiter area, and a Toff area. The Ton region is a region where the laser changes from an OFF state to an ON state. The SyncPattern area is an area where a predetermined bit pattern is repeated. The SyncPattern area is also called a burst preamble area. While receiving the signal in the SyncPattern area, gain adjustment, threshold adjustment, and clock data recovery of the receiver are performed. The BurstDelimiter area is an area for entering a predetermined bit pattern. By detecting this BurstDelimiter, the receiving part of the OLT is used to detect the start position of the data area. The Data area is an area in which a bit pattern in which the repetition of the MAC frame is encoded by FEC (Forward Error Correction) is entered. The EndBurstDelimiter area is an area for entering a predetermined bit pattern. By detecting this EndBurstDelimiter, the OLT receiving unit can detect the end position of the data area. The Toff region is a region where the laser changes from the ON state to the OFF state.

[Variation of Ton time for each ONU]
The rise time of the ONU laser that transmits the burst signal is called Ton. In the 10G-EPON standard, the maximum value is 512 ns (see Non-Patent Document 1 Clause 75). In actual ONUs, transmitter parts adopted for each vendor or product are different, so Ton may be different for each vendor or product. Therefore, it is desirable that the OLT can receive an upstream burst signal even in a situation where ON ONs of Ton from 0 ns to 512 ns are mixed.

[Features of gain-selective transimpedance]
A gain-selective transimpedance amplifier is known as a technique for realizing a wide dynamic range and a reduction in synchronization time (see, for example, Patent Document 1). By implementing the gain switching according to the comparison result, a wide dynamic range and a shortened synchronization time are realized.

[Problems of gain switching in the data part due to noise]
In this gain selection type transimpedance amplifier, there is a problem that gain switching occurs in the data part due to noise, and the bit error ratio (BER) is lowered. This is because when the intensity of the input signal is in the vicinity of the threshold for gain switching, the gain is switched due to noise generated during reception of the data part. As a result, the output waveform of the transimpedance immediately after the switching is distorted, and the BER is lowered. End up.

[Technology for switching problems]
As a technique for solving the problem of gain switching in the data portion due to noise, techniques for limiting a period during which gain switching is allowed during burst preamble reception are disclosed (for example, Patent Documents 2 and 3).
[Description of conventional burst receiver]
FIG. 4 shows a configuration of a conventional burst receiver described in Patent Document 2. The conventional burst receiver includes a photodiode 20, amplification circuits 321 and 322, gain switching circuits 311 and 312, buffer circuits 371 and 372, a data detection unit 35, a delay circuit 36, and a gain switching comparator 38. The optical signal input to the photodiode 20 is converted into a current signal Iin by the photodiode 20. The current signal Iin input to the transimpedance amplifier 300 is converted and amplified into a voltage signal by the amplifier circuit 321, amplified by the buffer circuits 371 and 372, and then output. The output of the buffer circuit 371 is input to the data detection unit 35 and the gain switching comparator 38. The data detection unit 35 outputs a data detection signal DET when the input voltage exceeds the set threshold value Vth2. The data detection signal DET is input to a delay circuit, and a signal delayed by a set time Td is output as a gain fixed signal HOLD. The gain switching comparator 38 compares the input voltage with the threshold value Vth1 and outputs a gain switching signal SEL. Note that when the gain fixing signal HOLD is invalid, the gain switching is performed, and when the HOLD is valid, the gain is fixed, and the gain switching is not performed.

  In the burst receiver of this configuration, the gain is switched for the time set by the delay circuit after the data is detected. By adjusting the time of the delay circuit so that gain switching occurs only in the burst preamble region of the burst signal, gain switching in the data region can be prevented and BER degradation can be prevented.

Japanese Patent No. 3259707 (Japanese Patent Laid-Open No. 2000-252774) JP 2006-311033 A WO05 / 013480 (Japanese Patent Application No. 2005-507384) IEEE 802.3av Clause75

  However, the technique described in Patent Document 2 does not take into consideration that the laser rise time Ton of the ONU transmitter differs for each ONU. When the burst receiver receives a signal with different Ton from each ONU, there is a possibility that the BER deteriorates in the burst receiver. This phenomenon is not eliminated even if the setting parameters Vth2 and Td of the receiver are adjusted. An example of operation when BER deteriorates when signals with different Ton are received will be described with reference to FIGS. 5, 6, 7, 8, 9, and 10. 5, FIG. 7, FIG. 8, and FIG. 9 are timing charts of each part of the apparatus of FIG. 4 when burst signals are input in order from ONU # 1, ONU # 2, ONU # 3 under each condition.

  Here, parameters used in the drawings will be described.

  Iin is a current signal input to the transimpedance amplifier 300. BURST_RESET is a control signal input to the transimpedance amplifier 300, is input to the gain switching comparator 38 in the transimpedance amplifier 300, and is used to return the gain to the initial value. Vc is a voltage signal output from the buffer circuit 371 and is referred to by the gain switching comparator 38 and the data detection unit 35. Vout is an output signal of the transimpedance amplifier 300. Specifically, it is a voltage signal output from the buffer circuit 372. Vth2 is a threshold for detecting data in the data detection unit 35. It is used when comparing with the voltage signal Vc. It is determined that data is detected when Vc> Vth2. Vth1 is a threshold value for determining whether or not to cause gain switching in the gain switching comparator 38. Vc and Vth1 are compared, and gain switching is generated when Vc> Vth1. ZTSEL_ENABLE is a signal for controlling whether or not to enable gain switching. Only when the output voltage of the delay circuit 36 and ZTSEL_ENABLE is at a high level, the comparison result of Vc and Vth1 is determined to be valid. Td is a delay time generated by the delay circuit 36. In the delay circuit 36, ZTSEL_ENABLE is set to the high level by the time width Td. ZTSEL is a control signal for switching the gain of the transimpedance amplifier 300. When switching the gain, it becomes High level.

It is assumed that a burst signal input to the OLT includes a signal having a large power and a short Ton, a signal having a large power and a long Ton, and a signal having a power near the gain switching and a short Ton. Hereinafter, the phenomenon that BER deteriorates in all of the four conditions, condition 1 to condition 4, will be described.
[Condition 1]
The operation under the condition (condition 1) where Vth2 is smaller than Vth1 and Td is shorter than the maximum Ton will be described with reference to FIGS.

  When the first burst signal is received, Vc exceeds Vth2 at time t2, and the gain switching allowable period starts. At time t3, Vc exceeds Vth1, and the gain is switched. At time t4, the gain switching allowable period ends. Therefore, when the first burst signal is received, an appropriate gain is selected and the BER does not deteriorate.

  However, when the second burst signal is received, Vc exceeds Vth2 at time t6, and the gain switching allowable period starts, and at time t7, the gain switching allowable period ends. Thereafter, Vc exceeds Vth2 at time t8. Therefore, although the input power is large, gain switching does not occur, and as a result, the BER deteriorates.

The BER curve in this case will be described with reference to FIG. The BER curve shows the change in BER with respect to the intensity of the burst current signal input to the transimpedance amplifier 300. The intensity of the burst current signal represents a value when the intensity is stabilized in the burst.
A broken line shows a curve of BER with respect to the intensity of the current signal when the gain of the transimpedance amplifier 300 is a large value ZT_H. A dotted line indicates a BER curve with respect to the intensity of the current signal when the gain of the transimpedance amplifier 300 is a small value ZT_L. Ith1 is a current value when ZT switches from ZT_H to ZT_L. A solid line represents a curve of BER with respect to the intensity of the current signal when ZT is switched according to the input current. When a burst signal is actually input, the BER curve is a BER curve indicated by a solid line.

  When Td is shorter than Ton, the gain is switched at Ith1_alpha that is larger than the intensity Ith1 of the input current that is originally switched. Therefore, as shown in FIG. 6, the BER deteriorates in the vicinity of the intermediate input current intensity Ith1_alpha.

[Condition 2]
The operation under the condition (condition 2) where Vth2 is smaller than Vth1 and Td is longer than the maximum Ton will be described with reference to FIGS.

  When the second burst signal is received, Vc exceeds Vth2 at time t6 and the gain switching allowable period starts. At time t7, Vc exceeds Vth1, the gain is switched, and at time t8, the gain switching allowable period ends. Therefore, when the second burst signal is received, an appropriate gain is selected and the BER does not deteriorate.

  However, when the third burst signal is received, gain switching occurs due to noise at time t11, and the gain switching allowable period ends at time t12. For this reason, gain switching occurs in the data portion, and as a result, the BER deteriorates.

  The BER curve in this case will be described with reference to FIG. When Td is longer than Ton, gain switching occurs in the data portion due to noise during reception of a signal near the input current intensity Ith1. For this reason, the BER deteriorates in the vicinity of the intermediate input current intensity Ith1.

[Condition 3]
The operation under the condition (condition 3) where Vth2 is close to Vth1 and Td is shorter than the maximum Ton will be described with reference to FIGS.

  At the time of receiving the second burst signal, Vc exceeds Vth2 at time t6, and the gain switching allowable period starts. At time t7, Vc exceeds Vth2, so that the gain is switched, and at time t8, the gain switching allowable period ends. Therefore, when the second burst signal is received, an appropriate gain is selected and the BER does not deteriorate.

However, when the third burst signal is received, Vc exceeds Vth2 at time t10, and a gain switching allowable period starts. At time t11, gain switching occurs due to noise, and at time t12, the gain switching allowable period ends. For this reason, gain switching occurs in the data portion, and as a result, the BER deteriorates.
Therefore, the BER curve in this case is the BER curve shown in FIG.

[Condition 4]
The operation under the condition (condition 4) where Vth2 is close to Vth1 and Td is longer than the maximum Ton will be described with reference to FIGS.
When the second burst signal is received, Vc exceeds Vth2 at time t6, and a gain switching allowable period starts. At time t7, the gain is switched, and at time t8, the gain switching allowable period ends. Therefore, when the second burst signal is received, an appropriate gain is selected and the BER does not deteriorate.

However, when the third burst signal is received, Vc exceeds Vth2 at time t10, and a gain switching allowable period starts. At time t11, gain switching occurs due to noise, and at time t12, the gain switching allowable period ends. For this reason, gain switching occurs in the data portion, and as a result, the BER deteriorates.
Therefore, the BER curve in this case is the BER curve shown in FIG.

  Therefore, in the technique described in Patent Document 2, when there are ONUs with different Ton times, an appropriate gain allowable period is set for each ONU even if the receiver parameters (Vth1, Vth2, Td) are adjusted. As a result, the BER at the intermediate power in the vicinity where the gain switching occurs is deteriorated.

  The present invention has been made in view of such a problem, and an object of the present invention is to set an appropriate gain allowable period and prevent deterioration of BER when ONUs having different Ton times exist.

  The OLT sets a gain switching allowable period of the transimpedance amplifier for each burst signal, and performs control so that the optimum gain switching allowable period is reached. Specifically, the correspondence between the Ton notified from the ONU and the ONU identifier during ONU registration is retained, and an appropriate switching permission time Tsel is determined based on the Ton time for each received burst signal, and the gain switching of the transimpedance amplifier is performed. Set the period to allow.

  According to the present invention, it is possible to prevent BER deterioration near the gain switching point of the transimpedance amplifier even when ONUs having different Ton times exist.

  In addition, in the gain switching type transimpedance amplifier, an overlapping region that can achieve a BER of a certain level or lower is generally prepared regardless of which gain is set. According to the present invention, the operation can be performed with the overlapping area reduced, so that the dynamic range can be expanded.

  In addition, when there are ONUs having different Ton times, it is not necessary to increase Td and the burst preamble length Synctime in accordance with the maximum Ton. Therefore, even when Ton changes for each ONU, a short synchronization time can be maintained as it is, and the upstream band utilization efficiency can be maintained.

General PON system configuration General OLT configuration General ONU registration sequence Configuration of conventional burst receiver Timing chart in conventional burst receiver Condition 1 (Vth2: small, Td: small) Example of BER curve in a conventional burst receiver (Condition 1) Timing chart for conventional burst receiver Condition 2 (VTh2: small, Td: large) Timing chart for conventional burst receiver Condition 3 (Vth2: large, Td: small) Timing chart for conventional burst receiver Condition 4 (Vth2: large, Td: large) Example of BER curve in a conventional burst receiver (conditions 2, 3, 4) Configuration of burst receiver in first embodiment of the present invention Example of operation of gain switching level detector and data detector Configuration of logic circuit in first embodiment of the present invention Example of management table of gain switching allowable time in the first embodiment of the present invention The flowchart showing operation | movement of the logic circuit in the 1st Embodiment of this invention. The sequence diagram showing operation | movement of OLT and ONU in the 1st Embodiment of this invention Timing chart in the first embodiment of the present invention Configuration of burst receiver in the second embodiment of the present invention Configuration of burst receiver in the third embodiment of the present invention Timing chart in the third embodiment of the present invention Configuration of burst receiver in the fourth embodiment of the present invention Timing chart in the fourth embodiment of the present invention Configuration of burst receiver in fifth embodiment of the present invention Configuration of logic circuit in fifth embodiment of the present invention Timing chart in the fifth embodiment of the present invention Example of gain switching allowable time management table in the sixth embodiment of the present invention

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is provided to the common part in each figure.

[First Embodiment]
[Configuration of PON system]
FIG. 1 shows a configuration example of an optical access network using a PON. The optical access network includes an OLT 1, an optical splitter 3, and a plurality of ONUs 2 (2-1 to 2-n). The OLT 1 is connected to the optical splitter 3 through a trunk optical fiber 4-0. The ONUs 2 (2-1 to 2-n) are respectively connected to the optical splitter 3 via branch optical fibers 4 (4-1 to 4-n). The uplink transmission from the ONU 2 (2-1 to 2-n) to the OLT 1 will be described. The optical signal transmitted from the ONU 2 is multiplexed by the optical splitter 3. The combined optical signal is input to the OLT 1. The distance between the ONU 2 and the OLT 1 is different for each ONU. Further, since the optical signal attenuates as the distance increases, the optical signal input to the OLT 1 becomes a burst signal whose intensity varies.

[Configuration of OLT]
FIG. 2 shows a configuration example of the OLT1 apparatus. The OLT 1 includes a WDM 10, a photodiode 20, a transimpedance amplifier 30, a limit amplifier 40, a laser diode 50, a driver circuit 60, a SerDes 70, a logic circuit 80, and an SNI 90.

  The WDM 10 multiplexes / demultiplexes the upstream optical signal (wavelength λ1) and downstream optical signal (wavelength λ2). The WDM 10 outputs an upstream optical signal input from the trunk optical fiber 4-0 to the photodiode 20. The WDM 10 outputs the downstream optical signal input from the laser diode 50 to the trunk optical fiber 4-0. The photodiode 20 converts the upstream optical signal input from the WDM 10 into a current signal and outputs the current signal to the transimpedance amplifier 30. The transimpedance amplifier 30 converts the current signal input from the photodiode 20 into a voltage signal, amplifies the voltage signal, and outputs it to the limit amplifier 40. The limit amplifier 40 outputs to the SerDes 70 a serial signal obtained by amplifying the voltage signal input from the transimpedance amplifier 30 to a certain amplitude. The SerDes 70 extracts a clock from the voltage signal input from the limit amplifier 40, retimes the voltage signal with the extracted clock, and converts it into a digital signal. When converting to a digital signal, the serial signal is converted to a parallel signal. The converted parallel signal is output to the logic circuit 80. The SerDes 70 converts the parallel signal received from the logic circuit into a serial signal and outputs it to the driver circuit 60. The driver circuit 60 converts the serial voltage signal input from the SerDes 70 into a current signal, and drives the laser diode 50. The laser diode 50 converts the current signal input from the driver circuit 60 into an optical signal and outputs the optical signal to the WDM 10.

  The logic circuit 80 performs decoding, frame analysis, distribution of the uplink user data signal and the uplink control signal, analysis of the uplink control signal, and the like on the digital signal input from the SerDes 70. The uplink user data signal is output to the SNI 90. In addition, the logic circuit 80 outputs to the SerDes 70 a digital parallel signal obtained by multiplexing the downlink user data signal input from the SNI 90 and the downlink control signal generated in the logic circuit.

[ONU registration sequence]
FIG. 3 shows an ONU registration sequence. In 10G-EPON, this is called a discovery process, and is applied when a new ONU is connected. In this discovery process, the ONU-OLT round trip time is measured and information about the connected ONU is collected.

  The OLT 1 transmits Discovery GATE to all ONUs (SIG 100). When the unregistered ONU receives the Discovery GATE, it waits for a random time Random delay and then sends REGISTER_REQ to the OLT (SIG200). The reason for waiting for a random time is to prevent collision of upstream optical signals when a plurality of ONUs respond. In addition, since Discovery Window does not allocate time slots to other registered ONUs for a certain period after the Discovery GATE transmits Discovery GATE, only unregistered ONUs can transmit data to the OLT. When the OLT receives REGISTER_REQ, the OLT transmits REGISTER to all ONUs (SIG300). Thereafter, the OLT transmits GATE to the corresponding ONU (SIG400). When the ONU receives GATE, it transmits REGISTER_ACK to the OLT (SIG500). The message REGISTER_REQ includes information about the ONU's Ton time and Toff time, and the OLT can know the Ton time and Toff time of each ONU when receiving REGISTER_REQ.

[Configuration of Burst Receiver in First Embodiment]
FIG. 11 shows the configuration of the burst receiver in the first embodiment of the present invention.

  The burst receiver of the present invention includes a photodiode 20, a transimpedance amplifier 301, a limit amplifier 40, SerDes 70, and a logic circuit 81. The logic circuit 81 and the transimpedance amplifier 301 are connected by a control line, and a plurality of control signals BURST_RESET, ZTSEL_ENABLE, and DATA_DETECT are exchanged.

  The optical signal input to the photodiode 20 is converted into a current signal Iin and input to the amplifier circuit 32.

  The amplifier circuit 32 converts and amplifies the input current signal Iin into a voltage signal with a gain controlled by the gain switching circuit 31. The voltage signal amplified by the amplifier circuit 32 is output to the limit amplifier 40 as Vout. A buffer circuit may be provided after the amplifier circuit 32. The output Vc of the amplifier circuit 32 is input to the data detection unit 35 and the gain switching level detection unit 33.

  The gain switching circuit 31 switches the gain based on the control signal ZTSEL output from the gain switching control unit 343. For example, when ZTSEL = High level, the gain is set to Zt_H, and when ZTSEL = Low level, the gain is set to Zt_L.

  The limit amplifier 40 amplifies the input voltage Vout to a certain amplitude and outputs it to the SerDes 70.

  The SerDes 70 extracts a clock from the input serial electrical signal and retimes the data. Thereafter, the serial signal is converted into a parallel signal and output to the logic circuit 81.

  The logic circuit 81 controls the uplink band assigned to each ONU and controls the timing of uplink transmission. The uplink transmission timing control will be described later.

  The data detection unit 35 outputs a DATA_DETECT signal based on the result of comparing the level of the preset threshold voltage Vth2 and the input voltage Vc. An operation example of the data detection unit 35 is shown in FIG. When Vc> Vth2, DATA_DETECT = High level is output, and when Vc <Vth2, DATA_DETECT = Low level is output (see the lowermost stage in FIG. 12). The output DATA_DETECT of the data detection unit 35 is also output to the logic circuit 81.

  The gain switching level detector 33 outputs a ZTSEL_DETECT signal based on the result of comparing the preset threshold voltage Vth1 and the level of the input voltage Vc. An example of the operation of the gain switching level detector 33 is shown in FIG. When Vc> Vth1, ZTSEL_DETECT = High level is output, and when Vc <Vth1, ZTSEL_DETECT = Low level is output.

  The gain switching control unit 343 outputs a control signal ZTSEL based on the input control signals BURST_RESET, ZTSEL_ENABLE, DATA_DETECT, and ZTSEL_DETECT.

The operation of the gain switching control unit 343 will be described below. When the gain switching control unit 343 detects the rise of BURST_RESET, it outputs ZTSEL = High and sets the gain of the amplifier circuit 32 to Zt_H. Further, the gain switching operation is permitted only during a period from detection of DATA_DETECT = High to detection of ZTSEL_ENABLE = Low, and the gain is fixed, that is, the output level of ZTSEL is fixed during other periods.
Further, gain switching itself is performed based on ZTSEL_DETECT. When ZTSEL_DETECT = High, ZTSEL = High and the gain is set to Zt_H. When ZTSEL_DETECT = Low, ZTSEL = Low and the gain is Zt_L.

  In the above description, the gain switching control unit 343 determines the ZTSEL signal based on the level of ZTSEL_DETECT when the ZTSEL_ENABLE signal is High. When the input power fluctuates in the vicinity of the gain switching during the period when ZTSEL_ENABLE is High, the ZTSEL signal fluctuates between High and Low, so that the gain fluctuates and the reception operation may become unstable. Therefore, a circuit that maintains Low once the ZTSEL signal becomes Low may be added to the gain switching control unit 343.

[Configuration of Logic Circuit in First Embodiment]
FIG. 13 shows the configuration of the logic circuit in the first embodiment of the present invention.
The logic circuit 81 according to the first embodiment of the present invention includes an upstream frame receiver 801, a downstream frame transmitter 802, an MPCP controller 803, and a burst receiver controller 810.

  The upstream frame reception unit 801 performs decoding, frame analysis, distribution of control signals and user signals, and the like from the digital signal input from SerDes. The control signal is input to the MPCP control unit 803, and the user signal is input to the NNI.

  The downlink frame transmission unit 802 multiplexes the control signal received from the MPCP control unit 803 and the user signal received from the NNI, and inputs the multiplexed signal to SerDes.

  The burst receiver control unit 810 exchanges signals with the MPCP control unit 803, receives a control signal from the burst receiver, determines control of the burst receiver, and generates a control signal for receiver control. The burst receiver control unit 810 includes a control signal generation unit 811, an ONU-ID, Ton correspondence storage unit 812, and a Tsel calculation unit 813.

  Based on the DATA_DETECT signal input from the burst receiver, the Tsel signal input from the Tsel calculation unit 813, and the StartTime signal input from MPCP, the control signal generation unit 811 generates control signals BURST_RESET and ZTSEL_ENABLE for burst receiver control. Generate.

  The ONU-ID / Ton correspondence storage unit 812 stores the relationship between the ONU-ID and Ton input from the MPCP control unit 803. When an ONU-ID is input from the Tsel calculation unit 813, a corresponding Ton is output.

  When the ONU-ID is input from the MPCP control unit 803, the Tsel calculation unit 813 acquires Ton from the ONU-ID and Ton correspondence storage unit 812 using the ONU-ID. Based on the acquired Ton, the Tsel calculation unit 813 determines Tsel using a preset function, and inputs the determined Tsel to the control signal generation unit. A function for calculating Tsel will be described later.

[Management table of allowable gain switching time in logic circuit]
The logic circuit 81 holds the correspondence between the ONUID, which is the ONU identifier, and the ONU Ton time. Further, the gain switching allowable time manages the correspondence of Tsel_n = F1 (Ton_n) by the function F1. Note that ONU-ID = 0 is set for ONUs not registered in the OLT.

[Tsel calculation method]
The Tsel calculation unit 813 calculates the gain switching allowable time using the function F1 having Ton as a variable. For example, the function F1 (Ton) = Ton + α−β is used.

  α is the time when gain control of the transimpedance amplifier 301 and threshold control of the limit amplifier 40 are completed when Ton is almost zero, and is a value that can be actually measured. β is calculated based on a processing delay time from when the logic circuit 81 detects the DATA_DETECT signal to when the ZTSEL_ENABLE signal is output. This processing delay time is a value that can be estimated when the logic circuit is designed, and an estimated value is set. Further, the value may be set by measuring in advance. For unregistered ONUs, since Ton is unknown, calculation is based on Ton_max, which is the maximum Ton time assumed in the system. For example, the maximum Ton time specified by the standard is used.

[Uplink transmission timing control]
The OLT controls uplink communication using a GATE message transmitted to the ONU. The GATE message includes information on the time GrantStartTime for starting uplink transmission and the uplink transmission permission time GrantLength, and the ONU performs uplink transmission based on this information. Therefore, the OLT can know in advance the timing StartTime received from each ONU.

[Operation of Logic Circuit in First Embodiment]
FIG. 15 is a flowchart showing the operation of the logic circuit according to the first embodiment of the present invention.

  In S100, the logic circuit is initialized and processing is started.

  In S101, it is determined whether it is the Discovery phase or the normal transfer phase. For example, the time per Discovery phase and the normal transfer phase is 1 ms, the Discovery phase is executed once, the normal transfer phase is executed 999 times, the Discovery phase is executed once, the normal transfer phase is executed 999 times, and so on. . By providing a counter that counts the number of times that the normal transfer phase has been executed, it is possible to determine whether it is the Discovery phase or the normal transfer phase. If it is determined in S101 that the phase is the Discovery phase, the process proceeds to S201. Otherwise, the process proceeds to S301.

First, the operation when it is determined as the Discovery phase will be described.
In S201, the Discovery process is started, and the process proceeds to S202.
In S202, Discovery GATE is transmitted to all ONUs, and the process proceeds to S203.
In S203, in preparation for receiving a burst signal from the ONU responding to the DiscoveryGATE, the logic circuit sets a Tsel for unregistered ONU, and proceeds to S204.
In S204, it is determined whether or not REGISTER_REQ has been received for a fixed time.

If received, the process proceeds to S205. If not received, the process proceeds to S209.
In S205, REGISTER is transmitted to all ONUs, and the process proceeds to S206.
In S206, GATE is transmitted to the ONU that transmitted REGISTER_REQ. After completion of GATE transmission, the process proceeds to S207.
In S207, REGISTER_ACK is received, and ACK or NACK is determined from the message content. If it is ACK, the process proceeds to S208. Otherwise, the process proceeds to S209.
In S208, the correspondence between the Ton time included in REGISTER_REQ and the ONU-ID included in REGISTER_ACK is acquired in S204, and the correspondence is held in the ONU-ID and Ton correspondence storage unit.

  In S209, the Discovery process is terminated, and the process returns to S101.

Next, an operation when it is not determined as the Discovery phase will be described.
In S301, normal transfer processing is started, and the process proceeds to S302.
In S302, GATE is transmitted to the registered ONU, and the process proceeds to S303.
In S303, the correspondence between the ONU-ID and the scheduled period for receiving the burst signal from each ONU from the StartTime and Length assigned by GATE is determined and input to the receiver control circuit.
In S304, the receiver control circuit generates a burst control signal based on Tsel set for each ONU-ID, and the receiver receives data or report.
In S305, the normal transfer process is terminated, and the process returns to S101.

[Operation of OLT and ONU in First Embodiment]
FIG. 16 shows a sequence diagram representing the operations of the OLT and the ONU in the first embodiment of the present invention. It is assumed that ONU # 1 is not registered and ONU # 2 is registered at the start time.

  The OLT starts the Discovery process and sends Discovery GATE (SIG01) to all ONUs. Thereafter, the OLT sets the Tsel of the unregistered ONU in preparation for signal reception from the unregistered ONU. The unregistered ONU # 1 transmits REGISTER_REQ (SIG02) to the OLT after waiting for a random time after receiving DiscoveryGATE.

The OLT transmits REGISTER (SIG03) to all ONUs after the Discovery Window ends. Furthermore, the OLT transmits GATE (SIG04) to the ONU that transmitted REGISTER_REQ (SIG02).
ONU # 1 transmits REGISTER_ACK (SIG05) to the OLT.
The OLT stores the correspondence between the ONU-ID and the Ton time for the ONU that has received the REGISTER_ACK. Then, the Discovery process ends.

  Next, the OLT starts normal transfer processing, transmits GATE (SIG06 and SIG07) to each registered ONU, and gives an upstream transmission grant to the ONU. Further, Tsel for receiving each ONU is set in preparation for reception from the ONU. The OLT first sets the ONU # 1 Tsel.

  In the ONU, an uplink signal is transmitted for a period permitted by the uplink transmission grant GATE. Data (SIG08) and REPORT (SIG09) are transmitted during the period when ONU # 1 is permitted. The OLT performs control of the receiving unit determined by Tsel_1 on the received signal. Data (SIG10) and REPORT (SIG11) are transmitted during the period when ONU # 2 is permitted. The OLT performs control of the receiving unit determined by Tsel_2 with respect to the received signal.

[Operation Example of Receiver in First Embodiment]
FIG. 17 is a timing chart showing the operation in the first embodiment of the present invention. An operation example of Iin, BURST_RESET, Vc, Vout, ZTSEL_ENABLE, and ZTSEL is shown. Further, it is assumed that burst signals are input in order from ONU # 1, ONU # 2, ONU # 3.

  In the initial state, no signal is input to Iin, and all other control signals are Low.

  BURST_RESET is input at time t1, ZTSEL = Low, and the gain is set to ZT_H. At time t2, Vc exceeds Vth2, ZTSEL_ENABLE = High, and a gain switching allowable period starts. At time t3, Vc exceeds Vth1, ZTSEL = High, and the gain changes to ZT_L. At time t4 = t2 + Tsel_1, the gain switching allowable period ends, the output High of ZTSEL at this time is fixed, and the gain is set to ZT_L. Note that Tsel_1 is adjusted to end the gain switching allowable period during the reception of SyncPattern.

  BURST_RESET is input at time t5, ZTSEL = Low, and the gain is set to ZT_H. At time t6, Vc exceeds Vth2, ZTSEL_ENABLE = High, and a gain switching allowable period is started. At time t7, Vc exceeds Vth1, ZTSEL = High, and the gain changes to ZT_L. At time t8 = t6 + Tsel_2, the gain switching allowable period ends, the output High of ZTSEL at this time is fixed, and the gain is set to ZT_L. Since Tsel_2 is set based on Ton_2, the gain switching allowable period is ended during the reception of SyncPattern. Since an appropriate gain switching allowable period is set even for a burst with a long Ton, an appropriate gain is selected, and BER deterioration can be prevented.

  At time t9, BURST_RESET is input, ZTSEL = Low, and the gain is set to ZT_H. At time t10, Vc exceeds Vth2, ZTSEL_ENABLE = High, and a gain switching allowable period is started. At time t11 = t10 + Tsel_3, the gain switching allowable period ends, the output Low of ZT_SEL at this time is fixed, and the gain remains ZT_H. Note that since Tsel_3 is set based on Ton_3, the gain switching allowable period ends during the reception of SyncPattern. At time t12, Iin changes during data reception, and Vc exceeds Vth1. At this time, since ZTSEL_ENABLE = Low and gain switching is not allowed, gain switching due to noise does not occur. For this reason, it is possible to prevent waveform deterioration due to gain switching and to prevent BER deterioration.

  As described above, according to the first embodiment, it is possible to prevent the deterioration of the BER even when the Ton time is different for each ONU.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. Description will be made centering on differences from the first embodiment. In the second embodiment, data detection is not performed by a transimpedance amplifier but by a limit amplifier 41 having a function equivalent to data detection.

[Configuration of Burst Receiver in Second Embodiment]
The configuration of the burst receiver in the second embodiment will be described with reference to FIG.

  The difference from the first embodiment is that the transimpedance amplifier 302 does not have a data detection unit, and the limit amplifier 41 outputs a data detection signal DATA_DETECT_LA. The logic circuit may be the same as in the first embodiment. Some limit amplifiers can output LOS (Loss of Signal) as a control signal. The data detection signal can be used as a LOS signal or a signal obtained by inverting the LOS signal.

[Example of receiver operation in the second embodiment]
The operation of the burst receiver in the second embodiment is almost the same as that of the first embodiment. In the first embodiment, when Vc exceeds Vth2 and DATA_DETECT = High, ZTSEL_ENABLE = High. In the second embodiment, when LA becomes DATA_DETECT_LA = High, ZTSEL_ENABLE = High. In addition, in the first embodiment, the start of the gain switching allowance is performed by DATA_DETECT, but in the second embodiment, it is performed at the rising edge of ZTSEL_ENABLE.

[Effects of the second embodiment]
According to the second embodiment, it is possible to prevent the BER from being deteriorated even when the Ton time is different for each ONU as in the first embodiment. Further, the control signal of the transimpedance amplifier is reduced as compared with the first embodiment, and the data detection unit becomes unnecessary in the transimpedance amplifier. Therefore, the circuit of the transimpedance amplifier can be simplified.

[Third embodiment]
Next, a third embodiment of the present invention will be described. Description will be made centering on differences from the first embodiment.

[Configuration of Burst Receiver in Third Embodiment]
The configuration of the burst receiver in the third embodiment will be described with reference to FIG.
The difference from the first embodiment is that the transimpedance amplifier 303 does not have a data detection unit, and the logic circuit does not have a control input for DATA_DETECT.
In the third embodiment, the gain switching allowable period is started when the rising edge of ZTSEL_ENABLE that rises simultaneously with BURST_RESET is detected. Further, the end of the gain switching allowable period is performed when the falling edge of ZTSEL_ENABLE is detected. In the third embodiment and the first embodiment, since the start timing of the gain switching allowable period is different, the Tsel calculation function may be different from that of the first embodiment.

[Operation example in the third embodiment]
FIG. 20 shows a timing chart showing the operation in the third embodiment of the present invention. An operation example of Iin, BURST_RESET, Vc, Vout, ZTSEL_ENABLE, and ZTSEL is shown. Further, it is assumed that burst signals are input in order from ONU # 1, ONU # 2, ONU # 3.

  In the initial state, no signal is input to Iin, and all other control signals are Low.

  BURST_RESET is input at time t1, ZTSEL = Low, and the gain is set to ZT_H. Further, ZTSEL_ENABLE = High is set and the gain switching allowable period is started. At time t2, Vc exceeds Vth1, ZTSEL = High, and the gain changes to ZT_L. At time t3 = t2 + Tsel_1, the gain switching allowable period ends, the output High of ZTSEL at this time is fixed, and the gain is set to ZT_L. Note that Tsel_1 is adjusted to end the gain switching allowable period during the reception of SyncPattern.

  BURST_RESET is input at time t4, ZTSEL = Low, and the gain is set to ZT_H. At time t5, Vc exceeds Vth1, ZT_SEL = High, and the gain changes to ZT_L. At time t6 = t4 + Tsel_2, the gain switching allowable period ends, the output High of ZTSEL at this time is fixed, and the gain is set to ZT_L. Since Tsel_2 is set based on Ton_2, the gain switching allowable period is ended during the reception of SyncPattern. Since an appropriate gain switching allowable period is set even for a burst with a long Ton, an appropriate gain is selected, and BER deterioration can be prevented.

  At time t7, BURST_RESET is input, ZTSEL = Low, and the gain is set to ZT_H. At time t8 = t7 + Tsel_3, the gain switching allowable period ends, the output Low of ZTSEL at this time is fixed, and the gain remains ZT_H. Note that since Tsel_3 is set based on Ton_3, the gain switching allowable period ends during the reception of SyncPattern. At time t9, Iin changes during data reception, and Vc exceeds Vth1. At this time, since ZTSEL_ENABLE = Low and gain switching is not allowed, gain switching due to noise does not occur. For this reason, it is possible to prevent waveform deterioration due to gain switching and to prevent BER deterioration.

[Effects of the third embodiment]
As described above, also in the third embodiment, it is possible to prevent the deterioration of the BER even when the Ton time is different for each ONU. The control signal for the transimpedance amplifier is reduced as compared with the first embodiment, and the data detection unit is not required for the transimpedance amplifier. Further, since the DATA_DETECT input is not required in the logic circuit, the logic circuit can be simplified. Therefore, the transimpedance amplifier and the logic circuit can be simplified.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. Description will be made centering on differences from the first embodiment.

  In the fourth embodiment, the functions of the BURST_RESET signal and the ZTSEL_ENABLE signal are realized by a common signal line BURST_RESET / ZTSEL_ENABLE signal.

[Configuration of Burst Receiver in Fourth Embodiment]
The configuration of the burst receiver in the fourth embodiment will be described with reference to FIG.
The difference from the first embodiment is that there is one control signal from the logic circuit to the transimpedance amplifier.
In the fourth embodiment, the start of the gain switching allowable period is performed when DATA_DETECT rises, and the gain switching allowable period ends when the common signal falls. Also, the transimpedance amplifier is reset when the common signal rises.

[Example of operation in the fourth embodiment]
FIG. 22 is a timing chart showing the operation in the fourth embodiment of the present invention. An operation example of Iin, BURST_RESET, Vc, Vout, ZTSEL_ENABLE, and ZTSEL is shown. Further, it is assumed that burst signals are input in order from ONU # 1, ONU # 2, ONU # 3.

  In the initial state, no signal is input to Iin, and all other control signals are Low.

  BURST_RESET / ZTSEL_ENABLE is input at time t1, ZTSEL = Low, and the gain is ZT_H. At time t2, Vc exceeds Vth2 and DATA_DETECT = High is set, and the logic circuit starts time measurement of the gain switching allowable period. At time t3, Vc exceeds Vth1, ZT_SEL = High, and the gain changes to ZT_L. At time t4 = t2 + Tsel_1, the logic circuit sets BURST_RESET / ZTSEL_ENABLE = Low to end the gain switching allowable period, fixes the output High of ZT_SEL at this time, and sets the gain to ZT_L. Note that Tsel_1 is adjusted to end the gain switching allowable period during the reception of SyncPattern.

  At time t5, BURST_RESET / ZTSEL_ENABLE is input, ZTSEL = Low, and the gain is ZT_H. At time t6, Vc exceeds Vth2 and DATA_DETECT = High is set, and the logic circuit starts time measurement of the gain switching allowable period. At time t7, Vc exceeds Vth1, ZT_SEL = High, and the gain changes to ZT_L. At time t8 = t6 + Tsel_2, the gain switching allowable period ends, the output High of ZT_SEL at this time is fixed, and the gain is set to ZT_L. Since Tsel_2 is set based on Ton_2, the gain switching allowable period is ended during the reception of SyncPattern. Since an appropriate gain switching allowable period is set even for a burst with a long Ton, an appropriate gain is selected, and BER deterioration can be prevented.

  At time t9, BURST_RESET / ZTSEL_ENABLE is input, ZTSEL = Low, and the gain is ZT_H. At time t10, Vc exceeds Vth2 and DATA_DETECT = High is set, and the logic circuit starts time measurement of the gain switching allowable period. At time t11 = t10 + Tsel_3, the gain switching allowable period ends, the output Low of ZT_SEL at this time is fixed, and the gain remains ZT_H. Note that since Tsel_3 is set based on Ton_3, the gain switching allowable period ends during the reception of SyncPattern. At time t12, Iin changes during data reception, and Vc exceeds Vth1. At this time, since ZTSEL_ENABLE = Low and gain switching is not allowed, gain switching due to noise does not occur. For this reason, it is possible to prevent waveform deterioration due to gain switching and to prevent BER deterioration.

  As described above, according to the fourth embodiment, it is possible to prevent the deterioration of the BER even when the Ton time is different for each ONU.

[Effects of the fourth embodiment]
In the fourth embodiment, since the functions of the BURST_RESET signal and the ZTSEL_ENABLE signal can be realized by a common signal line, the number of control lines between the transimpedance amplifier and the logic circuit can be reduced, and the circuit can be simplified. it can.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. Description will be made centering on differences from the first embodiment. In the fifth embodiment, the end of the gain switching allowable period is performed by specific pattern detection.

[Configuration of Burst Receiver in Fifth Embodiment]
The configuration of the burst receiver in the fifth embodiment will be described with reference to FIG.
The difference from the first embodiment is that the logic circuit does not maintain the correspondence between the ONU identifier, the Ton time, and the gain switching allowable period, and ends the gain switching allowable period by detecting a specific pattern.

  The logic circuit 84 includes a pattern detection circuit that compares the bit pattern of the upstream signal with a preset pattern and can detect when the number of error bits matches a certain number or less. For example, in 10G-EPON, a pattern detection circuit such as SyncPattern or BurstDelimiter is provided.

[Configuration of Logic Circuit in Fifth Embodiment]
FIG. 24 shows the configuration of the logic circuit 84 in the fifth embodiment of the present invention.
The logic circuit 84 in the fifth embodiment of the present invention includes an upstream frame receiver 801, a downstream frame transmitter 802, an MPCP controller 804, and a burst receiver controller 840.

  The upstream frame reception unit 801 performs decoding, frame analysis, distribution of control signals and user signals, and the like from the digital signal input from SerDes. The control signal is input to the MPCP control unit 804, and the user signal is input to the NNI.

  The downlink frame transmission unit 802 multiplexes the control signal received from the MPCP control unit 804 and the user signal received from the NNI, and inputs the multiplexed signal to SerDes.

  The burst receiver control unit 840 exchanges signals with the MPCP control unit 804, receives a control signal from the burst receiver, determines control of the burst receiver, and generates a control signal for receiver control. The burst receiver controller 840 includes a control signal generator 841 and a pattern detector 842.

  Based on the DATA_DETECT signal input from the burst receiver, the PAT_DETECT signal input from the pattern detection unit 842, and the StartTime signal input from the MPCP control unit 804, the control signal generation unit 841 controls the burst receiver control control signal BURST_RESET. , ZTSEL_ENABLE is generated. Specifically, the pattern detection unit 842 detects a specific pattern composed of Ntotal bits from the digital signal input from SerDes. Specifically, a specific bit pattern and a received bit pattern are compared, and if the number of bit mismatches Nerror is equal to or smaller than a certain number, it is determined that a detection has been made. In the case of 10G-EPON, it may be compared with BurstDelimiter or SyncPattern. In addition, since the OLT logic circuit for 10G-EPON has a BurstDelimiter detection function, the BurstDelimiter detection function can be substituted for the pattern detection unit. Note that values set in advance are used for Ntotal and Nerror.

[Example of operation in the fifth embodiment]
FIG. 25 shows a timing chart showing the operation in the fifth embodiment of the present invention. An operation example of Iin, BURST_RESET, Vc, Vout, ZTSEL_ENABLE, and ZTSEL is shown. Further, it is assumed that burst signals are input in order from ONU # 1, ONU # 2, ONU # 3.

  In the initial state, no signal is input to Iin, and all other control signals are Low.

  BURST_RESET is input at time t1, ZTSEL = Low, and the gain is set to ZT_H. At time t2, Vc exceeds Vth2, ZT_SEL_ENABLE = High is set, and a gain switching allowable period is started. At time t3, Vc exceeds Vth1, ZT_SEL = High, and the gain changes to ZT_L. At time t4, the pattern is detected by the logic circuit, and the gain switching allowable period ends. At this time, the output High of ZT_SEL is fixed, and the gain is set to ZT_L.

  BURST_RESET is input at time t5, ZTSEL = Low, and the gain is set to ZT_H. At time t6, Vc exceeds Vth2, ZTSEL_ENABLE = High, and a gain switching allowable period is started. At time t7, Vc exceeds Vth1, ZT_SEL = High, and the gain changes to ZT_L. At time t8, the pattern is detected by the logic circuit, and the gain switching allowable period ends. At this time, the output High of ZT_SEL is fixed, and the gain is set to ZT_L. Since an appropriate gain switching allowable period is set even for a burst with a long Ton, an appropriate gain is selected, and BER deterioration can be prevented.

  At time t9, BURST_RESET is input, ZTSEL = Low, and the gain is set to ZT_H. At time t10, Vc exceeds Vth2, ZTSEL_ENABLE = High, and a gain switching allowable period is started. At time t11, the logic circuit detects a pattern, and the gain switching allowable period ends. At this time, the output Low of ZT_SEL is fixed, and the gain remains ZT_H. At time t12, Iin changes during data reception, and Vc exceeds Vth1. At this time, since ZTSEL_ENABLE = Low and gain switching is not allowed, gain switching due to noise does not occur. For this reason, it is possible to prevent waveform deterioration due to gain switching and to prevent BER deterioration.

[Effects of the fifth embodiment]
In the fifth embodiment, it is not necessary to maintain the Ton time or calculate the gain switching allowable period for each ONU, and it is possible to set the allowable gain period.

[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described. Description will be made centering on differences from the first embodiment. In the sixth embodiment, the length of the gain switching allowable period is calculated based on the ONU's Ton and SyncTime (burst preamble length). FIG. 26 shows an ONU identifier and gain allowable period management table according to the sixth embodiment. In the management table, each gain allowable period GainSelectTime is calculated by a function F2 (Ton, Tsync). For example, F2 (Ton, Tsync) = Ton + Tsync−γ. γ is a time required for clock recovery and is a constant value regardless of the ONU.

[Configuration of Burst Receiver in Sixth Embodiment]
The configuration of the burst receiver may be the same as in the first, second, third, and fourth embodiments.

[Configuration of Logic Circuit in Sixth Embodiment]
In the ONU-ID / Ton correspondence storage unit, the ONU-ID is changed to hold the correspondence between Ton and SyncTime.

  Moreover, what is necessary is just to change so that it may calculate in Tsel calculation part using Ton and SyncTime.

[Example of operation in the sixth embodiment]
The operation of the receiver is the same as that of the first, second, third, and fourth embodiments except that Tsel is different.

[Effects of the sixth embodiment]
Even in a system in which SyncTime is different for each ONU, an optimum gain switching allowable period can be set.

[Supplement]
In this description, the frame format in 10GE-PON (IEEE802.3av) has been described, but the same applies to the frame format in E-PON (IEEE802.3ah) and G-PON (ITU-T G.984). It can be applied to.
Further, in the present invention, it has been described that there are two types of gain that can be selected.

1 Optical line equipment (OLT)
2-1 to 2-n Optical network equipment (ONU)
3 Optical splitters 4-0 to 4-n Optical fiber 10 Multiplexer / demultiplexer (WDM)
20 Photodiode (Photo Diode, PD)
30, 300, 301, 302, 303, 304, 305, 306, 307 Transimpedance Amplifier (TIA)
40, 41 Limit amplifier (Limiting Amplifier, LA)
50 Laser diode (LD)
60 Driver circuit (Driver)
70 SerDes (Serializer / Deserializer)
80, 81, 82, 83, 84 Logic circuit 90 SNI (Service Node Interface)
31, 311, 312 Gain switching circuit 32, 321, 322 Amplifier circuit 33 Gain switching level detection unit 340 Gain switching determination circuit 341, 342, 343, 344, 345, 346, 347 Gain switching control unit 35 Data detection unit 36 Delay circuit 371, 372 Buffer circuit 38 Gain switching comparator 801 Up frame receiver 802 Down frame transmitter 803, 804 MPCP controller 810, 840 Burst receiver controller 811, 841 Control signal generator 812 ONU-ID, Ton correspondence storage unit 813 Tsel calculation unit 842 pattern detection unit

Claims (15)

Transimpedance amplifier capable of gain switching,
A gain switching level detector for detecting a level for switching the gain of the transimpedance amplifier by comparing the output level of the transimpedance amplifier with a first threshold;
A burst reception control unit for controlling a period during which gain switching is allowed for each burst signal received by the transimpedance amplifier ; and
Based on a control signal from the burst reception control unit, it is determined whether or not gain switching is allowed. During a period when gain switching is allowed, the gain switching of the transimpedance amplifier is performed based on the output of the gain switching level detection unit. And a gain switching control unit for executing the control. A control device (OLT) according to claim 1,
The burst reception control unit
For each received burst signal, determine the start time for allowing gain switching and the length of the period for allowing gain switching,
A control apparatus that controls the gain switching control unit based on the determined start time for permitting gain switching and the length of a period for permitting gain switching. A control device (OLT) according to claim 1,
The burst reception control unit
For each received burst signal, determine a start time that allows gain switching and an end time that allows gain switching,
A control apparatus that controls the gain switching control unit based on the determined start time allowing gain switching and ending time allowing gain switching. A control device (OLT) according to claim 2 or claim 3, wherein
A data detection unit for detecting the start of burst reception by comparing the output level of the transimpedance amplifier and a second threshold;
The control apparatus according to claim 1, wherein the burst reception control unit sets a time at which the data detection unit detects a burst reception start as a start time at which the gain switching is allowed. A control device (OLT) according to claim 2 or claim 3, wherein
Provided with a limit amplifier that amplifies the signal of the transimpedance amplifier,
The limit amplifier includes a data detection unit that detects a burst reception start by comparing the input level or the level after amplification with a third threshold,
The control apparatus according to claim 1, wherein the burst reception control unit sets a time at which the data detection unit detects a burst reception start as a start time at which the gain switching is allowed. A control device (OLT) according to claim 2 or claim 3, wherein
The ONU designates the time to transmit the burst signal, predicts the time to start receiving the burst signal based on the designated ONU transmission time, and inputs the time to start receiving the burst signal to the burst reception control unit An MPCP controller,
The control apparatus according to claim 1, wherein the burst reception control unit determines a start time at which the gain switching is allowed based on a time at which reception of the burst signal input from the MPCP control unit is started. A control device (OLT) according to claim 2,
An MPCP control unit that manages the laser rise time and ONU identifier of each ONU notified from the ONU;
A storage unit that stores a laser rise time and an ONU identifier of each ONU; an MPCP control unit that writes the laser rise time and the ONU identifier of each ONU notified from the ONU to the storage unit;
Calculating a period allowing the gain switching from a laser rise time of the ONU read from the storage unit, and inputting the calculated period allowing the gain switching to the burst reception control unit; Prepared,
The burst reception control unit sets a period for allowing gain switching input from the calculation unit as a length of a period for allowing the gain switching. A control device (OLT) according to claim 2,
A storage unit for storing the laser rise time, SyncTime, and ONU identifier of each ONU;
An MPCP controller that manages the ONU laser rise time notified from each ONU, the ONU identifier, and the burst preamble length transmitted by the ONU, and writes the ONU laser rise time, burst preamble length, and ONU identifier to the storage unit;
A calculation unit that calculates a period during which gain switching is allowed from the laser rise time of the ONU and the burst preamble length, and inputs the period during which the calculated gain switching is allowed to the burst reception control unit, and
The burst reception control unit sets a period for allowing gain switching input from the calculation unit as a length of a period for allowing the gain switching. A control device (OLT) according to claim 3,
A limit amplifier that amplifies the output signal of the transimpedance amplifier;
A clock data recovery circuit that performs clock extraction and retiming from the output signal of the limit amplifier, and outputs a digital signal;
The digital signal of the clock data recovery circuit is compared with a specific bit pattern sequence composed of N bits, and it is determined that a pattern is detected when the number of mismatched bits is equal to or less than a certain number, and the pattern is transmitted to the burst reception control unit. A pattern detection circuit for inputting a detection result,
The burst reception control unit determines an end time at which the gain switching is allowed based on a pattern detection result input from the pattern detection circuit. A control device (OLT) according to claim 2,
A storage unit for storing the laser rise time and ONU identifier of each ONU;
The burst reception control unit controls the switching of the gain by using a preset gain switching allowable period length for a burst signal transmitted by the ONU whose rise time of the ONU is not stored in the storage unit. A control device characterized by: A control device (OLT) according to claim 7,
The storage unit stores an unregistered ONU identifier and an ONU laser rise time,
For the burst signal transmitted by the ONU whose ONU laser rise time is not held in the storage unit, the calculation unit burst-receives the gain switching allowable period calculated using the ONU laser rise time of the unregistered ONU. Input to the control unit,
The burst reception control unit controls gain switching using an input gain switching allowable period. A control device (OLT) according to claim 1,
The gain switching control unit has a reset input,
The burst reception control unit outputs a reset signal for resetting the gain switching control unit, and outputs a reset every time a burst signal is received. A control device (OLT) according to claim 12,
The gain switching control unit
Upon detecting a reset signal from the burst reception control unit, a signal for setting the gain of the transimpedance amplifier to the first gain is output,
When a gain switching signal is received from the gain switching level detector during the gain switching allowable period, a signal for setting the gain of the transimpedance amplifier to a second gain lower than the first gain is output to the transimpedance amplifier,
Once a signal for setting the gain of the transimpedance amplifier to the second gain is output, a signal for setting the gain of the transimpedance amplifier to the second gain is detected until a reset signal from the burst reception control unit is detected. A control device for outputting to the transimpedance amplifier. A network system including a control device (OLT) and a terminal device (ONU),
The ONU notifies the OLT of the rise time of the transmitter during ONU registration,
The control device (OLT)
Transimpedance amplifier capable of gain switching,
A gain switching control unit for controlling the gain switching of the transimpedance amplifier;
A gain switching level detector for detecting a level at which gain switching is performed by comparing an output level of the transimpedance amplifier with a first threshold;
A burst reception control unit for controlling a period during which gain switching is allowed in the gain switching control unit;
An MPCP controller for controlling ONU transmission, and
A storage unit that holds a correspondence between the ONU identifier and the length of the gain switching allowable period determined based on the rise time of the transmitter notified from the ONU;
A calculation unit for determining a length of a gain switching allowable period based on an ONU identifier received next notified from the MPCP control unit,
The burst reception control unit controls the transimpedance gain switching allowable period based on the gain switching allowable period determined by the calculation unit. A system composed of a control device (OLT) and a terminal device (ONU),
The ONU notifies the OLT of the rise time of the transmitter during ONU registration,
The control device (OLT)
Transimpedance amplifier capable of gain switching,
A gain switching control unit for controlling the gain switching of the transimpedance amplifier;
A gain switching level detector for detecting a level at which gain switching is performed by comparing an output level of the transimpedance amplifier with a first threshold;
A burst reception control unit for controlling a period during which gain switching is allowed in the gain switching control unit, and an MPCP control unit for controlling ONU transmission;
A storage unit that holds correspondence between an ONU identifier, a burst preamble length at the time of ONU transmission, a rise time of a transmitter notified from the ONU, and a length of a gain switching allowable period determined based on the burst preamble length When,
A calculation unit for determining a length of a gain switching allowable period based on an ONU identifier received next notified from the MPCP control unit,
The burst reception control unit controls the transimpedance gain switching allowable period based on the gain switching allowable period determined by the calculation unit.

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