JP4082207B2 - Frequency synthesizer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a frequency synthesizer.
[0002]
[Prior art]
A conventional frequency synthesizer will be described below. As shown in FIG. 5, the conventional frequency synthesizer includes a voltage controlled oscillator 1 whose oscillation frequency is controlled by a control voltage, an output terminal 2 to which the output of the voltage controlled oscillator 1 is connected, and an output of the voltage controlled oscillator 1. Are connected to each other and the frequency divider 4 can be changed by the microcomputer 3, and the output of the frequency divider 4 is connected to one input and the output of the reference oscillator 5 is connected to the other input. A phase comparator 7 connected via a frequency divider 6, a charge pump 8 connected to the output of the phase comparator 7, and a connection between the output of the charge pump 8 and the input of the voltage controlled oscillator 1. And the low-pass filter 9 thus made.
[0003]
The operation of the frequency synthesizer configured as described above will be described below. First, the frequency division ratio between the frequency divider 6 and the frequency divider 4 is set as follows so that the frequency to be output from the output terminal 2 is obtained. That is, the frequency division ratio of the frequency divider 6 is set so that the frequency output from the reference oscillator 5 by the microcomputer 3 becomes a predetermined reference comparison frequency. Next, the frequency division ratio of the frequency divider 4 is set. Then, the oscillation output output from the voltage controlled oscillator 1 is divided by the frequency divider 4, the output is compared with the reference comparison frequency by the phase comparator 7, and the difference signal is supplied to the charge pump 8. . The charge pump 8 supplies a charge / discharge current proportional to the difference signal to the low-pass filter 9. The low pass filter 9 generates a voltage proportional to the charge / discharge current and supplies it to the voltage controlled oscillator 1.
[0004]
In other words, the phase comparator 7 controls the reference comparison frequency output from the frequency divider 6 and the frequency output from the frequency divider 4 to be equal. By appropriately setting the division ratio of 6, a desired frequency can be obtained from the output terminal 2.
[0005]
Here, reference numeral 10 denotes a switch composed of an electronic circuit, which controls the charge / discharge current generated by the charge pump 8. This is for shortening the frequency switching time. At the time of switching, the switch 10 is turned on by the unlock signal output from the phase comparator 7 to increase the charge / discharge current, thereby switching the frequency. That is, the lockup time is shortened.
[0006]
As prior art document information related to the invention of this application, for example, Patent Document 1 is known.
[0007]
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-261606
[Problems to be solved by the invention]
However, since such a conventional frequency synthesizer uses the unlock signal output from the phase comparator 7, a lock-up time is required until the frequency output from the voltage controlled oscillator 1 settles in a steady state. Therefore, there is a problem that a certain amount of time is necessary. In addition, since the charging / discharging current greatly changes at the end of the switching time, there is a problem that an unstable region is inevitably generated immediately after the switching, and the switching time becomes longer.
[0009]
SUMMARY OF THE INVENTION The present invention solves this problem and aims to provide a frequency synthesizer with a short switching time.
[0010]
[Means for Solving the Problems]
In order to achieve this object, the frequency synthesizer of the present invention is provided with a switch capable of increasing the charge / discharge current generated by the charge pump when the enable signal is high , and the frequency dividing ratio of the frequency divider is changed by the switching means. when switching the in the lock-up time for the output of the voltage controlled oscillator settles to a steady state, the charge-discharge current value to the low pass filter of the charge pump to the time the enable signal is high, twice than the steady state The high time of the enable signal has a length proportional to the difference between the frequency before switching the output frequency output from the voltage controlled oscillator and the frequency after switching. Thereby, the switching time can be shortened.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
According to a first aspect of the present invention, a voltage controlled oscillator whose oscillation frequency is controlled by a control voltage, an output terminal to which an output of the voltage controlled oscillator is connected, and an output of the voltage controlled oscillator are connected. In addition, a divider capable of changing the division ratio by a clock signal, a data signal, and an enable signal output from the switching means, and the output of the divider is connected to one input and the other input is a reference A phase comparator to which an output of the oscillator is supplied; a charge pump to which the output of the phase comparator is connected; and a low-pass filter connected between the output of the charge pump and the input of the voltage controlled oscillator. the switch capable of increasing the charge and discharge current the enable signal is generated by the charge pump in the high time provided, the frequency divider in said switching means When switching the dividing ratio, in said voltage controlled oscillator lock-up time the output to settle to steady state, the charge-discharge current value to the low pass filter of the charge pump to the enable signal is high time constant always than, twice the time of high of the enable signal is a frequency synthesizer and a length of which is proportional to the difference in frequency after switching the frequency before switching of the output frequency output from the voltage controlled oscillator, the charge and discharge current Since the time for increasing can be controlled using the enable signal, the switching time can be shortened.
[0012]
In addition, since the enable signal is used, it is not necessary to provide a special signal line. Furthermore, the switching means can be easily programmed and the number of output terminals is not increased.
[0013]
Furthermore, the switching time can be controlled to the shortest time according to the difference in switching frequency.
[0014]
In addition, the switching time can be shortened while maintaining the steady state C / N in good condition and stabilizing the voltage controlled oscillator within the switching time.
[0015]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a frequency synthesizer according to the present invention. A voltage controlled oscillator 21 whose oscillation frequency is controlled by a control voltage, an output terminal 22 to which an output of the voltage controlled oscillator 21 is connected, and a voltage controlled oscillator 21. And a frequency divider 24 whose frequency division ratio can be changed by a microcomputer 23 (used as an example of a switching means), and an output of the frequency divider 24 is connected to one input. The other input has a phase comparator 27 to which the output of the reference oscillator 25 is connected via a frequency divider 26, a charge pump 28 to which the output of the phase comparator 27 is connected, and an output of the charge pump 28. It comprises a low-pass filter 29 connected between the input of the voltage controlled oscillator 21.
[0016]
Here, the reference oscillator 25 is a 16.8 MHz TCXO. In this embodiment, 31 is a 4.7 k ohm resistor that controls the charge / discharge current of the charge pump 28, and 32 is a 4.7 k ohm resistor connected in series with the switch 30 formed of an electronic circuit. It is. When the switch 30 is off, the charge / discharge current is approximately 0.29 mA, and when the switch 30 is turned on, the charge / discharge current is approximately 0.58 mA.
[0017]
The low pass filter 29 includes a 10 k ohm resistor 33 connected between its input and output, and a 330 p Farad capacitor 34 connected between the resistor 33 and the connection point of the voltage controlled oscillator 21 and the ground. , A 3.9 n Farad capacitor 35 connected between the connection point of the resistor 33 and the charge pump 28 and the ground, and a 0.33 k ohm resistor 36 and a 68 n Farad capacitor 37 connected in parallel with the capacitor 35. And a series connection body.
[0018]
The microcomputer 23 outputs a clock signal 38, a data signal 39, and an enable signal 40 as shown in FIG. 2, and controls the frequency division ratio of the frequency divider 24. The enable signal 40 also controls on / off of the switch 30. That is, after the clock signal 38 and the data signal 39 are output, the switch 42 is turned on when the enable signal 40 is H (high) to increase the charge / discharge current. By controlling the length of the time 42 with the microcomputer 23, the charge / discharge current increase time can be controlled.
[0019]
The clock signal 38 and the data signal 39 are also connected to the frequency divider 26. Reference numeral 41 denotes an enable signal connected to the frequency divider 26, which controls the frequency division ratio of the frequency divider 26 using these signals to generate a reference comparison frequency. Here, when the frequency dividers 24 and 26 are configured by the same register, the enable signals 40 and 41 can be shared. Therefore, in this case, there is one enable signal.
[0020]
By such control, the output terminal 22 outputs a frequency of about 900 MHz to 1060 MHz.
[0021]
The operation of the frequency synthesizer configured as described above will be described below. First, the frequency division ratio of the frequency divider 26 and the frequency divider 24 is set as follows so that the frequency to be output from the output terminal 22 is obtained. That is, the frequency division ratio of the frequency divider 26 is set so that the frequency output from the reference oscillator 25 by the microcomputer 23 becomes a predetermined reference comparison frequency. Next, the frequency division ratio of the frequency divider 24 is set. Then, the oscillation output output from the voltage controlled oscillator 21 is divided by the frequency divider 24, the output is compared by the reference comparison frequency and the phase comparator 27, and the difference signal is supplied to the charge pump 28. . The charge pump 28 supplies a charge / discharge current proportional to the difference signal to the low-pass filter 29. The low pass filter 29 generates a voltage proportional to the charge / discharge current and supplies it to the voltage controlled oscillator 21.
[0022]
That is, the phase comparator 27 controls the reference comparison frequency output from the frequency divider 26 and the frequency output from the frequency divider 24 to be equal. A desired frequency can be obtained from the output terminal 22 by appropriately setting the frequency division ratio of 26.
[0023]
Here, the charge / discharge current generated by the charge pump 28 is controlled using the enable signal 40 output from the microcomputer 23.
[0024]
This is for shortening the frequency switching time, that is, the lock-up time. At the time of switching, the switch 30 is turned on (time 42 in FIG. 2) to increase the charging / discharging current, that is, the frequency switching time, The lock-up time is shortened.
[0025]
Here, the relationship between charge / discharge time and stability will be described with reference to FIG. In FIG. 3, the vertical axis 45 represents the stability of the control voltage at the input of the voltage controlled oscillator 21, and the horizontal axis 46 represents time.
[0026]
FIG. 3A shows the characteristics when the length of the enable signal 40 (ON time 42) is controlled to increase the charge / discharge current increase time to 5 microseconds, and approximately 430 microseconds until the stable point 47 is reached. It depends. On the other hand, FIG. 3B shows a case where the length of the enable signal 40 (ON time 42), that is, the charge / discharge current increase time is controlled to 120 microseconds. In this case, the stable point 48 is reached in 260 microseconds. Further, as shown in FIG. 3C, when the length of the enable signal 40 (ON time 42) is set to 300 microseconds, it is once stabilized at a time 49 per 260 microseconds. However, when the charging / discharging current increase time ends, the abrupt change of the charging / discharging current occurs, so that an unstable region 51 appears once, and eventually it takes approximately 360 microseconds until the stable point 52 is reached. Thus, the switching time can be minimized by appropriately selecting the charging / discharging current increase time.
[0027]
If the charge / discharge current is not switched at the time of frequency switching, it is considered that the characteristic is as shown in FIG. Further, when switching is performed using an unlock signal as in the conventional example, it is assumed that the result is as shown in FIG. The characteristic of FIG. 3B is shown when approximately 0.58 mA is applied when the charge / discharge current is increased. At this time, in a steady state, the current is reduced to about 0.29 mA, which is half, so that the C / N characteristic is improved. Thus, setting the charging / discharging current at the time of charging / discharging to approximately twice the steady current is important for shortening the lockup time while maintaining good C / N.
[0028]
FIG. 4 is a characteristic diagram when the frequency is switched. The horizontal axis 55 is time, and the vertical axis 56 is frequency. FIG. 4A shows characteristics when the frequency is changed from the frequency 57 to the frequency 58, and the change time 59 is short. On the other hand, as shown in FIG. 4B, when the frequency difference for switching from the frequency 60 to the frequency 61 increases, the change time 62 becomes longer. Therefore, if the length proportional to the difference in frequency for switching the charging / discharging current increase time is controlled, the frequency can be switched in the shortest time.
[0029]
【The invention's effect】
As described above, according to the present invention, when the switch capable of increasing the charge / discharge current generated by the charge pump in the time when the enable signal is high is provided and the frequency dividing ratio of the frequency divider is switched by the switching means. in the lock-up time for the output of the voltage controlled oscillator settles to a steady state, the charge-discharge current value to the low pass filter of the charge pump to the time the enable signal is high, twice than the steady state, the enable signal The high time is set to a length proportional to the difference between the frequency before switching of the output frequency output from the voltage controlled oscillator and the frequency after switching.
[0030]
Thus , the charge / discharge current value to the low-pass filter of the charge pump is increased when the enable signal is high, and the high time of the enable signal is the frequency before switching the output frequency output from the voltage controlled oscillator. Since the length is proportional to the frequency difference after switching, the switching time can be shortened.
[0031]
In addition, since the enable signal is used, it is not necessary to provide a special signal line. Furthermore, the switching means can be easily programmed and the number of output terminals is not increased.
[Brief description of the drawings]
1 is a block diagram of a frequency synthesizer in an embodiment of the present invention. FIG. 2 is a signal waveform diagram of a control signal supplied to a frequency divider. FIG. 3A is a voltage controlled oscillator. First signal waveform diagram of input signal (b) Same as above, second signal waveform diagram (c) Same as above, third signal waveform diagram [FIG. 4] (a) Same as above, output from voltage controlled oscillator FIG. 5B is a second frequency characteristic diagram of the signal to be transmitted. FIG. 5 is a block diagram of a conventional frequency synthesizer.
21 Voltage Control Oscillator 22 Output Terminal 23 Microcomputer 24 Frequency Divider 25 Reference Oscillator 27 Phase Comparator 28 Charge Pump 29 Low Pass Filter 30 Switch 31 Resistor 32 Resistor

Claims (1)

A voltage-controlled oscillator whose oscillation frequency is controlled by a control voltage, an output terminal to which the output of the voltage-controlled oscillator is connected, a clock signal and a data signal that are connected to the output of the voltage-controlled oscillator and output from the switching means A frequency divider capable of changing a frequency division ratio by an enable signal; a phase comparator in which an output of the frequency divider is connected to one input and an output of a reference oscillator is supplied to the other input; A charge pump to which the output of the phase comparator is connected; and a low-pass filter connected between the output of the charge pump and the input of the voltage controlled oscillator; and the charge pump when the enable signal is high. in a switch capable of increasing the charge and discharge current generated when switching the dividing ratio of the frequency divider by said switching means, said voltage In the lock-up time for the output of the controlled oscillator settles to a steady state, the charge-discharge current value to the low pass filter of the charge pump to the time the enable signal is high, twice than the steady state, the enable signal A frequency synthesizer in which the high time is a length proportional to the difference between the frequency before the switching of the output frequency output from the voltage controlled oscillator and the frequency after the switching.

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