JP2002100962A - Frequency-characteristic adjusting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency-characteristic adjusting circuit, which does not require a large-capacitance capacitor and which can deal with an intermittent operation by a method, where a signal processing circuit and a correction circuit are installed inside the same chip, the capacitance value of a variable capacitance circuit in the signal processing circuit is controlled, so as to be interlocked with the capacitance value of a reference capacitance circuit, the characteristic of the signal processing circuit is changed, by changing the capacitance value of the reference capacitance circuit and the frequency characteristic, such as the cutoff frequency or the like of a filter circuit can be controlled. SOLUTION: The frequency-characteristic adjusting circuit 2 is provided with the reference capacitance circuit 6 and a body circuit 23, whose capacitance value is changed so as to be interlocked with the capacitance value of the circuit 6. When the correction circuit 10 controls the capacitance value in such a way that the circuit 6 becomes a prescribed frequency characteristic, the body circuit 23 is set at a desired frequency characteristic. In this case, an oscillation circuit 5 which is oscillated at a frequency according to the capacitance value of the circuit 6 is installed, and the capacitance value of the circuit 6 is controlled in such a way that its oscillation frequency becomes a definite value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for correcting a capacitance value of a circuit having a capacitor such as a filter.
In particular, it relates to a circuit for correcting a capacitance value using digital technology.

[0002]

2. Description of the Related Art Conventionally, a correction circuit has been used to correct a characteristic variation of a filter due to a manufacturing error. Reference numeral 110 in FIG. 5 is an example of a conventional filter circuit. The filter circuit 110 includes the correction circuit 10
0 and a main circuit 131.

[0003] The correction circuit 100 includes first and second phase shift circuits 101 and 102, a phase comparator 103, a capacitor 104, and an amplifier 105.

[0004] Reference numeral 136 denotes a clock circuit. The reference clock signal generated by the clock circuit 136 is supplied to the phase comparator 103 and the first phase shift circuit 101.
Is entered.

First and second phase shift circuits 101, 10
2 are connected in series, and the second phase shift circuit 102
Are input to the phase comparator 103.

First and second phase shift circuits 101 and 10
2 has first and second constant current circuits 111 and 121, first and second amplifiers 112 and 122, and first and second capacitors 113 and 123, respectively.
The input signal is delayed for a predetermined time by the resistive components of the second constant current circuits 111 and 121, the first and second amplifiers 112 and 122, and the capacitances of the first and second capacitors 113 and 123. And delay circuits for outputting the signals.

Accordingly, the reference clock signal input to the first phase shift circuit 101 is sequentially delayed by the first and second phase shift circuits 101 and 102, and the phase comparator 103
Is input to

[0008] The phase comparator 103 compares the phase of the reference clock signal with the phase of the delayed reference clock signal, and outputs a phase difference to the amplifier 105.

A capacitor 1 is connected to the input terminal of the amplifier 105.
The high frequency component is removed by the capacitor 104, and the DC component of the output signal of the phase comparator 103 is input to the amplifier 105. The amplifier 105 amplifies the input signal and outputs the first and second constant current circuits 11.
1, 121 and the main circuit 131.

First and second phase shift circuits 101, 10
2 has first and second constant current circuits 111, 1
21 and the resistances of the first and second amplifiers 112 and 122 and the capacitances of the first and second capacitors 113 and 123. Here, the first and second phase shift circuits 101 and 122 It is assumed that the frequency characteristic of 102 is set so as to delay the input signal by 45 °.

Accordingly, a reference clock signal and a signal obtained by delaying the reference clock signal by 90 ° are input to the phase comparator 103. In this case, a signal having no phase error is output from the phase comparator 103. Is output, and the main body circuit 131 is output.
The constant current circuit 134 supplies a current of a preset value to the amplifier 132.

When the magnitude of the resistance component in the constant current circuits 111 and 121 and the capacitance values of the capacitors 113 and 123 change when the correction circuit 100 is affected by temperature fluctuations, the first and second phase shift circuits The delay times of 101 and 102 deviate from 45 °. As a result, the phase comparator 103
, A reference clock signal and a reference clock signal delayed by a delay time other than 90 ° are input, so that a phase difference occurs in the input signal.

In the correction circuit 100, the signal output from the amplifier 105 is divided into first and second constant current circuits 111,
It is configured such that the amount of current supplied to the first and second amplifiers 112 and 122 is controlled by a signal input to the amplifier 121 and input from the amplifier 105.

First and second phase shift circuits 101, 10
When the delay time of 2 deviates from 45 °, the phase comparator 10
3 outputs a signal corresponding to the shift amount, and the signal is
The first and second constant current circuits 11 via the amplifier 105
1, 121.

The amplifier 105 controls the amount of current supplied by the constant current circuits 111 and 121 so as to reduce the amount of deviation. 1, second phase shift circuits 101 and 102
Is maintained constant.

The first and second constant current circuits 111 and 12
The signal for controlling the amount of current 1 is also output to the main circuit 131.

The main circuit 131 has an amplifier 132, a capacitor 133, and a constant current circuit 134. The amplifier 132 operates by the current supplied from the constant current circuit 134, The input AC signal is configured to be amplified and output from an output terminal to another circuit 138.

The output terminal of the amplifier 132 has a capacitor 1
33, a constant current source 134 and an amplifier 132
And the capacitance of the capacitor 133 constitute a low-pass filter.

A signal for controlling the amount of current of the first and second constant current circuits 111 and 121 is input to the constant current circuit 134 of the main circuit 131. Therefore, the constant current circuit 134
The frequency characteristic is controlled together with the first and second constant current circuits 111 and 121, and the amount of current supplied to the amplifier 132 is controlled.

In this case, the first and second constant current circuits 11
1 and 121 are controlled so that a predetermined frequency characteristic is maintained even when the resistance component and the capacitance value fluctuate. Therefore, by controlling the constant current circuit 134 in the main body circuit 131, the main body 1 and the main body 121 are controlled. The circuit 131 also has the same frequency characteristics as when there is no change in the resistance component or the capacitance value.

As described above, the frequency characteristics of the main circuit 131 are controlled together with the frequency characteristics of the correction circuit 100, and the effects of temperature fluctuations and process variations are eliminated.

However, the correction circuit 10 as described above
If 0 is to be used in a TDMA filter circuit that requires intermittent operation, it is necessary to arrange a capacitor for holding a DC voltage at the input terminal of the filter circuit.

The capacitor can be replaced by the capacitor 104 in the stage preceding the amplifier 105 of the correction circuit 100. However, since a large capacity is required, a capacitor having a large area is formed.

On the other hand, the DC voltage is converted into a digital value,
Although it is possible to hold the data digitally, an AD converter and a DA converter are required in this case.

[0025]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned disadvantages of the prior art, and has as its object to provide a filter circuit which does not require a large-capacity capacitor and can cope with intermittent operation. And the like.

[0026]

According to a first aspect of the present invention, there is provided a variable capacitance circuit having a variable capacitance circuit, wherein a predetermined signal is input, and a capacitance of the variable capacitance circuit is supplied to the input signal. A signal processing circuit for performing predetermined processing according to a value, an oscillation circuit having a reference capacitance circuit, and outputting an oscillation signal having a frequency corresponding to the capacitance value of the reference capacitance circuit, and a counter circuit for counting the oscillation signal A comparator that compares the count value with a predetermined value and outputs the comparison result; a capacitance value of a variable capacitance circuit of the signal processing circuit and a capacitance of a reference capacitance circuit of the oscillation circuit based on the comparison result And a correction circuit having a control circuit for controlling the value and a frequency characteristic adjustment circuit. The invention according to claim 2 is the frequency characteristic adjustment circuit according to claim 1, wherein the counter circuit includes an AND element that inputs a reference clock signal and the oscillation signal.
A circuit for receiving the output of the AND element and counting the number of waves of the oscillation signal. The invention according to claim 3 is the frequency characteristic adjustment circuit according to claim 1 or 2, wherein the variable capacitance circuit of the signal processing circuit and the reference capacitance circuit of the oscillation circuit each include a transistor between two nodes. And the control circuit controls the conduction state of each of the transistors to change the capacitance values of the variable capacitance circuit and the reference capacitance circuit. The invention described in claim 4 is the invention according to claim 1, 2 or 3.
Wherein the signal processing circuit is a filter circuit, and the frequency characteristic is controlled by a capacitance value of the variable capacitance circuit. According to a fifth aspect of the present invention, in the frequency characteristic adjusting circuit of the first, second or third aspect, the signal processing circuit is a delay circuit, and the amount of delay is controlled by a capacitance value of the variable capacitance circuit. Is done.

The frequency characteristic adjusting circuit of the present invention is configured as described above, and its signal processing circuit (main circuit) is used for a filter circuit such as a low-pass filter.

The signal processing circuit and the correction circuit of the frequency characteristic adjusting circuit of the present invention are provided in the same chip. Therefore, the signal processing circuit and the correction circuit are also affected by variations in resistance value and capacitance value due to process variations, and also due to temperature changes.

A variable capacitance reference capacitance circuit is provided in the correction circuit, and the capacitance value of the variable capacitance circuit of the signal processing circuit is controlled in conjunction with the capacitance value of the reference capacitance circuit. Therefore, the characteristics of the signal processing circuit can be changed by changing the capacitance value of the reference capacitance circuit, so that the frequency characteristics such as the cutoff frequency of the filter circuit can be controlled.

As an example of changing the capacitance value of the reference capacitance circuit, an oscillating circuit oscillating at a frequency corresponding to the capacitance value of the reference capacitance circuit and a signal output by the oscillating circuit within a predetermined time are provided in the correction circuit. A counter circuit that counts the wave number and outputs a count value, a comparator that compares the input count value with a predetermined value, and outputs a comparison result indicating a magnitude, and the count value is based on the comparison result. A control circuit for changing the capacitance value of the reference capacitance circuit so as to match the value is provided.

As described above, even when there is a change in the capacitance value or the resistance value due to the temperature change or the process change, the capacitance value of the reference capacitor circuit is changed so as to cancel the change, and the variable capacitor circuit of the signal processing circuit is changed. Is changed in conjunction with the capacitance value of the reference capacitance circuit.

For example, in order to cancel the fluctuation of the resistance value,
When the capacitance value of the reference capacitance circuit increases, the capacitance value of the variable capacitance circuit of the signal processing circuit also increases. Conversely, when the capacitance value of the reference capacitance circuit decreases, the capacitance value of the variable capacitance circuit of the signal processing circuit also decreases. The capacitance value of the variable capacitance circuit of the signal processing circuit is automatically corrected, and its frequency characteristic is kept constant.

A plurality of capacitors are provided in the reference capacitance circuit and the variable capacitance circuit.
By connecting a switch such as a transistor and switching the state of the switch, the capacitance value can be changed. In this case, since the capacitance value is changed digitally,
The circuit configuration for changing the capacitance value is simplified.

[0034]

FIG. 1 shows an example in which a frequency characteristic adjusting circuit 2 of the present invention is applied to a filter circuit. The filter circuit 2 (frequency characteristic adjustment circuit 2) includes a correction circuit 1
0 and a main circuit 23. The correction circuit 10 includes an AC signal generation source 11, a counter circuit 12, a comparator 13, a control circuit 14, and a setting circuit 16.

FIG. 2 shows the internal circuit of the AC signal source 11. The AC signal generation source 11 includes an oscillation circuit 5, a reference capacitance circuit 6, and a constant current circuit 8. Oscillation circuit 5
Has a pair of oscillation transistors 55 and 56 composed of NPN transistors, a pair of resistance elements 57 and 58, and an amplifier 59.

One end of each of the pair of resistance elements 57 and 58 is connected to the power supply voltage line 45, and the other end is connected to the collector terminals of the oscillation transistors 55 and 56, respectively.

The base terminals of the pair of oscillation transistors 55 and 56 are connected to the other oscillation transistors 55 and 5 respectively.
6 is connected to the collector terminal. In this configuration, when one of the pair of oscillation transistors 55 and 56 is conductive, the other is cut off.

The constant current circuit 8 is connected to the emitter terminals of the oscillation transistors 55 and 56. The constant current circuit 8 is a current mirror circuit including NPN transistors 81 to 83 and balance resistors 84 to 86. When a constant current is supplied from the current source 80 to the diode-connected NPN transistor 81. , The other NPN transistors 82 and 83 sink current of the same magnitude as the constant current from the oscillation transistors 55 and 56, respectively.
Each of the oscillation transistors 55 and 56 is operated.

A reference capacitance circuit 6 is connected between the emitter terminals of the pair of oscillation transistors 55 and 56. As described later in detail, a plurality of capacitors are provided in the reference capacitance circuit 6 and have a capacitance component.

When one of the pair of oscillation transistors 55 and 56 conducts, the capacitance component of the reference capacitance circuit 6 becomes
It is charged by the oscillating transistor that is conducting. When the reference capacitance circuit 6 is charged, the voltage of the emitter terminal of the conductive oscillation transistor increases.

Here, the oscillation transistor 55 at the left position in the drawing is conducting, and the oscillation transistor 56 at the right position is
Is turned off, the capacitance component of the reference capacitance circuit 6 is charged, so that the voltage at the emitter terminal of the conductive oscillation transistor 55 rises to near the voltage at the base terminal, and the oscillation transistor 55 It shuts off, and the voltage at the collector terminal of the oscillation transistor 55 rises.

Since the voltage of the collector terminal is connected to the base terminal of the cut-off oscillation transistor 56 at the right side of the drawing, the cut-off oscillation transistor 56
Turns on and charges the capacitance component of the reference capacitance circuit 6 to the opposite polarity.

As a result of the charging, the voltage at the emitter terminal of the oscillation transistor 56, which has been turned on, rises at the right position in the drawing, as described above. When the voltage at the emitter terminal rises to near the voltage at the base terminal, the oscillation transistor 56 changes from conduction to cutoff.

As described above, the pair of oscillation transistors 5
5, 56 can maintain the conductive state only during the period when the capacitance component of the reference capacitance circuit 6 is charged and the voltage of the emitter terminal rises to near the voltage of the base terminal. As a result, the pair of oscillation transistors 55 and 56 are periodically and alternately turned on for the charging time of the reference capacitance circuit 6, that is, the time determined by the capacitance value of the reference capacitance circuit 6 and the current value drawn by the constant current circuit 8. I do.

The collector terminals of the oscillation transistors 55 and 56 are connected to the input terminal of the amplifier 59. When the pair of oscillation transistors 55 and 56 are turned on alternately and an AC signal appears at the collector terminal, the AC signal is output. Is the amplifier 5
9 and output to the counter circuit 12.

In the counter circuit 12, an AND element 21
, A stepping circuit 22 is arranged, and an AC signal output from the amplifier 59 of the AC signal generation source 11 and a reference clock signal output from the reference clock generator 25 are input to the AND element 21. I have. The AND circuit 21 outputs a pulse to the stepping circuit 22 when the logical value of the clock signal matches the logical value of the AC signal.

The signal generated in the AC signal source 11 and
The AC signal input to the circuit 21 is set to have a higher frequency than the reference clock signal.
A pulse is output from the D circuit 21.

Reference numeral 28 in FIG. 1 indicates a reset terminal, and the correction circuit 10 starts operating in response to a signal input to the reset terminal.
The number of pulses input from 1 is counted. Then, the number of pulses counted during the predetermined time is output to the comparator 13.

The setting circuit 16 is connected to the comparator 13. The setting circuit 16 stores a predetermined number of reference pulses set in advance. The reference pulse number and the pulse number counted by the step-up circuit 22 are input to the comparator 13. The comparator 13 compares the reference pulse number with the counted pulse number, and The comparison result shown is output to the control circuit 14.

The control circuit 14 is configured to control the capacitance value of the reference capacitance circuit 6 in the AC signal source 11, as will be described later. If it indicates that the number of pulses is smaller than the reference pulse number, the capacitance component of the reference capacitor circuit 6 in the AC signal source 11 is reduced, and conversely, the number of counted pulses is larger than the reference pulse number. If so, the capacitance component of the reference capacitance circuit 6 is increased.

When the capacitance of the reference capacitance circuit 6 decreases, the oscillation frequency of the AC signal source 11 increases, and when the capacitance increases, the oscillation frequency decreases. As a result, the frequency of the AC signal generation source 11 is stabilized at a constant magnitude based on the number of reference pulses set in the setting circuit 16.

Referring to FIG. 2, the configuration of the reference capacitance circuit 6 and a method of controlling the capacitance will be described. The reference capacitance circuit 6 has a plurality of unit capacitance circuits. Here, four unit capacitance circuits are provided, and reference numerals 3 are used in descending order of capacitance value.
Numbers 0 ₁ to 30 ₄ are assigned to form _first to _fourth unit capacitance circuits.

[0053] The first unit capacity circuit 30 ₁ of the maximum capacity,
The _second to _fourth unit capacitance circuits 302 to 304 are configured by a MOS transistor 42.
To 47 and capacitors 62 to 67 in series.

Both ends of the capacitor 61 of each _first unit capacitance circuit 301 and the _second to _fourth unit capacitance circuits 302 to 304
Both ends of the series connection circuit are connected between the emitter terminals of a pair of oscillation transistors 55 and 56, respectively.

Each of the capacitors 61 to 67 is mounted on a semiconductor element.
Two-layer electrodes formed on the substrate and insulation located between the electrodes
And a second to fourth unit capacitance circuit comprising a conductive thin film
30 _Two~ 30_FourCapacitors 62 to 67 connected in parallel within
Is different between the electrode on the lower side of the thin film and the electrode on the surface side of the thin film.
Connected to the emitter terminals of the oscillation transistors 55 and 56
Have been. That is, for example, the second unit capacitance circuit 30_TwoInside
One of the two capacitors 62 and 63
The electrode on the lower side of the thin film among the electrodes constituting the
The emitter terminal of the oscillation transistor 55 is
The electrode on the front side of the thin film is connected through a transistor 42
Is the emitter terminal of the oscillation transistor 56 on the right side of the drawing.
When the other capacitor 63 is connected to
The electrode on the lower side of the film is the oscillation transistor 56 on the right side of the drawing.
Connected via the MOS transistor 43 to the emitter terminal of
The electrode on the surface side of the thin film is
It is connected to the emitter terminal of the transistor 55.

According to this configuration, each of the capacitors 62 to 6
The effect of the parasitic capacitance formed between the substrate below the thin film 7 and the substrate is evenly distributed to the two oscillation transistors 55 and 56.

The MOS transistors 42 to 47 in the _second to _fourth unit capacitance circuits 302 to 304 have a common gate terminal for each MOS transistor connected in parallel, and are connected to the control circuit 14. .

Accordingly, the second to fourth unit capacitance circuits 30 ₂
In 30 within _4, parallel-connected MOS transistor is controlled together. Then, each MOS transistor 42
To 47 are controlled, the second to fourth unit capacitance circuits 30
MOS transistors 42 to 47 is rendered conductive or cut off every _{2-30 4,} connects both ends of the capacitor 62 to 67 between the emitter terminal of the oscillation transistor 55 and 56, or is configured to decouple from the emitter terminals.

In this reference capacitance circuit 6, the capacitance value of the _first unit capacitance circuit 30 ₁ is C ₀ , and the n-th unit capacitance circuit 3
If the total capacity of two capacitors connected in parallel within 0 _n is C _n ,

[0060] ^{_{C n = C 0/2 n}} -1 of which is set so that the magnitude (second to capacitance of each capacitor 62 to 67 of the fourth unit capacitance circuit 30 _{2-30 4} is Each is one half of the capacity of the unit capacitor circuit in the preceding stage).

Accordingly, the second to fourth unit capacitance circuits 30_Two
~ 30_FourControl the MOS transistors in the capacitor
By switching the connection state of the sensors 62 to 67, the reference capacity
The total capacity of the road 6 is up to 15C₀/ 8, minimum C₀Nana
You. And the maximum capacity of 15C ₀/ 8 and minimum capacity C₀When
Between, C₀The capacity value can be set in / 8 increments.
You.

Here, assuming that the capacitance of the reference capacitance circuit 6 is set to an intermediate value between the maximum value and the minimum value in the initial state, the control circuit 14 determines the count value of the count circuit 12 and the setting circuit 16 Is compared with the set reference pulse number, and the capacitance value of the reference capacitance circuit 6 is changed based on the comparison result.

For example, if the comparison result indicates that the number of counted pulses is larger than the number of reference pulses, this is because the oscillation frequency of the oscillation circuit 5 is too high. The _second to _fourth unit capacitance circuits 302 to 304 are controlled to increase the capacitance value of the reference capacitance circuit 6 and lower the frequency.

Conversely, when the count value is smaller than the reference pulse number, the oscillation frequency is too low, so that the capacitance value of the reference capacitance circuit 6 is reduced and the frequency is increased. If the comparison and the control of the capacitance value are repeated based on the binary search method, the number of pulses counted by the count circuit 12 is stabilized at a value substantially equal to the reference pulse number.

As described above, when the capacitance value of the reference capacitance circuit 6 is changed, the capacitance value in the main circuit 23 is changed according to the capacitance value of the reference capacitance circuit 6 as described below.

Signals for controlling the _second to _fourth unit capacitance circuits 302 to 304 are also input to the main circuit 23.

The structure of the main circuit 23 will be described with reference to FIG. 3. In the main circuit 23, first and second variable capacitance circuits 70 and 90 and first and second resistance elements 79 and 99 are provided. When,
An amplifier 89 is provided.

The first and second variable capacitance circuits 70 and 90
First to fourth unit capacitance circuits 31 _{1 to} 31 ₄ , 32
It has a _{1-32 4.}

The first unit capacitance circuits 31 ₁ and 32 ₁ are composed of capacitors 71 and 91, and the second to fourth unit capacitance circuits 31 _{2 to} 31 ₄ and 32 _{2 to} 32 ₄ are connected to the capacitor 7.
2-74, 92-94 and MOS transistors 75-7
7, 95 to 97 in series.

Reference numeral 27 in FIGS. 1 and 3 denotes a main body circuit 2
3 shows a source of an AC signal input to the AC power supply 3, and an AC signal input from the source is connected to a first,
The signal is input to the non-inverting input terminal of the amplifier 89 via the second resistance elements 79 and 99.

One end of each of the first to fourth unit capacitance circuits 31 _{1 to} 31 ₄ in the first variable capacitance circuit 70 is connected to a connection midpoint where the first and second resistance elements 79 and 99 are connected to each other. The other ends are connected to the output terminal of the amplifier 89. The output terminal of the amplifier 89 is input to the inverting input terminal, and the resistance component of the first resistance element 79, the capacitance of the first variable capacitance circuit 70, and the amplifier 89 constitute a low-pass filter.

On the other hand, the first to the first in the second variable capacitance circuit 70
One end of each of the fourth unit capacitance circuits 32 _{1 to} 32 ₄ is connected to an amplifier 89.
And the other ends thereof are connected to the ground potential. The resistance component of the second resistance element 99 and the capacitance of the second variable capacitance circuit 90 similarly
A low-pass filter is configured.

The first to fourth unit capacitance circuits 31 _{1 to} 31 ₄ ,
32 _1-32 capacitance value of ₄ is either a first through capacitance value equal to the magnitude of the fourth unit capacitance circuit 30 ₁ to 30 ₄ of the reference capacitance circuit 6, or a constant multiplied by is sized I have.

Then, the second to fourth unit capacitance circuits 31 ₂
To 31 _4, 32 each MOS transistors _{2-32 4} 75
The gate terminals of 77 to 95 and 97 are connected to the gate terminals of the MOS transistors 42 to 47 of the _second to _fourth unit capacitance circuits 302 to 304 in the reference capacitance circuit 6, respectively.

Therefore, when the conduction state of the MOS transistors 42 to 47 in the reference capacitance circuit 6 is controlled by the control circuit 14, the second to fourth unit capacitance circuits 31 _{2 to} 31 ₄ in the main circuit 23, The conduction states of the MOS transistors 75 to 77 and 95 to 97 in 32 _{2 to} 32 ₄ are also controlled.

As a result, when the capacitance value of the reference capacitance circuit 6 is changed, the capacitance values of the first and first variable capacitance circuits 70 and 90 are also changed while the ratio of the capacitance values is constant.

Here, as a result of changing the capacitance value of the reference capacitance circuit 6, finally, the first and second variable capacitance circuits 70,
Assuming that the capacitance value of 90 is set to C ₁ and C ₂ ,
When the resistance value of the second resistor element and R _1, R _2, cut-off frequency f _c and Q in the body circuit 23 is represented by the following formula. f _c = 1 / (2π × √ (R ₁ × R ₂ × C ₁ × C ₂ ) Q = 1 / ((√ (R ₂ / R ₁ ) + √ (R ₁ / R ₂ )) × √ (C ₁
/ C ₂ ))

From the above equation, it can be seen that f _c can be controlled by changing the magnitudes of C ₁ and C ₂ . In addition, since the ratio between R ₁ and R _{2 and} the ratio between C ₁ and C ₂ are constant, it can be seen that Q has a constant value.

Next, an example of use of the frequency characteristic adjusting circuit of the present invention will be described. Reference numeral 200 in FIG. 4A is a part of the modulation circuit of the transmission unit, and includes DACs (digital / analog converters) 201 and 204 and low-pass filters 202 and 2.
05 and two circuits in which mixer circuits 203 and 206 are connected in series.

Signals whose phases are shifted by 90 degrees are input to the DACs 201 and 204, and the low-pass filters 202 and 20
After the high frequency component is removed in step 5, the mixer circuit 203
At 206, it is mixed with the 2.4 GHz clock signal,
The signals are synthesized by the adder 207.

Reference numeral 3 denotes a frequency characteristic adjusting circuit of the present invention, which has two main circuits 23. Each main circuit 23 is used for each of the low-pass filters 202 and 205, and is configured so that one correction circuit 10 controls two main circuits 23.

By controlling the capacitance values of the low-pass filters 202 and 205, the variation of the cutoff frequency fc can be reduced, so that a required attenuation characteristic can be obtained with a low order.

Next, reference numeral 202 in FIG. 4B is a part of the FM delay detection circuit, and is an example in which the frequency characteristic adjustment circuit 3 inherent to the main circuit 23 is applied to a filter and a delay circuit.

The FM delay detection circuit 202 includes a mixer circuit 221 and first and second low-pass filters 22.
2, 223 and a delay circuit 224.

The mixer circuit 211 has an FSK (frequency shift keying) signal and the signal
24, and the first and second signals are input.
Through the low-pass filters 222 and 223.

The two main circuits 23 are used for the second low-pass filter 223 and the delay circuit 224.
The configuration is such that one correction circuit 10 controls two main circuits 23.

If the sensitivity of the delay circuit 224 fluctuates due to process conditions, the loop gain fluctuates, causing an increase in lock time and instability of the system.

The main circuit 23 of the present invention is
By applying to No. 4, the capacitance value is corrected, and a stable closed-loop gain can be obtained.

Further, by using the main circuit 23 for the second low-pass filter 223, the variation of the cutoff frequency is reduced.

Reference numeral 203 in FIG. 4C indicates a frequency synthesizer, which includes a voltage controlled oscillator 231 and a frequency divider 2
32, a phase comparator 234, and a low-pass filter 235
And The frequency synthesizer 203 divides the frequency of the signal output from the voltage controlled oscillator 231 by the frequency divider 232, and the phase comparator 234 compares the phase of the frequency-divided signal with the phase of the reference clock signal.
, And outputs a signal to the voltage controlled oscillator 231.

The voltage controlled oscillator 231 changes the oscillation frequency in accordance with the input signal, reduces the phase difference between the reference clock signal and the output signal of the frequency divider 232, and makes the frequencies of both signals coincide. And as a result,
A signal of a constant frequency can be obtained from the output terminal 236.

The voltage control oscillator 231 uses the main circuit 23 of the frequency characteristic adjusting circuit 2 of the present invention, and
When the capacitance in the voltage controlled oscillator 231 is adjusted by 0, the voltage controlled oscillator 231
Can be made constant, and the loop gain can be stabilized more than the conventional frequency synthesizer.

[0093]

When the capacitance value of the reference capacitance circuit is changed to an appropriate value, the capacitance value of the variable capacitance circuit in the main circuit is also changed in conjunction therewith, so that the frequency characteristic of the main circuit is automatically corrected. Is done. Therefore, the frequency characteristic of the main circuit is
Unaffected by fluctuations in resistance and capacitance. Further, it is possible to cope with the intermittent operation without requiring a large-capacity capacitor.

[Brief description of the drawings]

FIG. 1 shows an example of a frequency characteristic adjusting circuit according to the present invention.

FIG. 2 is an internal circuit diagram of the AC signal generation source.

FIG. 3 is an internal circuit diagram of a main circuit.

4 (a) to 4 (c): Examples of use of the frequency characteristic adjusting circuit of the present invention.

FIG. 5 is a prior art filter circuit.

[Explanation of symbols]

 2, 3 ... frequency characteristic adjustment circuit 5 ... oscillation circuit 6 ... reference capacitance circuit 10 ... correction circuit 12 ... counter circuit 13 ... comparator 14 ... control circuit 23 ... body circuit 61-67, 72 ~ 74,92 ~ 94 .... Capacitor

Continued on the front page F term (reference) 5J081 AA08 CC22 DD11 EE03 FF02 FF10 FF18 FF25 KK02 KK07 KK23 MM01 5J098 AA03 AA14 AB02 AB03 AB04 AB15 AB22 AB23 AC02 AD18 AD25 CA02 CA04 CA05

Claims (5)

[Claims] A signal processing circuit having a variable capacitance circuit, for inputting a predetermined signal and performing predetermined processing on the input signal in accordance with the capacitance value of the variable capacitance circuit; and a reference capacitance circuit. An oscillation circuit that outputs an oscillation signal having a frequency corresponding to the capacitance value of the reference capacitance circuit, a counter circuit that counts the oscillation signal, and a comparison that compares the count value with a predetermined value and outputs the comparison result And a control circuit for controlling a capacitance value of a variable capacitance circuit of the signal processing circuit and a capacitance value of a reference capacitance circuit of the oscillation circuit based on the comparison result. 2. The apparatus according to claim 1, wherein said counter circuit has an AND element for inputting a reference clock signal and said oscillation signal, and a circuit for inputting an output of said AND element and counting the number of waves of said oscillation signal. The described frequency characteristic adjustment circuit. 3. The variable capacitance circuit of the signal processing circuit and the reference capacitance circuit of the oscillation circuit have a plurality of capacitors connected between two nodes via transistors, respectively, and the control circuit includes a transistor connected to each of the transistors. 3. The frequency characteristic adjusting circuit according to claim 1, wherein capacitance values of the variable capacitance circuit and the reference capacitance circuit are changed by controlling a conduction state of the frequency characteristic adjustment circuit. 4. 4. The signal processing circuit is a filter circuit,
4. The frequency characteristic adjusting circuit according to claim 1, wherein said frequency characteristic is controlled by a capacitance value of said variable capacitance circuit. 5. The frequency characteristic adjusting circuit according to claim 1, wherein said signal processing circuit is a delay circuit, and the amount of delay is controlled by a capacitance value of said variable capacitance circuit.