JP2003338668A - Circuit board, multilayer circuit board and manufacturing method therefor - Google Patents

Circuit board, multilayer circuit board and manufacturing method therefor

Info

Publication number
JP2003338668A
JP2003338668A JP2002146832A JP2002146832A JP2003338668A JP 2003338668 A JP2003338668 A JP 2003338668A JP 2002146832 A JP2002146832 A JP 2002146832A JP 2002146832 A JP2002146832 A JP 2002146832A JP 2003338668 A JP2003338668 A JP 2003338668A
Authority
JP
Japan
Prior art keywords
circuit board
conductive
circuit
hole
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002146832A
Other languages
Japanese (ja)
Inventor
Satoru Nakao
知 中尾
Shoji Ito
彰二 伊藤
Masahiro Okamoto
誠裕 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Priority to JP2002146832A priority Critical patent/JP2003338668A/en
Publication of JP2003338668A publication Critical patent/JP2003338668A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To achieve stable electric connection between a conductive circuit and a conductive resin with low resistance, in a circuit board formed by provid ing the conductive circuits on both front and rear surfaces of an insulated substrate, and connecting the conductive circuits to each other with the conduc tive resin through a through hole formed in the insulated substrate. <P>SOLUTION: The conductive circuit provided to the insulated substrate comprises a groove. The groove and the through hole are filled with the conductive resin to increase an area of a contact surface between the conductive circuit and the conductive resin. Thereby the electrical connection of them is absolutely obtained and resistance is lowered. To form the groove to the conductive circuit, a resist pattern whose width is sufficiently smaller than the thickness of the conductive circuit is used for alkali-etching. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、電子部品を実装す
る回路基板またはパッケージ基板に関し、特に基板に形
成した回路の電気特性を向上させるための基板構造及び
その製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board or a package board on which electronic parts are mounted, and more particularly to a board structure for improving electric characteristics of a circuit formed on the board and a manufacturing method thereof.

【0002】[0002]

【従来の技術】従来より、電子機器の軽薄短小化、半導
体チップや部品の小型化および端子の狭ピッチ化に連動
して、プリント回路基板でも実装面積の縮小や配線の精
細化が進んでいる。同時に情報関連機器では信号周波数
の広帯域化に対応して、部品間を連結する配線の短距離
化が求められており、高密度、高性能を達成するための
回路基板の多層化は必要不可欠の技術となっている。こ
の多層回路基板では、従来の平面回路には無かった層間
を電気的に接続する回路形成がキーテクノロジーとなっ
てきている。多層回路基板の第一ステップである両面配
線基板は、絶縁基材に貫通孔をあけ、孔の壁面に沿って
導体をメッキして表裏の配線を接続している。例えば、
ビルドアップ多層基板においても回路層間の絶縁層の一
部をレーザ等で除去し、メッキで接続する方法を用いて
いる(福田著:「はじめてのエレクトロニクス実装技
術」工業調査会 p.71参照)。メッキを用いた回路
配線の接続は、微細な回路を低く安定した接続抵抗で連
結できる利点を持つが、工程が複雑で工数も多いためコ
ストが高くなり、多層基板の用途を制限する要因となっ
ていた。
2. Description of the Related Art Conventionally, the mounting area and wiring of printed circuit boards have become smaller and finer in association with the miniaturization of electronic equipment, the miniaturization of semiconductor chips and components, and the narrowing of terminal pitches. . At the same time, in information-related equipment, it is required to shorten the distance of the wiring that connects the parts in response to the widening of the signal frequency, and it is indispensable to multilayer the circuit board to achieve high density and high performance. It has become a technology. In this multi-layer circuit board, a key technology is to form a circuit for electrically connecting layers, which is not present in a conventional planar circuit. In the double-sided wiring board, which is the first step of the multilayer circuit board, through holes are formed in the insulating base material, and a conductor is plated along the wall surface of the hole to connect the front and back wirings. For example,
Also in the build-up multilayer board, a method of removing a part of the insulating layer between the circuit layers with a laser or the like and connecting by plating is used (see Fukuda: "First Electronics Packaging Technology" Industrial Research Group, p.71). The circuit wiring connection using plating has the advantage that minute circuits can be connected with a low and stable connection resistance, but the process is complicated and the number of steps is large, so the cost is high and it becomes a factor limiting the application of the multilayer substrate. Was there.

【0003】近年、メッキに変わる安価な層間接続方法
として導電性樹脂(導電ペースト)を用いた多層基板が
実用化され、多層基板の用途も急速に拡大し始めた(例
えば、白石ら:松下テクニカルジャーナル、Vol.45,N
o.4、p.401 (1999)あるいは福岡ら:電子材料、Vo
l.34,No.16、p.95 (1995)参照)。この技術では、
絶縁樹脂板を出発材料としてレーザを用いて貫通孔(ビ
アホール)を開口した後、印刷法によって導電性樹脂を
貫通孔内に充填して、表裏接続回路としている。所望の
箇所に導電性樹脂による接続部が設けられた絶縁基材
を、銅箔で挟んで圧着することをくり返し、多層接続導
電回路を構成している。
In recent years, a multilayer board using a conductive resin (conductive paste) has been put into practical use as an inexpensive interlayer connection method instead of plating, and the application of the multilayer board has begun to rapidly expand (for example, Shiraishi et al .: Matsushita Technical Journal, Vol.45, N
o.4, p. 401 (1999) or Fukuoka et al .: Electronic materials, Vo
l.34, No.16, p. 95 (1995)). With this technology,
A through hole (via hole) is opened using a laser using an insulating resin plate as a starting material, and then a conductive resin is filled in the through hole by a printing method to form a front and back connection circuit. An insulating base material having a connection portion made of a conductive resin provided at a desired position is sandwiched between copper foils and pressure-bonded repeatedly to form a multilayer connection conductive circuit.

【0004】図16は従来の多層回路基板の構造を示す
図であり、図16(a)は平面図を、図16(b)は線
D−D’に沿った断面図を示している。図に示すように
樹脂フィルムからなる絶縁性基板101上に銅箔などか
らなる導電回路102が形成されており、導電回路10
2をとおして絶縁性基板101に貫通孔104が設けら
れている。貫通孔104内には導電性樹脂105が充填
されている。図16(b)に示すようにこのような基板
が貫通孔104を一致させて複数枚重ね合わされて多層
回路基板100が構成されている。この結果、導電性樹
脂中に含まれる銅や銀などの導電性粒子を介して導電回
路102と導電性樹脂105が電気的に接続されてい
る。
FIG. 16 is a diagram showing the structure of a conventional multilayer circuit board, FIG. 16 (a) is a plan view, and FIG. 16 (b) is a sectional view taken along line DD ′. As shown in the figure, a conductive circuit 102 made of copper foil or the like is formed on an insulating substrate 101 made of a resin film.
A through hole 104 is provided in the insulating substrate 101 through 2. A conductive resin 105 is filled in the through hole 104. As shown in FIG. 16B, a plurality of such substrates are stacked with the through holes 104 aligned with each other to form a multilayer circuit board 100. As a result, the conductive circuit 102 and the conductive resin 105 are electrically connected via the conductive particles such as copper and silver contained in the conductive resin.

【0005】図17に上記のような従来の多層回路基板
の製造工程の一例を示す。絶縁性基板101を出発材料
とし(工程(a)参照)、所定位置に貫通孔104を窄
孔する(工程(b)参照 )。次に貫通孔104内に導
電性樹脂105を充填する(工程(c)参照 )。次に
基板の両面にたとえば銅箔2aを貼り付ける(工程
(d)参照 )。次いで銅箔の表面にフォトレジスト膜
を形成し、所定の回路パターンを露光・現像した後フォ
トレジスト膜をマスクとしてケミカルエッチングを行っ
て、所定の導電回路102を形成する次いでこのように
して得た所定の導電回路を有する回路基板110,11
4を必要枚数と銅箔102aを上下に重ね合わせて熱圧
着する(工程(f)参照 )。このようにして図17
(g)に示す多層回路基板100を得ていた。
FIG. 17 shows an example of the manufacturing process of the conventional multilayer circuit board as described above. The insulating substrate 101 is used as a starting material (see step (a)), and a through hole 104 is formed at a predetermined position (see step (b)). Next, the through hole 104 is filled with a conductive resin 105 (see step (c)). Next, for example, copper foil 2a is attached to both surfaces of the substrate (see step (d)). Next, a photoresist film is formed on the surface of the copper foil, a predetermined circuit pattern is exposed and developed, and then chemical etching is performed using the photoresist film as a mask to form a predetermined conductive circuit 102. Circuit boards 110, 11 having a predetermined conductive circuit
The required number of 4 and the copper foil 102a are vertically stacked and thermocompression bonded (see step (f)). In this way, FIG.
The multilayer circuit board 100 shown in (g) was obtained.

【0006】図18には従来の多層回路基板100を得
るための別の一例を示す。この方法では工程(a)から
工程(d)では片面に銅箔を貼った片面どう貼り基板を
出発材料として使用して、図7と同様な手順で回路基板
111を製作し、一方工程(e)から工程(h)では両
面に銅箔2a,2aを貼った両面倒貼り基板を出発材料
として使用し、やはり図17と同様の手順で回路基板1
14を作図18(i)に示すよ板200を得たいた。
FIG. 18 shows another example for obtaining the conventional multilayer circuit board 100. In this method, in steps (a) to (d), a circuit board 111 is manufactured in the same procedure as in FIG. 7 using a single-sided board having copper foil adhered on one side as a starting material. ) To step (h), a double-sided inverted-pasted substrate having copper foils 2a, 2a on both sides is used as a starting material, and the circuit board 1 is also processed in the same procedure as in FIG.
A plate 200 was obtained as shown in Fig. 18 (i).

【0007】また、これ以外にも絶縁層として感光性樹
脂を用い、露光・現像を行うことにより貫通孔を形成し
たり、ケミカルエッチング(町田:表面実装技術 Vol.
17 No.1 p.31 (1997) )あるいはドライエッチングによ
って樹脂を除去する方法も提案されている。導電性樹脂
を用いた方法では安価である反面、導電性樹脂部分の電
気抵抗が高く、銅箔を使用した導電回路との接触抵抗が
安定しない等のいくつかの欠点があるが、それらも徐々
に克服されつつある。
In addition to this, a photosensitive resin is used as an insulating layer, and a through hole is formed by performing exposure and development, or chemical etching (Machida: Surface Mount Technology Vol.
17 No.1 p.31 (1997)) or a method of removing the resin by dry etching has also been proposed. Although the method using a conductive resin is inexpensive, there are some drawbacks such as high electrical resistance of the conductive resin portion and unstable contact resistance with a conductive circuit using a copper foil, but they also gradually Is being overcome by.

【0008】しかしながら、マルチチップモジュールな
どベアチップを実装する基板では、配線の高密度化に伴
って1層の回路基板の厚さも減少する傾向にある。層厚
の減少によって基板として使用する絶縁フィルム単体で
は基板の撓みや皺が発生し易くなり、寸法安定性が確保
しにくくなっている。層間接続に導電性樹脂を用いる多
層基板の製造方法においては、素材として銅箔貼りフィ
ルムを出発材料とすることにより、フィルムの剛性が高
まり高い寸法精度を容易に維持できるが、なお次のよう
な欠点が残っている。
However, in a board on which a bare chip such as a multi-chip module is mounted, the thickness of a single-layer circuit board tends to decrease as the wiring density increases. Due to the reduction of the layer thickness, the insulating film used as a substrate is liable to be bent or wrinkled, which makes it difficult to secure dimensional stability. In a method for manufacturing a multilayer substrate using a conductive resin for interlayer connection, by using a copper foil-bonded film as a starting material, the rigidity of the film is increased and high dimensional accuracy can be easily maintained. The drawbacks remain.

【0009】上記の欠点を補い、回路導体と導電性樹脂
との接触抵抗を安定して低く維持するために、図20
(蓋メッキ型)に示すように、回路基板111の貫通孔
104内に導電性樹脂105を充填した後、導電回路1
02及び貫通孔104内の導電性樹脂105の表面にメ
ッキ層114を形成して導電回路102と導電性樹脂1
05との接触面積を確保する手段が提案されている。こ
の手段によれば回路導体と導電性樹脂との接触面積を広
げることができるため、接触抵抗は充分低く抑えること
ができるが、メッキ処理によるコストアップは避けられ
ず、導電性樹脂による層間接続法の利点は失われてしま
う。
In order to compensate for the above-mentioned drawbacks and to keep the contact resistance between the circuit conductor and the conductive resin stable and low, FIG.
After the conductive resin 105 is filled in the through hole 104 of the circuit board 111 as shown in (capping type), the conductive circuit 1 is formed.
02 and the through hole 104, a plating layer 114 is formed on the surface of the conductive resin 105 in the through hole 104 to form the conductive circuit 102 and the conductive resin 1.
The means for ensuring the contact area with 05 is proposed. By this means, the contact area between the circuit conductor and the conductive resin can be widened, so the contact resistance can be suppressed to a sufficiently low level, but the cost increase due to the plating treatment is unavoidable, and the interlayer connection method using the conductive resin is inevitable. The advantage of is lost.

【0010】メッキを用いずに同様の構造を達成するた
めに、回路導体を有する基板に表裏接続回路用の貫通孔
をあける際に、回路導体を残して基板のみを貫通させ、
形成された有蓋貫通孔に導電性樹脂を充填する方法が考
えられている。図21(有蓋貫通孔型)はこの方法によ
って得られた回路基板112の断面図を示している。こ
の方法では導電性樹脂105と導電回路102との電気
的接続は良好であるものの、有蓋貫通孔への導電性樹脂
の充填に難点がある。貫通孔の場合の導電性樹脂の充填
は、孔の片方から導電性樹脂を印刷、注入することによ
り容易に充填が達成されるが、有蓋貫通孔の場合には導
電性樹脂の注入の過程で孔底に残った空気が排出され
ず、気泡として残留して導電性樹脂の充填が不完全とな
り易い。真空中で印刷することにより気泡を残留させる
ことなく孔に充填することのできる装置も開発されてい
るが、装置コスト、加工工数とも極端に増大してしま
い、本工程を適用した製品は限定された分野にしか用い
ることができない。
In order to achieve a similar structure without using plating, when a through hole for front and back connecting circuits is formed in a substrate having a circuit conductor, the circuit conductor is left and only the substrate is penetrated.
A method of filling the formed through-hole with a cover with a conductive resin is considered. FIG. 21 (through-hole type with a lid) shows a cross-sectional view of the circuit board 112 obtained by this method. With this method, the electrical connection between the conductive resin 105 and the conductive circuit 102 is good, but there is a problem in filling the through hole with a lid with the conductive resin. In the case of a through hole, the filling of the conductive resin is easily achieved by printing and injecting the conductive resin from one side of the hole, but in the case of the through hole with a lid, the process of injecting the conductive resin is performed. The air remaining on the bottom of the hole is not discharged, and remains as bubbles, which tends to cause incomplete filling of the conductive resin. An apparatus that can fill the holes without leaving air bubbles by printing in vacuum has been developed, but the equipment cost and processing man-hours increase significantly, and the products to which this process is applied are limited. Can be used only in the field

【0011】一方、回路導体の表面を含み、貫通孔の開
口部よりも一回り大きな範囲に導電性樹脂を印刷するこ
とによっても、導電性樹脂と回路導体との接触面積を拡
大して接触抵抗を低く安定化させることができる。図2
2(ランド積層型)はこの方法によって作られた回路基
板113の断面を示している。図に示すようにこの回路
基板113では、貫通孔104を含む導電回路102上
に導電性樹脂からなるランド116が形成されており、
導電回路102の表面でも導電回路102と導電性樹脂
105とが接触しているので、接触面積は図19(b)
の貫通孔型に比較して接触面積は増加している。この方
法によれば絶縁性基板101に形成した貫通孔104に
印刷法を用いて導電性樹脂105を充填する際、同時に
貫通孔周りに導電性樹脂からなるランド116をパター
ン形成できるため、低コストで回路基板を得ることがで
きる。
On the other hand, by printing the conductive resin in a region including the surface of the circuit conductor and slightly larger than the opening of the through-hole, the contact area between the conductive resin and the circuit conductor is expanded to increase the contact resistance. Can be stabilized low. Figure 2
2 (land laminated type) shows a cross section of the circuit board 113 manufactured by this method. As shown in the figure, in this circuit board 113, a land 116 made of a conductive resin is formed on the conductive circuit 102 including the through hole 104,
Since the conductive circuit 102 and the conductive resin 105 are also in contact with each other on the surface of the conductive circuit 102, the contact area is shown in FIG.
The contact area is larger than that of the through-hole type. According to this method, when the through holes 104 formed in the insulating substrate 101 are filled with the conductive resin 105 by using the printing method, the lands 116 made of the conductive resin can be formed around the through holes at the same time, which results in low cost. The circuit board can be obtained with.

【0012】[0012]

【発明が解決しようとする課題】しかしながら、上記構
造においては一層の回路基板の小型化・高密度化を目的
とした回路ピッチの微細化や導体間の薄層化に対して障
害が起こる恐れがある。すなわち、貫通孔周辺のランド
部において導電回路102上に重ねて導電性樹脂105
を印刷するため、ランド厚さが極端に増大し基板の薄型
化を妨げたり、多層積層後の基板全体の平坦性を損ない
易くなる。また、導電性樹脂の印刷時にランドの中心と
貫通孔の位置を整合させる必要があるため、印刷装置の
アライメント精度よりランドの寸法を小さくできず、回
路の微細化が制約されることとなる。したがって多層積
層基板の層間の接続に導電性樹脂を使用し、低コストで
優れた電気特性を維持しつつ高密度化に対応するために
は層間接続方法のさらなる改良が望まれている。
However, in the above structure, there is a possibility that an obstacle may occur to the miniaturization of the circuit pitch and the thinning of the conductor for the purpose of further miniaturization and high density of the circuit board. is there. That is, the conductive resin 105 is overlaid on the conductive circuit 102 in the land portion around the through hole.
Since the printing is performed, the land thickness is extremely increased, which hinders the thinning of the substrate, and the flatness of the entire substrate after the multilayer lamination is easily impaired. Further, since it is necessary to align the center of the land with the position of the through hole during printing of the conductive resin, the dimension of the land cannot be made smaller than the alignment accuracy of the printing apparatus, and miniaturization of the circuit is restricted. Therefore, further improvement of the interlayer connection method is desired in order to use a conductive resin for the connection between the layers of the multilayer laminated substrate and to cope with high density while maintaining excellent electrical characteristics at low cost.

【0013】[0013]

【課題を解決するための手段】上記の問題を解決するた
め本発明の回路基板は、絶縁性基板に貫通孔を有し、該
貫通孔内に導電性樹脂が充填されており、該導電性樹脂
と前記絶縁性基板の表面に形成された導電回路とを電気
的に接続してなる回路基板であって、該導電回路の導体
表面に一端が貫通孔に達しており、他端の少なくとも一
部が該導電回路の導体裏面まで貫通していない溝を有し
てなる回路基板とした。本発明においては前記導電回路
表面の溝の平面形状は放射状ないしは星形を使用するこ
とができる。あるいは前記導電回路表面の溝の平面形状
は放射状ないしは星形と前記貫通孔の同心円との組み合
わせ形状とすることもできる。回路基板をこのように構
成することにより、特殊な装置を用いず工数の増大を最
小限に留めた方法で、導電回路と導電性樹脂との接触面
積を増大させて、接触抵抗を低位安定させ、良好な電気
特性を有する回路基板とすることができる。
In order to solve the above problems, a circuit board of the present invention has a through hole in an insulating substrate, and the through hole is filled with a conductive resin. A circuit board in which a resin and a conductive circuit formed on the surface of the insulating substrate are electrically connected, one end of which reaches a through hole on the conductor surface of the conductive circuit, and at least one of the other ends A circuit board having a groove whose portion does not penetrate to the back surface of the conductor of the conductive circuit is provided. In the present invention, the planar shape of the groove on the surface of the conductive circuit may be radial or star-shaped. Alternatively, the planar shape of the groove on the surface of the conductive circuit may be a combination of a radial shape or a star shape and a concentric circle of the through hole. By configuring the circuit board in this way, the contact area between the conductive circuit and the conductive resin is increased by a method that minimizes the increase in man-hours without using a special device, and the contact resistance is stabilized at a low level. A circuit board having good electrical characteristics can be obtained.

【0014】本発明の多層回路基板は、上記の本発明の
回路基板を、少なくとも1枚以上の積層してなる多層回
路基板である。各回路基板の導電回路と導電性樹脂との
接触抵抗が低いので、多層に積層しても全体として接触
抵抗が低く、良好な電気特性を有する多層回路基板とす
ることができる。
The multilayer circuit board of the present invention is a multilayer circuit board in which at least one circuit board of the present invention is laminated. Since the contact resistance between the conductive circuit of each circuit board and the conductive resin is low, the contact resistance is low as a whole even when laminated in multiple layers, and a multilayer circuit board having good electrical characteristics can be obtained.

【0015】また、本発明の回路基板の製造方法は、少
なくとも一方の面に導電体膜を具備した絶縁性基板の導
電体膜上にフォトレジスト膜を形成した後、細い溝パタ
ーンを有する所定の回路パターンを露光して現像処理
し、得られたフォトレジスト膜パターンをマスクとして
基板をエッチャント中に浸漬して前記導電体膜をエッチ
ングし、次いで得られた導電体パターンをマスクとして
基板の所定位置に貫通孔を設けた後、導電体パターン表
面の溝と前記貫通孔内に導電性樹脂を充填して、導電性
樹脂と導電体膜とを電気的に接続する方法を採用した。
本発明の方法においては、前記フォトレジスト膜に形成
するを形成する細い溝パターンの幅が、該フォトレジス
ト膜厚さの4倍以下であることが好ましい。本発明の方
法によれば、エッチング速度の差によって溝の深さに差
異が生じるので、特殊な装置を用いずに工数の増大を最
小限に抑えて安価に導電回路と導電性樹脂との接触面積
を増大させ、電気特性に優れた回路基板を得ることが可
能となる。
Further, according to the method of manufacturing a circuit board of the present invention, a photoresist film is formed on a conductor film of an insulating substrate having a conductor film on at least one surface, and then a predetermined groove pattern is formed. The circuit pattern is exposed and developed, the substrate is immersed in an etchant by using the obtained photoresist film pattern as a mask to etch the conductor film, and then the obtained conductor pattern is used as a mask at a predetermined position on the substrate. After a through hole is provided in the through hole, a conductive resin is filled in the groove on the surface of the conductive pattern and the through hole to electrically connect the conductive resin and the conductive film.
In the method of the present invention, it is preferable that the width of the narrow groove pattern forming the photoresist film is 4 times or less the thickness of the photoresist film. According to the method of the present invention, since the depth of the groove varies due to the difference in etching rate, the increase in the number of steps is minimized without using a special device, and the contact between the conductive circuit and the conductive resin is inexpensive. It is possible to increase the area and obtain a circuit board having excellent electrical characteristics.

【0016】さらに、本発明の多層回路基板の製造方法
は、上記の本発明の製造方法により得られた回路基板
を、少なくとも1枚以上積層して接合する方法を採用し
た。この方法によれば、特殊な装置を用いずに工数の増
大を最小限に抑えて安価に得られた回路基板を使用し、
通常の方法で積層するので高性能を有する多層回路基板
を安価に得ることができる。
Further, the manufacturing method of the multilayer circuit board of the present invention employs a method of laminating and bonding at least one circuit board obtained by the manufacturing method of the present invention. According to this method, using a circuit board obtained at a low cost by minimizing the increase in man-hours without using a special device,
Since the layers are laminated by the usual method, a high-performance multilayer circuit board can be obtained at low cost.

【0017】[0017]

【発明の実施の形態】以下図面を使用して本発明をさら
に詳細に説明する。なお、以下の図においては構造を分
かり易く説明するため、縮尺は必ずしも正確ではない。 (第1の実施形態)図1は、本発明の回路基板の貫通孔
部分を示す部分平面図である。また図2及び図3は、そ
れぞれ図1に示す回路基板の線A−A’及び線B−B’
に沿った断面図である。図1ないし図3に示すように、
本発明の回路基板10では、樹脂等からなる絶縁性基板
1に貫通孔4が設けてあり、絶縁性基板1の表面には銅
箔等からなる所定のパターンの導電回路2が設けてあ
る。導電回路2の表面には溝3が形成されており、本実
施形態においては溝3は貫通孔4の中心から放射状に形
成された直線状の溝3aと、貫通孔4と同心円状の溝3
bからなっている。貫通孔4の内部と溝3の内部には、
銅ペースト等の導電性樹脂5が充填されており、導電性
樹脂5と導電回路2とは電気的に接続されている。ま
た、図2及び図3に示すように溝3の一端は貫通孔4に
達しており、他端は円状の溝3bに接続されている。さ
らに、導電回路2の溝3の深さは導電回路2の厚さより
薄く、溝3内の導電性樹脂5は溝の側面と底面とにおい
て導電回路2に接触している。このため導電回路2と導
電性樹脂5との接触面積は、図19に示した従来の貫通
孔型の回路基板の場合と比較して大幅に増加しており、
導電回路2と導電性樹脂5との接触抵抗は低く、安定し
た電気特性を示す回路基板となる。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail with reference to the drawings. In the following figures, the scale is not necessarily accurate in order to make the structure easy to understand. (First Embodiment) FIG. 1 is a partial plan view showing a through hole portion of a circuit board of the present invention. 2 and 3 are line AA 'and line BB' of the circuit board shown in FIG. 1, respectively.
It is sectional drawing along. As shown in FIGS. 1 to 3,
In the circuit board 10 of the present invention, the through hole 4 is provided in the insulating substrate 1 made of resin or the like, and the conductive circuit 2 having a predetermined pattern made of copper foil or the like is provided on the surface of the insulating substrate 1. A groove 3 is formed on the surface of the conductive circuit 2. In this embodiment, the groove 3 is a linear groove 3a formed radially from the center of the through hole 4 and a groove 3 concentric with the through hole 4.
It consists of b. Inside the through hole 4 and inside the groove 3,
It is filled with a conductive resin 5 such as copper paste, and the conductive resin 5 and the conductive circuit 2 are electrically connected. Further, as shown in FIGS. 2 and 3, one end of the groove 3 reaches the through hole 4, and the other end is connected to the circular groove 3b. Further, the depth of the groove 3 of the conductive circuit 2 is thinner than the thickness of the conductive circuit 2, and the conductive resin 5 in the groove 3 is in contact with the conductive circuit 2 on the side surface and the bottom surface of the groove. Therefore, the contact area between the conductive circuit 2 and the conductive resin 5 is significantly increased as compared with the case of the conventional through-hole type circuit board shown in FIG.
The contact resistance between the conductive circuit 2 and the conductive resin 5 is low, and the circuit board exhibits stable electrical characteristics.

【0018】次に、図1ないし図3に示すような本発明
の回路基板の製造方法の一例について説明する。図4及
び図5は本発明の回路基板の製造方法の一例を示す工程
断面図である。この例ではポリイミドフィルムからなる
絶縁性基板1の片面に導電回路2となる銅箔2aを貼り
付けた片面銅貼り基板( Copper Clad Laminate:CC
L )6に接着剤7を貼り合わせた積層フィルム8を出
発材料としている(図4(a)参照)。CCLにはポリ
イミド等の絶縁性樹脂と金属導体箔とを接着剤を用いて
接合したタイプ、銅箔上にポリイミドの前駆体を塗布し
た後加熱焼成したタイプや、ポリイミドフィルム上に金
属膜を蒸着したタイプ、または蒸着膜をシード層として
メッキにより銅を成長させるタイプ等があり、本発明で
はこれらのCCLの銅と反対側に接着剤層が存在する張
り合わせフィルムの他、全層が熱可塑性ポリイミドから
なるCCLも出発材料として適用できる。また、熱可塑
性挙動を示す液晶ポリマーを絶縁層として用いたCCL
も出発材料として適用可能である。
Next, an example of a method of manufacturing the circuit board of the present invention as shown in FIGS. 1 to 3 will be described. 4 and 5 are process cross-sectional views showing an example of the method for manufacturing a circuit board of the present invention. In this example, a single-sided copper-clad substrate (Copper Clad Laminate: CC) in which a copper foil 2a serving as a conductive circuit 2 is attached to one surface of an insulating substrate 1 made of a polyimide film
The laminated film 8 in which the adhesive 7 is bonded to L) 6 is used as a starting material (see FIG. 4A). The CCL is a type in which an insulating resin such as polyimide and a metal conductor foil are joined together with an adhesive, a type in which a polyimide precursor is applied on a copper foil and then heated and baked, and a metal film is vapor-deposited on a polyimide film. And a type in which copper is grown by plating with a vapor-deposited film as a seed layer. In the present invention, in addition to the laminating film in which an adhesive layer is present on the side opposite to the copper of these CCLs, all layers are made of thermoplastic polyimide. CCL consisting of can also be applied as a starting material. In addition, CCL using a liquid crystal polymer exhibiting thermoplastic behavior as an insulating layer
Is also applicable as a starting material.

【0019】次に、積層フィルム8の導電回路側の表面
に、ロールラミネーターを用いてフォトレジストフィル
ム35を熱圧着する(図4(b)参照)。次いでフォト
レジストフィルム35に所定形状の回路パターンを露光
し、現像処理してレジストマスクを形成する(図4
(c)参照)。この際貫通孔周辺のフォトレジストフィ
ルムに貫通孔部41に接続するような溝部31となる細
いスリットを形成しておく。この細いスリットの幅はフ
ォトレジストフィルム35の厚さに対して十分細くし、
例えばフォトレジストフィルム35の厚さの4倍以下と
するのが好ましい。スリットの形状は貫通孔から放射状
に広がる形や、貫通孔を中心にほぼ同心円状に囲む形
等、スリットの一端が貫通孔部に達するように配置され
ていればよい。
Next, a photoresist film 35 is thermocompression-bonded to the surface of the laminated film 8 on the conductive circuit side using a roll laminator (see FIG. 4B). Next, a circuit pattern having a predetermined shape is exposed on the photoresist film 35 and developed to form a resist mask (FIG. 4).
(See (c)). At this time, a thin slit serving as the groove portion 31 connected to the through hole portion 41 is formed in the photoresist film around the through hole. The width of this narrow slit is made sufficiently thin with respect to the thickness of the photoresist film 35,
For example, the thickness is preferably four times or less the thickness of the photoresist film 35. The shape of the slit may be such that one end of the slit reaches the through hole portion, such as a shape that spreads radially from the through hole or a shape that surrounds the through hole in a substantially concentric shape.

【0020】次いで、レジストマスクを形成した基板を
塩化第二鉄を主成分とするエッチャント中に浸漬させケ
ミカルエッチングし、銅箔の不要部分をエッチング除去
する(図4(d)参照)。 この時、フォトレジストフ
ィルム35の厚さに対して十分細い幅のスリット部分は
エッチング速度が遅くなる。レジストをマスクとしてエ
ッチングを行う際に、レジスト開口間隔がレジスト厚さ
に近づくと、開口間隔が狭くなるにしたがってエッチン
グ速度は遅くなることが知られている( A.Kikuchi e
t.al. "Etching Rate of Copper Foil for Printed Cir
cuit Boad” Metallurgical Processes for Early Twe
nty-first Century, Edited by H.Y.Sohn, The Mineral
s, Metals & Materials Society,1994 参照)。 この
現象を利用してケミカルエッチングにより銅箔を貫通し
て貫通孔を形成すると同時に、銅箔表面に浅い溝を形成
することが可能である。
Then, the substrate on which the resist mask is formed is immersed in an etchant containing ferric chloride as a main component and chemical etching is performed to remove unnecessary portions of the copper foil by etching (see FIG. 4 (d)). At this time, the etching rate of the slit portion having a width sufficiently smaller than the thickness of the photoresist film 35 becomes slow. It is known that, when etching is performed using a resist as a mask, if the resist opening distance approaches the resist thickness, the etching speed becomes slower as the opening distance becomes narrower (A. Kikuchie
t.al. "Etching Rate of Copper Foil for Printed Cir
cuit Boad ”Metallurgical Processes for Early Twe
nty-first Century, Edited by HYSohn, The Mineral
s, Metals & Materials Society, 1994). By utilizing this phenomenon, it is possible to form a through hole through the copper foil by chemical etching and simultaneously form a shallow groove on the surface of the copper foil.

【0021】塩化第二鉄を主成分とするエッチャントを
用いたケミカルエッチングにより、貫通孔部41の銅箔
をエッチング除去して絶縁性基板1が露出した時点でエ
ッチングを停止する。するともともと厚さt1 あった銅
箔は貫通孔部41ではエッチングされて無くなっている
ものの、溝部31ではなお厚さt2 の薄い導体回路2の
銅箔が残留している(図4(e)参照)。溝部31に残
留する導体回路2の厚さt2 の適正値は、5μm程度で
ある。この程度の残留銅箔を得るための適正条件の一例
としては、たとえば厚さ8μmの銅箔を貼ったCCLを
使用し、厚さ10μm程度のフォトレジストフィルムま
たは液状フォトレジストを貼り付け、貫通孔の直径を1
00μm以上、溝用のスリットの幅を50μm程度とす
れば良い。
The etching is stopped when the insulating substrate 1 is exposed by etching away the copper foil in the through hole portion 41 by chemical etching using an etchant containing ferric chloride as a main component. Then, the copper foil originally having the thickness t 1 is etched away in the through hole portion 41, but the copper foil of the thin conductor circuit 2 having the thickness t 2 still remains in the groove portion 31 (FIG. 4 (e)). )reference). An appropriate value for the thickness t 2 of the conductor circuit 2 remaining in the groove 31 is about 5 μm. As an example of appropriate conditions for obtaining this level of residual copper foil, for example, CCL on which a copper foil with a thickness of 8 μm is pasted is used, and a photoresist film or liquid photoresist with a thickness of about 10 μm is pasted into the through hole. The diameter of 1
The width of the slit for the groove may be set to 00 μm or more and about 50 μm.

【0022】次に、残留したフォトレジスト膜を溶解除
去した後、導電回路2の銅箔をマスクとしてたとえばレ
ーザ照射を利用して絶縁性基板1及び接着剤7を貫通す
る貫通孔4を形成する。レーザ照射によりマスクとなる
導電回路2が残留している溝部31は穿孔されずに、導
電回路2が残留していない貫通孔部41のみ穿孔され
て、貫通孔4が形成される(図5(f)および(g)参
照)。利用できるレーザとしては、CO2 レーザの他
に、YAG等の固体レーザやエキシマレーザも使用可能
であるが、銅箔は浸食されずにポリイミド等の樹脂のみ
を浸食するようにエネルギーを選択する必要がある。樹
脂製の絶縁基板の穿孔には、レーザ照射を利用する以外
にもプラズマエッチングや適当な薬剤を用いた化学エッ
チングを利用することもできる。エッチング終了後、必
要に応じて貫通孔内を化学処理によってクリーニングす
る。
Next, after the remaining photoresist film is dissolved and removed, through holes 4 penetrating the insulating substrate 1 and the adhesive 7 are formed by using, for example, laser irradiation with the copper foil of the conductive circuit 2 as a mask. . The groove portion 31 in which the conductive circuit 2 serving as a mask remains by laser irradiation is not punched, but only the through hole portion 41 in which the conductive circuit 2 does not remain is punched to form the through hole 4 (FIG. f) and (g)). As a usable laser, a solid-state laser such as YAG or an excimer laser can be used in addition to a CO 2 laser, but it is necessary to select energy so that the copper foil is not eroded but only the resin such as polyimide is eroded. There is. For the perforation of the resin-made insulating substrate, plasma etching or chemical etching using an appropriate chemical can be used instead of using laser irradiation. After the etching is completed, the inside of the through hole is cleaned by a chemical treatment, if necessary.

【0023】最後に、溝3と貫通孔4とを形成した積層
フィルム8の導体回路2側に導電性樹脂5を印刷機を利
用して塗布し、導体回路2の表面に直接スキージを接触
させて導電性樹脂5を溝3と貫通孔4に充填する(図4
(h)参照)。刷版を用いずに金属箔上に直接導電性樹
脂を塗布し、スキージを用いて充填することにより凹部
である溝3と貫通孔4ににのみ導電性樹脂5が残留す
る。この時、溝3と貫通孔4との導電性樹脂5は連続し
ており、後の焼成によって一体化する。導電性樹脂はエ
ポキシ系樹脂を主成分とするバインダーと平均粒径5μ
m程度の金属粒をフイラーとする、粘度50〜150P
a・sの加熱硬化型導電ペーストを使用する。金属粒と
しては銀粒子や銅粒子あるいは銅粒子をフィラーとし、
銅粒子の表面を銀で被覆した粒子が利用できる。また、
溶媒成分が少なく乾燥及び硬化時に体積減少が僅かであ
れば樹脂の種類は問わない。
Finally, a conductive resin 5 is applied to the conductor circuit 2 side of the laminated film 8 having the groove 3 and the through hole 4 using a printing machine, and the surface of the conductor circuit 2 is directly contacted with a squeegee. To fill the groove 3 and the through hole 4 with the conductive resin 5 (see FIG. 4).
(See (h)). The conductive resin 5 is directly applied onto the metal foil without using a printing plate, and is filled with a squeegee, so that the conductive resin 5 remains only in the groove 3 and the through hole 4 which are the recesses. At this time, the conductive resin 5 in the groove 3 and the through hole 4 is continuous, and is integrated by subsequent firing. The conductive resin is a binder whose main component is an epoxy resin, and the average particle size is 5μ.
Viscosity of 50 to 150P, using metal particles of about m as filler
A heat-curable conductive paste of a · s is used. As the metal particles, silver particles or copper particles or copper particles as a filler,
Particles obtained by coating the surfaces of copper particles with silver can be used. Also,
The type of resin does not matter as long as the amount of solvent component is small and the volume reduction upon drying and curing is slight.

【0024】導電性樹脂を乾燥させた後、再び回路パタ
ーン用のフォトレジスト膜を形成し、導電回路用のパタ
ーンを露光・現像して銅箔をエッチングして所定パター
ンの導電回路2を形成すれば、図5(i)に示すような
回路基板10が得られる。
After drying the conductive resin, a photoresist film for a circuit pattern is formed again, the conductive circuit pattern is exposed and developed, and the copper foil is etched to form the conductive circuit 2 having a predetermined pattern. Thus, the circuit board 10 as shown in FIG. 5 (i) is obtained.

【0025】(第2の実施形態)多層回路基板を製造す
る場合には、上記のようにして得られた本発明の回路基
板10を少なくとも1枚使用して、所望の電気回路を有
する複数の回路基板を重ね合わせ、加熱圧着することに
より層間を接続すると同時に、導電性樹脂を硬化させて
層間の電気的接続を完全なものとすることにより得られ
る。たとえば、図6(j)は上記第1の実施形態で得ら
れた回路基板10を1枚と、貫通孔を2個有する別の回
路基板20を1枚と、さらに銅箔2aを1枚とを貫通孔
の一つを位置合わせして重ね合わせ、加熱圧着すること
により図6(k)に示すような3層の導電回路を有する
多層回路基板50とすることができる。図7はこのよう
にして得られた多層回路基板50の平面図であって、2
個の貫通孔4、4の周囲には、放射状の溝3a,3aと
それらを取り巻く貫通孔と同心円状の溝3b、3bが設
けられており、これらの溝3aと3bとは電気的に一体
接合されている。ここで図7の線C−C’に沿った断面
図が図6(k)である。
(Second Embodiment) In the case of manufacturing a multilayer circuit board, at least one circuit board 10 of the present invention obtained as described above is used, and a plurality of circuits having desired electric circuits are provided. It can be obtained by stacking circuit boards and connecting the layers by heating and pressure bonding, and at the same time curing the conductive resin to complete the electrical connection between the layers. For example, FIG. 6 (j) shows one circuit board 10 obtained in the first embodiment, another circuit board 20 having two through holes, and one copper foil 2a. By aligning one of the through-holes with each other and superimposing them by heat and pressure, a multilayer circuit board 50 having a three-layer conductive circuit as shown in FIG. FIG. 7 is a plan view of the multi-layer circuit board 50 thus obtained.
Radial grooves 3a, 3a and grooves 3b, 3b concentric with the through holes surrounding them are provided around the individual through holes 4, 4, and these grooves 3a and 3b are electrically integrated. It is joined. Here, FIG. 6K is a sectional view taken along the line CC ′ of FIG. 7.

【0026】(第3の実施形態)図8は貫通孔4の周囲
に設けられた溝3の別の実施形態を示す部分平面図であ
る。この回路基板21では、溝3は貫通孔4を中心にし
て放射状に設けられている。この実施形態では環状部は
存在しないが、放射状の溝3を第1の実施形態と同様に
して形成することにより、導電回路2と導電性樹脂5と
の接触面積が増加しているので、両者の接触抵抗を十分
低くすることが可能である。
(Third Embodiment) FIG. 8 is a partial plan view showing another embodiment of the groove 3 provided around the through hole 4. In this circuit board 21, the grooves 3 are provided radially around the through hole 4. Although there is no annular portion in this embodiment, since the contact area between the conductive circuit 2 and the conductive resin 5 is increased by forming the radial groove 3 in the same manner as in the first embodiment, both are not formed. It is possible to sufficiently lower the contact resistance of.

【0027】(第4の実施形態)図9は貫通孔4の周囲
に設けられた溝3のさらに他の実施形態を示す部分平面
図である。この回路基板22では、溝3は貫通孔4を中
心にして星形状に設けられている。この形状によっても
導電回路2と導電性樹脂5との接触面積が増加している
ので、両者の接触抵抗を十分低くすることが可能であ
る。なお、溝3を星形に形成した場合には、溝の付け根
部分と先端部分では溝幅が異なるため、エッチング速度
が異なり、エッチングによって形成される溝の深さも異
なってくる。図10は溝の深さを説明する図である。図
で22は導体回路で22aは表面を、22bは貫通孔面
を表している。23は導体回路22に設けられた溝であ
る。ここで紙面左下方向の星形の溝の付け根部分の溝深
さをd1 とし、紙面右上方向の星形の先端部の溝深さを
2 とすれば、先端部の深さd1 は付け根部の深さd2
よりも深くなる。すなわち、d1>d2 となる。
(Fourth Embodiment) FIG. 9 is a partial plan view showing still another embodiment of the groove 3 provided around the through hole 4. In this circuit board 22, the groove 3 is provided in a star shape centering on the through hole 4. This shape also increases the contact area between the conductive circuit 2 and the conductive resin 5, so that the contact resistance between the two can be made sufficiently low. When the groove 3 is formed in a star shape, since the groove width is different between the root portion and the tip portion of the groove, the etching rate is different and the depth of the groove formed by etching is also different. FIG. 10 is a diagram illustrating the depth of the groove. In the figure, 22 is a conductor circuit, 22a is the surface, and 22b is the through-hole surface. Reference numeral 23 is a groove provided in the conductor circuit 22. Here the groove depth of the base of the lower left direction of the star-shaped groove and d 1, if the groove depth of the tip of the star-shaped paper upper-right direction as d 2, the depth d 1 of the tip Root depth d 2
Deeper than. That is, d 1 > d 2 .

【0028】(第5の実施形態)導電回路2となる銅箔
上に溝3を形成後、貫通孔4を窄孔する方法として図1
1に示すようにドリル25による機械加工により、導電
回路2と樹脂製の絶縁性基板1及び接着材7を貫通させ
て、一気に窄孔する方法を利用することもできる。この
場合、図11(a)に示すように、導電回路2及び溝3
を第1の実施形態と同様の方法によりケミカルエッチン
グを利用して形成した後、ドリル25を使用して窄孔す
る。図11(b)のように導電回路2と絶縁性基板1及
び接着材7を貫通させて貫通孔4を形成した後、第1の
実施形態と同様の方法により溝3及び貫通孔4内に導電
性樹脂5を充填して図11(c)に示すように回路基板
10が得られる。
(Fifth Embodiment) FIG. 1 shows a method for forming a through hole 4 after forming a groove 3 on a copper foil to be a conductive circuit 2.
As shown in FIG. 1, it is also possible to use a method in which the conductive circuit 2, the resin-made insulating substrate 1 and the adhesive 7 are penetrated by machining by a drill 25 to form a hole at once. In this case, as shown in FIG. 11A, the conductive circuit 2 and the groove 3 are formed.
Is formed by utilizing chemical etching in the same manner as in the first embodiment, and then a drill 25 is used to form a hole. After forming the through hole 4 by penetrating the conductive circuit 2, the insulating substrate 1 and the adhesive material 7 as shown in FIG. 11B, the groove 3 and the through hole 4 are formed in the same manner as in the first embodiment. By filling the conductive resin 5, the circuit board 10 is obtained as shown in FIG.

【0029】(第6の実施形態)導電回路2となる銅箔
上に貫通孔4を窄孔する方法として図12に示すように
レーザ照射により、銅箔上に溝3を形成すると同時に貫
通孔4を窄孔する方法も利用できる。図12(a)に示
すように、絶縁性基板1の両面に導電回路2と接着剤7
を貼り付けた片面銅貼り積層フィルム8を使用し、図1
2(b)に示すように溝3と貫通孔4の部分にレーザを
照射する。この際貫通孔4の位置に照射するレーザL1
のエネルギーが、溝3の位置に照射するレーザL2 の量
よりも大きくなるようにレーザビームの走査を制御す
る。このようにして図12(c)に示す回路基板10が
得られる。
(Sixth Embodiment) As a method of forming a through hole 4 on a copper foil which becomes a conductive circuit 2, a groove 3 is formed on the copper foil by laser irradiation as shown in FIG. It is also possible to use a method in which 4 is narrowed. As shown in FIG. 12A, the conductive circuit 2 and the adhesive 7 are formed on both surfaces of the insulating substrate 1.
Using the single-sided copper-clad laminated film 8 attached to FIG.
As shown in FIG. 2 (b), the groove 3 and the through hole 4 are irradiated with laser. At this time, a laser L 1 for irradiating the position of the through hole 4
The scanning of the laser beam is controlled so that the energy of is larger than the amount of the laser L 2 with which the position of the groove 3 is irradiated. In this way, the circuit board 10 shown in FIG. 12C is obtained.

【0030】(第7の実施形態)次に、3枚の回路基板
を積層した多層回路基板の製造方法を説明する。図13
は両面銅貼り基板に貫通孔と溝を形成した回路基板31
を1枚と、片面銅貼り基板に貫通孔と溝を形成した回路
基板30を2枚使用して図13(a)のように重ね合わ
せて熱圧着し、図13(b)に示すような4面の導電回
路2を有する3層の多層回路基板51としたものであ
る。この回路基板51の少なくとも1面の導電回路に
は、溝3が形成されており、貫通孔4内の導電性樹脂5
との接触面積が大きくなっているので、接触抵抗の低い
多層回路基板とすることができる。
(Seventh Embodiment) Next, a method of manufacturing a multilayer circuit board in which three circuit boards are laminated will be described. FIG.
Is a circuit board 31 having through-holes and grooves formed on a double-sided copper-clad board.
13 and two circuit boards 30 each having a through hole and a groove formed in a single-sided copper-clad board are stacked and thermocompressed as shown in FIG. 13 (a), as shown in FIG. 13 (b). The multi-layer circuit board 51 has three layers having the conductive circuits 2 on four sides. The groove 3 is formed in the conductive circuit on at least one surface of the circuit board 51, and the conductive resin 5 in the through hole 4 is formed.
Since the contact area with is large, a multilayer circuit board with low contact resistance can be obtained.

【0031】(第8の実施形態)次に、図14は両面銅
貼り基板に貫通孔と溝を形成した回路基板31を1枚
と、片面銅貼り基板に貫通孔と溝を形成した回路基板3
0,32を2枚使用して図14(a)のように重ね合わ
せて熱圧着し、図14(b)に示すような4面の導電回
路2を有する3層の多層回路基板52としたものであ
る。このように重ね合わせる回路基板は必要に応じて任
意の構造のものを使用することができ、使用する回路基
板の少なくとも1面の導電回路に溝3を形成して導電性
樹脂5を充填しておけば、貫通孔4内の導電性樹脂5と
の接触面積が大きくなっているので、接触抵抗の低い多
層回路基板とすることができる。
(Eighth Embodiment) Next, FIG. 14 shows one circuit board 31 having a through-hole and a groove formed in a double-sided copper-clad substrate and a circuit board having a through-hole and a groove formed in a single-sided copper-clad substrate. Three
Using two sheets of 0 and 32, they were superposed and thermocompressed as shown in FIG. 14 (a) to obtain a three-layered multilayer circuit board 52 having four-sided conductive circuits 2 as shown in FIG. 14 (b). It is a thing. As described above, the circuit boards to be stacked can have any structure as required, and the groove 3 is formed in at least one conductive circuit of the circuit board to be used and the conductive resin 5 is filled therein. In other words, since the contact area with the conductive resin 5 in the through hole 4 is large, the multilayer circuit board can have a low contact resistance.

【0032】(第9の実施形態)また、図6(j)に示
す第2の実施形態で、銅貼り回路基板10に下側に銅箔
2aを重ね合わせる際に、銅箔の替わりに図15(a)
に示すように離型フィルム36の表面にあらかじ銅箔か
らなる導電回路2を形成しておき、これを回路基板3
0,32と重ね合わせて熱圧着した後、離型フィルム3
6を剥離して図15(b)に示すような多層回路基板5
3を得る方法も利用できる。
(Ninth Embodiment) In addition, in the second embodiment shown in FIG. 6 (j), when the copper foil 2a is superposed on the lower side of the copper-clad circuit board 10, a diagram is shown instead of the copper foil. 15 (a)
As shown in FIG. 3, the conductive circuit 2 made of rough copper foil is formed on the surface of the release film 36, and the conductive circuit 2 is formed on the circuit board 3
Release film 3 after overlapping with 0 and 32 and thermocompression bonding
6 is peeled off and the multilayer circuit board 5 as shown in FIG.
A method of obtaining 3 can also be used.

【0033】[0033]

【実施例】(実施例)図4から図6に示す第1の実施形
態の製造工程に従って、図6(k)に示すような3層の
導電回路を有する多層回路基板50を製造した。本実施
例では絶縁性基板1としてポリイミドフィルムを使用
し、導電回路2には厚さ18μmの銅箔を使用した片面
銅貼り基板を出発材料とした。ロールラミネータを使用
して銅箔上に厚さ15μmのフォトレジストフィルムを
熱圧着した。次いで、パターンを露光・現像して貫通孔
部分と貫通孔周辺部に形成する溝のレジストマスクパタ
ーンを形成した。貫通孔の直径は100μm、溝の幅は
50μmとした。
(Example) According to the manufacturing process of the first embodiment shown in FIGS. 4 to 6, a multi-layer circuit board 50 having a three-layer conductive circuit as shown in FIG. 6 (k) was manufactured. In this example, a polyimide film was used as the insulating substrate 1, and a single-sided copper-clad substrate using a copper foil having a thickness of 18 μm for the conductive circuit 2 was used as a starting material. A 15 μm thick photoresist film was thermocompression bonded onto the copper foil using a roll laminator. Then, the pattern was exposed and developed to form a resist mask pattern of a groove formed in the through hole portion and the peripheral portion of the through hole. The diameter of the through hole was 100 μm and the width of the groove was 50 μm.

【0034】次に、塩化第二鉄を主成分とするエッチャ
ントを用いて銅箔のケミカルエッチングを行った。エッ
チングにより銅箔に孔とスリットをあけ、この銅箔をマ
スクとしてCO2 レーザを照射し、ポリイミド基板と接
着剤を貫通させた。この時、溝部にはなお約5μmの厚
さの銅箔が残っていた。次に、貫通孔と溝を形成した片
面銅貼り基板の表面に銀ペーストを塗布し、銅箔表面に
直接スキージを接触させて銀ペーストを貫通孔及び溝内
に充填した。
Next, the copper foil was chemically etched using an etchant containing ferric chloride as a main component. Holes and slits were formed in the copper foil by etching, and CO 2 laser was irradiated using this copper foil as a mask to penetrate the polyimide substrate and the adhesive. At this time, the copper foil still having a thickness of about 5 μm remained in the groove. Next, a silver paste was applied to the surface of the single-sided copper-clad substrate on which the through holes and grooves were formed, and the squeegee was directly contacted with the surface of the copper foil to fill the silver paste into the through holes and grooves.

【0035】充填した銀ペーストを100℃のオーブン
中で乾燥した後、レジストフィルムを圧着し、回路パタ
ーンを露光・現像した。再度塩化第二鉄溶液を主成分と
するエッチャントを使用して銅箔をエッチングした後、
レジストを剥離して図5(i)に示す構造の回路基板1
0を完成させた。
After the filled silver paste was dried in an oven at 100 ° C., a resist film was pressed and the circuit pattern was exposed and developed. After etching the copper foil again using an etchant whose main component is ferric chloride solution,
The circuit board 1 having the structure shown in FIG.
Completed 0.

【0036】次いで、同様の方法により図6(j)に示
すような構造の回路基板20を作成し、1枚の回路基板
20と99枚の回路基板10と銅箔を図6(j)に示す
よう重ね合わせ、10〜50Kg/cm2 の加圧力を印
荷しながら150〜250℃に加熱して熱圧着し、10
0個の貫通孔を直列に接続した構造を有する多層回路基
板50’を作成して特性を評価した。
Next, a circuit board 20 having a structure as shown in FIG. 6 (j) is formed by the same method, and one circuit board 20, 99 circuit boards 10 and copper foil are formed as shown in FIG. 6 (j). As shown in the figure, they are piled up and heated to 150 to 250 ° C. while applying a pressure of 10 to 50 Kg / cm 2 , and thermocompression bonded to them.
A multilayer circuit board 50 ′ having a structure in which 0 through holes were connected in series was created and the characteristics were evaluated.

【0037】(比較例)層間接続部の特性を比較評価す
るために、同様に100個の貫通孔を直列に接続し、図
16に示す従来の貫通孔型の構造を有する多層回路基板
を作成した。
(Comparative Example) In order to compare and evaluate the characteristics of the interlayer connection portion, 100 through holes were similarly connected in series to prepare a multilayer circuit board having a conventional through hole type structure shown in FIG. did.

【0038】本実施例及び比較例の多層基板の表面の導
電回路と底面の導電回路間に直流電流を流した時の電気
抵抗を比較したところ、本発明の多層基板では電気抵抗
の変動値は±20%以内の範囲で一定値を示した。これ
に対して従来型構造の層基板では、電気抵抗の変動値は
±200%にも達して不安定であり、電気抵抗の絶対値
も本発明の場合に比較して1.5〜3倍も高かった。さ
らに両基板を−20℃〜+60℃の温度サイクル試験に
1000サイクル通した後、再び回路抵抗を測定した。
その結果、本発明の多層回路基板では5〜10%抵抗値
が増加していたのに対して、従来構造の多層回路基板で
は10〜100%も抵抗値が増加していた。以上の評価
結果より、導電樹脂と導電回路との接触抵抗が回路全体
の電気抵抗に大きく影響していることが確認された。
When the electric resistances when a direct current was applied between the conductive circuits on the front surface and the conductive circuit on the bottom surface of the multi-layered substrates of the present example and the comparative example were compared, the multi-layered substrate of the present invention showed that the variation value of the electric resistance was It showed a constant value within a range of ± 20%. On the other hand, in the layered substrate having the conventional structure, the fluctuation value of the electric resistance reaches ± 200% and is unstable, and the absolute value of the electric resistance is 1.5 to 3 times that of the present invention. It was also expensive. Further, both substrates were subjected to a temperature cycle test of −20 ° C. to + 60 ° C. for 1000 cycles, and then the circuit resistance was measured again.
As a result, the resistance value of the multilayer circuit board of the present invention increased by 5 to 10%, whereas the resistance value of the multilayer circuit board of the conventional structure increased by 10 to 100%. From the above evaluation results, it was confirmed that the contact resistance between the conductive resin and the conductive circuit greatly affects the electric resistance of the entire circuit.

【0039】[0039]

【作用】本発明の回路基板は、導電回路表面に溝を設
け、この溝内に導電性樹脂を充填して導電回路と貫通孔
内の導電性樹脂との接触面積を増大させることにより、
接触抵抗を低くしたものである。
The circuit board of the present invention is provided with a groove on the surface of the conductive circuit, and the conductive resin is filled in the groove to increase the contact area between the conductive circuit and the conductive resin in the through hole.
It has a low contact resistance.

【0040】[0040]

【発明の効果】本発明の回路基板によれば、薄い絶縁層
厚を要求される回路基板においても導体厚さを増加させ
る必要はなく、導電性樹脂で構成される層間接続回路と
絶縁基板上の導電回路とを広い面積で接触させ、低抵抗
で安定した層間接続を達成できるので、多層回路基板を
構成した場合でも基板厚さを薄くすることができ、電子
部品の軽薄短小化に寄与することができるようになる。
また、本発明の回路基板の製造方法によれば、従来の製
造工程に比較して大幅な工程付加をする必要もなく、従
来の材料や従来の装置を使用して容易に回路基板の薄型
化が達成できる。また、導体ランド上に導電性樹脂を印
刷するランド積層型に比較しても、導体厚さの増加がな
く、絶縁層を薄くできると同時に印刷時のアライメント
作業も不要となるので、製造工程が簡略化できる利点を
有する。
According to the circuit board of the present invention, it is not necessary to increase the conductor thickness even in a circuit board requiring a thin insulating layer thickness, and the interlayer connection circuit made of a conductive resin and the insulating board are provided. Since it can contact the conductive circuit in a wide area and achieve stable interlayer connection with low resistance, it is possible to reduce the board thickness even when a multilayer circuit board is configured, which contributes to the miniaturization of electronic parts. Will be able to.
Further, according to the method of manufacturing a circuit board of the present invention, it is possible to easily reduce the thickness of the circuit board by using a conventional material or a conventional apparatus without adding a large number of steps as compared with the conventional manufacturing process. Can be achieved. In addition, compared to the land laminated type in which conductive resin is printed on the conductor lands, the conductor thickness does not increase, the insulating layer can be made thin, and at the same time alignment work at the time of printing is not required. It has the advantage that it can be simplified.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の回路基板の貫通孔部の一例を示す部
分平面図である。
FIG. 1 is a partial plan view showing an example of a through hole portion of a circuit board of the present invention.

【図2】 図1に示した本発明の回路基板の線A−A’
に沿った断面図である。
2 is a line AA ′ of the circuit board of the present invention shown in FIG.
It is sectional drawing along.

【図3】 図1に示した本発明の回路基板の線B−B’
に沿った断面図である。
FIG. 3 is a line BB ′ of the circuit board of the present invention shown in FIG.
It is sectional drawing along.

【図4】 本発明の回路基板の製造方法の一例を示す断
面工程図である。
FIG. 4 is a cross-sectional process diagram showing an example of a method for manufacturing a circuit board of the present invention.

【図5】 図4に続く断面工程図である。FIG. 5 is a sectional process diagram following FIG. 4;

【図6】 図5に続く本発明の多層回路基板の製造方法
の断面工程図である。
FIG. 6 is a cross-sectional process diagram of the method for manufacturing a multilayer circuit board of the present invention, which is subsequent to FIG. 5;

【図7】 図6に示す本発明の多層回路基板の部分平面
図である。
FIG. 7 is a partial plan view of the multilayer circuit board of the present invention shown in FIG.

【図8】 本発明の他の回路基板の貫通孔部の例を示す
平面図である。
FIG. 8 is a plan view showing an example of a through hole portion of another circuit board of the present invention.

【図9】 本発明のさらに別の回路基板の貫通孔部の例
を示す平面図である。
FIG. 9 is a plan view showing an example of a through hole portion of still another circuit board of the present invention.

【図10】 図9に示す回路基板の溝の深さを説明する
図である。
10 is a diagram illustrating the depth of the groove of the circuit board illustrated in FIG.

【図11】 本発明の回路基板の製造方法における貫通
孔を加工する方法を説明する図である。
FIG. 11 is a diagram illustrating a method of processing a through hole in the method of manufacturing a circuit board according to the present invention.

【図12】 本発明の回路基板の製造方法における貫通
孔を加工する方法の他の例を説明する図である。
FIG. 12 is a diagram illustrating another example of a method of processing a through hole in the method of manufacturing a circuit board according to the present invention.

【図13】 本発明の多層回路基板の製造方法の一例を
示す図である。
FIG. 13 is a diagram showing an example of a method for manufacturing a multilayer circuit board according to the present invention.

【図14】 本発明の多層回路基板の製造方法の別の例
を示す図である。
FIG. 14 is a diagram showing another example of the method for manufacturing a multilayer circuit board according to the present invention.

【図15】 本発明の多層回路基板の製造方法のさらに
別の例を示す図である。
FIG. 15 is a diagram showing still another example of the method for manufacturing a multilayer circuit board according to the present invention.

【図16】 従来の多層回路基板の構造を示す図であ
る。
FIG. 16 is a diagram showing a structure of a conventional multilayer circuit board.

【図17】 図16に示す従来の多層回路基板の製造方
法を示す断面工程図である。
FIG. 17 is a sectional process diagram showing the method of manufacturing the conventional multilayer circuit board shown in FIG.

【図18】 従来の多層回路基板の別の製造方法を示す
断面工程図である。
FIG. 18 is a sectional process view showing another conventional method for manufacturing a multilayer circuit board.

【図19】 従来の回路基板の貫通孔部分の構造を説明
する図である。
FIG. 19 is a diagram illustrating a structure of a through hole portion of a conventional circuit board.

【図20】 従来の回路基板の別の構造を説明する図で
ある。
FIG. 20 is a diagram illustrating another structure of the conventional circuit board.

【図21】 従来の回路基板の他の構造を説明する図で
ある。
FIG. 21 is a diagram illustrating another structure of the conventional circuit board.

【図22】 従来の回路基板のさらに別の構造を説明す
る図である。
FIG. 22 is a diagram illustrating still another structure of the conventional circuit board.

【符号の説明】[Explanation of symbols]

1,101・・・・・・絶縁性基板、2,102・・・・・・導電回
路、3,23・・・・・・溝、4,104・・・・・貫通孔、5・・・
・・・導電性樹脂、6・・・・・・片面銅貼り基板、7・・・・・・接
着剤、8・・・・・・積層フィルム、10,20,21,11
0,111,112・・・・・・回路基板、25・・・・・・ドリ
ル、30,31,32・・・・・・回路基板、35・・・・・・フォ
トレジストフィルム、36・・・・・・離型フィルム、50,
51,52,53・・・・・・多層回路基板、114メッキ層
1, 101 ... Insulating substrate, 2, 102 ... Conductive circuit, 3, 23 ... Groove, 4, 104 ... Through hole, 5 ...・
... Conductive resin, 6 ..., Single-sided copper-clad substrate, 7 ..., Adhesive, 8 ..., Laminated film, 10, 20, 21, 11
0, 111, 112 ... Circuit board, 25 ... Drill, 30, 31, 32 ... Circuit board, 35 ... Photoresist film, 36 ... ...... Release film, 50,
51, 52, 53 ... Multi-layer circuit board, 114 plating layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 岡本 誠裕 千葉県佐倉市六崎1440番地 株式会社フジ クラ佐倉事業所内 Fターム(参考) 5E317 AA04 BB03 BB12 CC25 GG03 GG09 GG11 GG14 GG16 5E338 AA12 AA16 CD05 EE11 EE23 EE27 EE32 5E346 AA15 AA43 CC02 CC10 CC32 EE08 FF18 FF22 GG06 GG15 GG22 GG28 HH07 HH24 HH32 HH33    ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masahiro Okamoto             Fuji Co., Ltd. 1440 Rokuzaki, Sakura City, Chiba Prefecture             Kura Sakura Office F term (reference) 5E317 AA04 BB03 BB12 CC25 GG03                       GG09 GG11 GG14 GG16                 5E338 AA12 AA16 CD05 EE11 EE23                       EE27 EE32                 5E346 AA15 AA43 CC02 CC10 CC32                       EE08 FF18 FF22 GG06 GG15                       GG22 GG28 HH07 HH24 HH32                       HH33

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板に貫通孔を有し、該貫通孔内
に導電性樹脂が充填されており、該導電性樹脂と前記絶
縁性基板の表面に形成された導電回路とを電気的に接続
してなる回路基板であって、該導電回路の導体表面に一
端が貫通孔に達しており、他端の少なくとも一部が該導
電回路の導体裏面まで貫通していない溝を有してなるこ
とを特徴とする回路基板。
1. An insulating substrate having a through hole, and the through hole is filled with a conductive resin. The conductive resin and a conductive circuit formed on the surface of the insulating substrate are electrically connected to each other. A circuit board formed by connecting to a conductor surface of the conductive circuit, one end of which reaches a through hole, and at least a part of the other end of which has a groove which does not penetrate to the back surface of the conductor of the conductive circuit. A circuit board characterized in that.
【請求項2】 前記導電回路表面の溝の平面形状が放射
状ないしは星形をなしていることを特徴とする請求項1
に記載の回路基板。
2. The planar shape of the groove on the surface of the conductive circuit is radial or star-shaped.
The circuit board according to.
【請求項3】 前記導電回路表面の溝の平面形状が、放
射状ないしは星形と前記貫通孔の同心円との組み合わせ
形状をなしていることを特徴とする請求項1又は請求項
2に記載の回路基板。
3. The circuit according to claim 1, wherein the planar shape of the groove on the surface of the conductive circuit is a combination of a radial or star shape and a concentric circle of the through hole. substrate.
【請求項4】 請求項1から請求項3のいずれか1項に
記載の回路基板を、少なくとも1枚以上の積層してなる
ことを特徴とする積層回路基板。
4. A laminated circuit board comprising at least one circuit board according to any one of claims 1 to 3, which is laminated.
【請求項5】 少なくとも一方の面に導電体膜を具備し
た絶縁性基板の導電体膜上にフォトレジスト膜を形成し
た後、細い溝パターンを有する所定の回路パターンを露
光して現像処理し、得られたフォトレジスト膜パターン
をマスクとして基板をエッチャント中に浸漬して前記導
電体膜をエッチングし、次いで得られた導電体パターン
をマスクとして基板の所定位置に貫通孔を設けるととも
に、導電体表面に溝を設けた後、導電体パターン表面の
溝と前記貫通孔内に導電性樹脂を充填して、導電性樹脂
と導電体膜とを電気的に接続することを特徴とする回路
基板の製造方法。
5. A photoresist film is formed on a conductor film of an insulating substrate having a conductor film on at least one surface, and then a predetermined circuit pattern having a narrow groove pattern is exposed and developed. Using the obtained photoresist film pattern as a mask, the substrate is dipped in an etchant to etch the conductor film, and then the obtained conductor pattern is used as a mask to form through holes at predetermined positions of the substrate and the conductor surface. After providing a groove in the circuit board, a conductive resin is filled in the groove on the surface of the conductor pattern and in the through hole to electrically connect the conductive resin and the conductor film. Method.
【請求項6】 前記フォトレジスト膜に形成するを形成
する細い溝パターンの幅が、該フォトレジスト膜厚さの
4倍以下であることを特徴とする請求項5に記載の回路
基板の製造方法。
6. The method for manufacturing a circuit board according to claim 5, wherein the width of the narrow groove pattern formed in the photoresist film is 4 times or less the thickness of the photoresist film. .
【請求項7】 請求項5又は請求項6に記載の製造方法
により得られた回路基板を、少なくとも1枚以上積層し
て接合することを特徴とする多層回路基板の製造方法。
7. A method for manufacturing a multilayer circuit board, comprising laminating and bonding at least one circuit board obtained by the manufacturing method according to claim 5 or 6.
JP2002146832A 2002-05-21 2002-05-21 Circuit board, multilayer circuit board and manufacturing method therefor Withdrawn JP2003338668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002146832A JP2003338668A (en) 2002-05-21 2002-05-21 Circuit board, multilayer circuit board and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002146832A JP2003338668A (en) 2002-05-21 2002-05-21 Circuit board, multilayer circuit board and manufacturing method therefor

Publications (1)

Publication Number Publication Date
JP2003338668A true JP2003338668A (en) 2003-11-28

Family

ID=29705691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002146832A Withdrawn JP2003338668A (en) 2002-05-21 2002-05-21 Circuit board, multilayer circuit board and manufacturing method therefor

Country Status (1)

Country Link
JP (1) JP2003338668A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107516648A (en) * 2016-06-15 2017-12-26 欣兴电子股份有限公司 The manufacture method of circuit board structure
US20180014409A1 (en) * 2016-07-05 2018-01-11 Unimicron Technology Corp. Manufacturing method of circuit board structure
CN110572937A (en) * 2018-06-06 2019-12-13 南昌欧菲显示科技有限公司 Sensor with a sensor element
KR20200022792A (en) * 2018-08-23 2020-03-04 주식회사 엘지화학 Battery pack substrate and Battery pack substrate accessing system

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107516648A (en) * 2016-06-15 2017-12-26 欣兴电子股份有限公司 The manufacture method of circuit board structure
CN107516648B (en) * 2016-06-15 2020-10-16 欣兴电子股份有限公司 Manufacturing method of circuit board structure
US20180014409A1 (en) * 2016-07-05 2018-01-11 Unimicron Technology Corp. Manufacturing method of circuit board structure
US10070536B2 (en) * 2016-07-05 2018-09-04 Unimicron Technology Corp. Manufacturing method of circuit board structure
CN110572937A (en) * 2018-06-06 2019-12-13 南昌欧菲显示科技有限公司 Sensor with a sensor element
CN110572937B (en) * 2018-06-06 2022-07-08 江西卓讯微电子有限公司 Sensor with a sensor element
KR20200022792A (en) * 2018-08-23 2020-03-04 주식회사 엘지화학 Battery pack substrate and Battery pack substrate accessing system
KR102650086B1 (en) * 2018-08-23 2024-03-20 주식회사 엘지에너지솔루션 Battery pack substrate and Battery pack substrate accessing system

Similar Documents

Publication Publication Date Title
TWI305480B (en) Method of fabricating printed circuit board having embedded multi-layer passive devices
JP4538486B2 (en) Multilayer substrate and manufacturing method thereof
JP2001053447A (en) Multilayer wiring board with built-in part and manufacturing method thereof
KR100965341B1 (en) Method of Fabricating Printed Circuit Board
JP3188856B2 (en) Manufacturing method of multilayer printed wiring board
JP2003338668A (en) Circuit board, multilayer circuit board and manufacturing method therefor
JP2004031710A (en) Method for manufacturing wiring board
JP4012022B2 (en) Multilayer wiring substrate, base material for multilayer wiring substrate, and manufacturing method thereof
JP2004134467A (en) Multilayered wiring board, material for it, and method of manufacturing it
JP2003179321A (en) Circuit board, multi-layer circuit board and manufacturing method for circuit board
JP2002185099A (en) Printed circuit board and its manufacturing method
JP2004335726A (en) Method of manufacturing multilayer printed wiring board with cavity
JP2004014559A (en) Circuit board, multilayered circuit board, and method of manufacturing the same
JP2004221192A (en) Multilayer substrate, base material therefor and its manufacturing method
JP2005109299A (en) Multilayer wiring board and its manufacturing method
JP2004193278A (en) Multilayer wiring board, and blank board for it, and its manufacturing method
JP2004221426A (en) Multilayer circuit board, substrate therefor and its manufacturing method
JP2003008222A (en) High-density multilayer build-up wiring board and method of manufacturing the same
JPH1168316A (en) Manufacture of printed wiring board
KR20030047382A (en) The method for manufacturing circuit pattern of printed circuit board using a laser
JP2005175388A (en) Substrate for multilayer substrate, multilevel metallization board, and its manufacturing method
JP2005026587A (en) Multilayer substrate, base material therefor and manufacturing method therefor
JP3858765B2 (en) Film carrier and manufacturing method thereof
JP2001320169A (en) Multilayer circuit board and its manufacturing method
JP2001332855A (en) Method for manufacturing multi-layered wiring board

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20050802