JP2003324183A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP2003324183A
JP2003324183A JP2002131505A JP2002131505A JP2003324183A JP 2003324183 A JP2003324183 A JP 2003324183A JP 2002131505 A JP2002131505 A JP 2002131505A JP 2002131505 A JP2002131505 A JP 2002131505A JP 2003324183 A JP2003324183 A JP 2003324183A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor chip
semiconductor
substrate
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002131505A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003324183A5 (https=
Inventor
Shinji Baba
伸治 馬場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2002131505A priority Critical patent/JP2003324183A/ja
Priority to US10/283,208 priority patent/US20030209808A1/en
Publication of JP2003324183A publication Critical patent/JP2003324183A/ja
Priority to US10/953,059 priority patent/US20050104211A1/en
Publication of JP2003324183A5 publication Critical patent/JP2003324183A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP2002131505A 2002-05-07 2002-05-07 半導体装置 Pending JP2003324183A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2002131505A JP2003324183A (ja) 2002-05-07 2002-05-07 半導体装置
US10/283,208 US20030209808A1 (en) 2002-05-07 2002-10-30 Semiconductor device having semiconductor chips mounted on package substrate
US10/953,059 US20050104211A1 (en) 2002-05-07 2004-09-30 Semiconductor device having semiconductor chips mounted on package substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002131505A JP2003324183A (ja) 2002-05-07 2002-05-07 半導体装置

Publications (2)

Publication Number Publication Date
JP2003324183A true JP2003324183A (ja) 2003-11-14
JP2003324183A5 JP2003324183A5 (https=) 2005-09-29

Family

ID=29397351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002131505A Pending JP2003324183A (ja) 2002-05-07 2002-05-07 半導体装置

Country Status (2)

Country Link
US (1) US20030209808A1 (https=)
JP (1) JP2003324183A (https=)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007274000A (ja) * 2007-05-01 2007-10-18 Seiko Instruments Inc 半導体装置、その製造方法、及び、表示装置の製造方法、
JP2008187050A (ja) * 2007-01-30 2008-08-14 Toshiba Corp システムインパッケージ装置
JP2011192893A (ja) * 2010-03-16 2011-09-29 Zycube:Kk 半導体デバイスの実装方法
US8237289B2 (en) 2007-01-30 2012-08-07 Kabushiki Kaisha Toshiba System in package device
KR20140098160A (ko) * 2011-12-22 2014-08-07 인텔 코포레이션 윈도우 인터포저를 갖는 3d 집적 회로 패키지
JP2015530757A (ja) * 2012-09-27 2015-10-15 インテル・コーポレーション パッケージ基板にダイを含むスタックダイパッケージ
WO2018125061A1 (en) * 2016-12-27 2018-07-05 Intel Corporation Stacking multiple dies having dissimilar interconnect structure layout and pitch
JP2018117160A (ja) * 2009-06-24 2018-07-26 インテル・コーポレーション マルチチップパッケージ

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US6825567B1 (en) * 2003-08-19 2004-11-30 Advanced Semiconductor Engineering, Inc. Face-to-face multi-chip flip-chip package
JP4591886B2 (ja) * 2004-07-21 2010-12-01 ローム株式会社 半導体装置を用いた電源回路装置
US8654538B2 (en) * 2010-03-30 2014-02-18 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US20150255411A1 (en) * 2014-03-05 2015-09-10 Omkar G. Karhade Die-to-die bonding and associated package configurations
US10667399B1 (en) * 2018-11-27 2020-05-26 Nokia Solutions And Networks Oy Discrete component carrier
US11721677B2 (en) 2018-12-27 2023-08-08 Intel Corporation Microelectronic assemblies having an integrated capacitor
JP7210051B2 (ja) * 2019-01-30 2023-01-23 ウルトラメモリ株式会社 半導体モジュール、半導体部材、及びその製造方法
US20240079337A1 (en) * 2022-09-02 2024-03-07 Intel Corporation Microelectronic assemblies having power delivery routed through a bridge die

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW373308B (en) * 1995-02-24 1999-11-01 Agere Systems Inc Thin packaging of multi-chip modules with enhanced thermal/power management
US6515370B2 (en) * 1997-03-10 2003-02-04 Seiko Epson Corporation Electronic component and semiconductor device, method for manufacturing the same, circuit board have the same mounted thereon, and electronic equipment having the circuit board
US6150724A (en) * 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
US6369444B1 (en) * 1998-05-19 2002-04-09 Agere Systems Guardian Corp. Packaging silicon on silicon multichip modules
US6228682B1 (en) * 1999-12-21 2001-05-08 International Business Machines Corporation Multi-cavity substrate structure for discrete devices
JP3677429B2 (ja) * 2000-03-09 2005-08-03 Ｎｅｃエレクトロニクス株式会社 フリップチップ型半導体装置の製造方法
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US6734539B2 (en) * 2000-12-27 2004-05-11 Lucent Technologies Inc. Stacked module package

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008187050A (ja) * 2007-01-30 2008-08-14 Toshiba Corp システムインパッケージ装置
US8237289B2 (en) 2007-01-30 2012-08-07 Kabushiki Kaisha Toshiba System in package device
JP2007274000A (ja) * 2007-05-01 2007-10-18 Seiko Instruments Inc 半導体装置、その製造方法、及び、表示装置の製造方法、
US10763216B2 (en) 2009-06-24 2020-09-01 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US12113026B2 (en) 2009-06-24 2024-10-08 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US11876053B2 (en) 2009-06-24 2024-01-16 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US11824008B2 (en) 2009-06-24 2023-11-21 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US10923429B2 (en) 2009-06-24 2021-02-16 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
JP2018117160A (ja) * 2009-06-24 2018-07-26 インテル・コーポレーション マルチチップパッケージ
US10510669B2 (en) 2009-06-24 2019-12-17 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
JP2011192893A (ja) * 2010-03-16 2011-09-29 Zycube:Kk 半導体デバイスの実装方法
KR20140098160A (ko) * 2011-12-22 2014-08-07 인텔 코포레이션 윈도우 인터포저를 갖는 3d 집적 회로 패키지
US9391013B2 (en) 2011-12-22 2016-07-12 Intel Corporation 3D integrated circuit package with window interposer
JP2015507843A (ja) * 2011-12-22 2015-03-12 インテル・コーポレーション ウィンドウインタポーザを有する３ｄ集積回路パッケージ
JP2015530757A (ja) * 2012-09-27 2015-10-15 インテル・コーポレーション パッケージ基板にダイを含むスタックダイパッケージ
WO2018125061A1 (en) * 2016-12-27 2018-07-05 Intel Corporation Stacking multiple dies having dissimilar interconnect structure layout and pitch

Also Published As

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