JP2003289287A - Data receiving circuit, data receiving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data receiving circuit in which a low speed transmission signal can be prevented from being interrupted upon occurrence of a trouble in the master clock. <P>SOLUTION: A phase monitoring section 6 monitors the write timing and read timing of a buffer memory 4 in a destuff section 2 and delivers a count to an apparatus control section 9 where a decision is made whether a slip trouble is occurring or not. When a slip trouble is occurring, the apparatus control section 9 controls a clock switching section 8 to make a switch immediately from a retiming clock to a DPLL clock thus preventing a low speed transmission signal from being interrupted. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving circuit of an optical transmission communication device which constructs a perfect synchronous network using a master clock, and a data receiving method of this data receiving circuit.

[0002]

2. Description of the Related Art SONET of 51.84 Mb / s or more
(Synchronous Optical NETw
ork) / SDH (Synchronous Digi)
(tal Hierarchy) In order to destuff a high-speed transmission signal to a low-speed transmission signal, the destuffing section is provided with a retiming clock generation function.

The structure and operation of a conventional data receiving circuit will be described with reference to FIG. As shown in FIG. 4, the data receiving circuit separates the high-speed transmission signal (Demult).
DMUX unit 10 for performing (iplex processing) using an in-device clock signal supplied from an external master clock
And a clock and data output from the DMUX unit 10 are subjected to destuffing processing to perform a smoothed clock, a destuffing unit 11 for generating data, and a smoothed clock from the destuffing unit 11. , U which performs signal conversion from bipolar signal to unipolar signal by data U
/ B section 12 and.

Further, the destuffing unit 11 includes a retiming clock generating unit 13 for generating a retiming clock obtained by dividing the internal clock signal into a frequency of a clock signal used for a low-speed transmission signal, and a read timing clock for the retiming clock. And a buffer memory 14 that outputs the data that is input and held from the DMUX unit.

Such a retiming buffer system is
Generally ITU-TG. 813, ITU-TG. 8
This is a method used to comply with the low-speed transmission signal of 2.048 Mb / s jitter standard of No. 23 and the wander standard, and it is naturally assumed that byte stuffing does not occur.

[0006]

However, the AU / TU pointer operation using byte stuffing may be carried out, and the master clock may be damaged or deteriorated in quality. In the SONET / SDH network, in order to adjust the frequency of the high speed side signal, a stuffing pulse is inserted (stuffed) on the data transmitting side and the inserted stuffing pulse is removed (destuffed) on the data receiving side. As a result of performing this pointer operation, a phase gap occurs.

It is unavoidable that the low-speed transmission signal slips (a phenomenon in which the input data is read twice or lost due to the phase fluctuation due to the deviation of the input / output data speed), and the low-speed transmission signal may be disconnected. . This low-speed transmission signal disconnection can only be recovered by the master clock in the data receiving circuit having the above configuration, and the low-speed transmission signal disconnection continues for a long period of time.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a data receiving circuit and a data receiving method capable of avoiding disconnection of a low-speed transmission signal when a failure of a master clock occurs.

[0009]

In order to achieve the above object, the invention described in claim 1 is a SON input from the outside of the device.
ET (Synchronous Optical NE
Network) / SDH (Synchronous Di)
(Gear Hierarchy) A data receiving circuit for extracting a low speed transmission signal from a high speed transmission signal, comprising a storage means for inputting and storing the high speed transmission signal and a first read clock for reading data from the storage means from outside the device. A first clock generating unit that is generated by dividing the master clock of 1) into the frequency of the clock signal used for the low-speed transmission signal, and a write clock to the storage unit,
Input the reference clock from the reference oscillator, compare the phases of the write clock and the second read clock,
A second clock generation unit that generates a second read clock by performing phase control using the reference clock from the reference oscillator based on the comparison result; a first read clock from the first clock generation unit; Selection means for inputting the second read clock from the second clock generation means, selecting and outputting the read clock for the storage means based on an instruction from the control means, and timing for writing data to the storage means and read timing When the read timing is deviated from the write timing, the phase monitoring means for notifying the abnormality and the phase monitoring means for notifying the abnormality causes the read clock of the storage means to change from the first read clock. Control means for issuing an instruction to change to the second read clock.

According to a second aspect of the invention, in the first aspect of the invention, the phase monitoring means reads out a write address indicating a write start position of data generated by dividing a write clock to the storage means, and a read operation. When the phase difference from the read address indicating the read start position of the data generated by dividing the clock is larger or smaller than a predetermined reference value, the count value of the counting means is added and the count value is controlled. It is characterized by notifying the means.

The invention according to claim 3 is the invention according to claim 1 or 2.
In the invention described above, the data receiving circuit inputs a high-speed transmission signal from the outside of the device, and uses an internal device clock generated from a master clock, and uses only the overhead portion of the SONET / SDH frame format as a toothless clock with no clock. , And outputs the data from which the data of the overhead part is removed, and outputs the data without the data of the overhead part to the storage device by using the missing clock as a write clock of the storage device.

According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects, the second clock generation means is a DPLL (Digital Phase Lo).
Cucked Loop) circuit.

According to a fifth aspect of the present invention, there is provided a data receiving method of a data receiving circuit for extracting a low speed transmission signal from a SONET / SDH high speed transmission signal input from the outside of the device,
First clock generation that is generated by dividing a first read clock for reading data from a storage unit that stores a high-speed transmission signal into a frequency of a clock signal used for a low-speed transmission signal from a master clock from the outside of the device The process, the write clock to the storage means, and the reference clock from the reference oscillator are input, the phases of the write clock and the second read clock are compared, and the phase is controlled using the reference clock from the reference oscillator from the comparison result. A second clock generation step of generating a second read clock by performing the above, and a selection step of selecting a read clock for reading data from the storage means by the first read clock and the second read clock. Read data from the storage means using the read clock selected in the selection step A step out, the write timing of data into the storage means and the read timing monitor,
A phase monitoring step of notifying an abnormality when the read timing deviates from the write timing, and the selecting step sets the read clock of the storage means to a first clock when the phase monitoring step notifies the abnormality. It is characterized in that the read clock is switched to the second read clock.

According to a sixth aspect of the present invention, in the fifth aspect of the invention, the phase monitoring step includes a write address indicating a write start position of data generated by dividing the write clock to the storage means, and a read operation. When the phase difference from the read address indicating the read start position of the data generated by dividing the clock is larger or smaller than the predetermined reference value, the count value of the counting means is added and the count value is set to the predetermined value. The abnormality is detected by comparing with the threshold value of.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of a data receiving circuit and a data receiving method of the present invention will be described in detail with reference to the accompanying drawings. 1 to 3, there are shown embodiments of a data receiving circuit and a data receiving method of the present invention.

First, the configuration of an embodiment according to the present invention will be described with reference to FIG. The first embodiment according to the present invention has a DMUX unit 1, a destuff unit 2, a U / B unit 3, a phase monitoring unit 6, and a device control unit 9 as shown in FIG. Further, the destuffing unit 2 includes a buffer memory 4 and a DPLL (Digital Phase Loc).
ed loop) 5, a retiming clock generation unit 7, and a clock switching unit 8.

The DMUX unit 1 mainly receives a SONET / SDH high-speed transmission signal of 51.84 Mb / s or more from the outside of the optical transmission communication device and an in-device clock signal supplied from an external master clock. The DMUX unit 1 separates the input high-speed transmission signal (Demultiplex).
Processing) is performed using the clock signal in the device. By this separation processing, the SONET / SDH shown in FIG.
A missing clock without a clock only in the overhead portion of the frame format and data obtained by removing the data in the overhead portion shown in FIG. 2B (data in the payload portion, where there is empty data, only the payload portion) To generate.

The destuffing unit 2 outputs a clock without a clock in only the overhead portion output from the DMUX unit 1 and data from which the data in the overhead portion is removed, and a clock from a reference oscillator (hereinafter referred to as a reference OSC). And an in-device clock signal generated from the master clock signal are input to perform destuffing processing. The destuffing process generates a smoothed clock and data.

The U / B unit 3 uses the smoothed clock and data from the destuffing unit 2 to convert a bipolar signal into a unipolar signal.

Further, the buffer memory 4 in the destuffing section 2 writes a toothless clock having no clock only in the overhead portion output from the DMUX section 1 as a writing clock,
The data excluding the data in the overhead part is input as the write data. In addition, the retiming clock from the retiming clock generator 7 or the DPLL
Data is read using the DPLL clock from 5 as a read clock.

The DPLL 5 inputs the toothless clock having no clock only in the overhead portion from the DMUX unit 1 and the reference clock from the reference OSC, compares the phases of the write clock (toothless clock) and the DPLL clock, A DPLL clock is generated by controlling the phase from the comparison result using the reference clock from the reference OSC.

The retiming clock generator 7 divides the internal clock signal into the frequency of the clock signal used for the low-speed transmission signal to generate a retiming clock.

Under the control of the device control unit 9, the clock switching unit 8 sets the read clock of the buffer memory 4 to DP
The DPLL clock from the LL 5 and the retiming clock from the retiming clock generator 7 are switched.

The operation of the phase monitor 6 will be described with reference to FIG. The phase monitoring unit 6 calculates the write address indicating the write start position of the data generated by dividing the write clock and the phase of the read address indicating the read start position of the data generated by dividing the read clock. Compare. Specifically, the phase of the determination signal generated by dividing the write address is compared with the phase of the read address, and when these phases overlap, the counter is counted up. As shown in FIG. 3, the determination signal rises at the rising edge of the write address and falls at a predetermined interval, and rises at a certain interval from the falling edge of this pulse and rises at the rising edge of the write address. It consists of a falling pulse. The count value of the counter is output to the device control unit 9.

As shown in FIG. 3, if a write clock has a phase gap due to byte stuffing (see FIG. 3).
Write clock B) and the read address phase deviate from the write address phase, and the write address phase approaches the read address phase (read clock B in FIG. 3) or moves away (see FIG. 3 read clock C).

The device control unit 9 acquires the count value of the counter from the phase monitoring unit 6, and when the count value becomes larger than the threshold value, the read clock of the buffer memory 4 is retimed by the retiming clock generation unit 7. It issues an instruction to change from the clock to the DPLL clock of DPLL5. The device control unit 9 also performs alarm monitoring, status change monitoring, command execution control, etc. for the entire optical transmission communication device.

Next, the operation procedure of this embodiment having the above-mentioned configuration will be described. The DMUX unit 1 separates a SONET / SDH high-speed signal of 51.84 Mb / s or more input from the outside of the optical transmission communication device. The DMUX unit 1 performs separation processing by using the in-device clock signal supplied from the master clock, and removes the toothless clock having no clock only in the overhead portion and the data obtained by removing the data in the overhead portion shown in FIG. To generate.

The data generated by the DMUX unit 1 from which the data of the overhead portion has been removed is written in the buffer memory 4 by using a toothless clock having no clock only in the overhead portion as a write clock.

The clock switching section 8 outputs the retiming clock from the retiming clock generating section 7 as a read clock of the buffer memory 4 in a normal state where no abnormality occurs in the master clock.

The data written in the buffer memory 4 is read using the retiming clock from the retiming clock generator 7 as a read clock, and U / B
The part 3 converts the bipolar signal into a unipolar signal.

Further, the phase monitoring unit 6 includes a buffer memory 4
The data writing timing and the data reading timing are constantly monitored. The phase monitoring unit 6 calculates the write address indicating the write start position of the data generated by dividing the write clock and the phase of the read address indicating the read start position of the data generated by dividing the read clock. By comparison, when the phases of these pulses approach or move away from each other, the value of the counter is incremented. More specifically, by using the determination signal shown in FIG. 3 generated by dividing the write address, when a portion where the phase of this determination signal and the phase of the read address overlap is formed, the counter is Count up. The count value of the counter is output to the device control unit 9.

The device control section 9 acquires the count value of the counter from the phase monitoring section 6, and when the count value becomes larger than the threshold value, the read clock of the buffer memory 4 is retimed by the retiming clock generation section 7. An instruction to change from the clock to the DPLL clock of the DPLL 5 is output.

In response to an instruction from the device control unit 9, the clock switching unit 8 sets the read clock of the buffer memory 4 to the DPL generated by the DPLL 5 from the retiming clock.
Switch to L clock.

As described above, in this embodiment, the destuffing unit 2
The write timing and the read timing of the buffer memory 4 in the internal unit are monitored by the phase monitoring unit 6 and the count value is sent to the device control unit 9, so that the device control unit 9 determines whether or not a slip failure has occurred. To be done. Therefore,
When a slip failure occurs, the device control unit 9 controls the clock switching unit 8 so that the retiming clock causes the DP
By switching to the LL clock immediately, it is possible to avoid a low speed transmission signal disconnection.

The above-described embodiment is a preferred embodiment of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention. For example, although the low-speed transmission signal is described as 2.048 Mb / s in the above-described embodiment, it can be applied to a DS1 signal of 1.544 Mb / s.

[0036]

As is apparent from the above description, according to the present invention, the writing timing and the reading timing of the storage means are monitored by the phase monitoring means and the count value is notified to the control means. It is determined whether or not a failure has occurred. Therefore, when a slip failure occurs, the control unit controls the selection unit to immediately switch from the first read clock to the second read clock, thereby avoiding the disconnection of the low-speed transmission signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment according to the present invention.

FIG. 2 is a diagram for explaining the processing of the DMUX unit 1.

FIG. 3 is a diagram for explaining a process of a phase monitoring unit 6.

FIG. 4 is a block diagram showing a configuration of a conventional data receiving circuit.

[Explanation of symbols]

1 DMUX section 2 Destuff department 3 U / B section 4 buffer memory 5 DPLL 6 Phase monitor 7 Retiming clock generator 8 clock switching section 9 Device control section

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5K028 AA14 BB08 NN22 NN23 NN32                       PP02 PP15 SS24                 5K047 AA12 BB02 CC02 GG02 GG07                       GG44 GG45 GG52 KK02 KK12                       KK15 MM24 MM55                 5K102 AA44 AC01 LA52 RD04 RD22

Claims (6)

[Claims] 1. SONET (Sy input from the outside of the device
nchronous Optical NETwork)
/ SDH (Synchronous Digital)
Hierarchy) A data receiving circuit for extracting a low-speed transmission signal from a high-speed transmission signal, comprising: storage means for inputting and storing the high-speed transmission signal; and a first read clock for reading data from the storage means external to the device. The first clock generating means, which is generated by dividing the master clock from the above into the frequency of the clock signal used for the low-speed transmission signal, the write clock to the storage means, and the reference clock from the reference oscillator are input. Second clock generation means for generating a second read clock by comparing the phases of the write clock and the second read clock and performing phase control using the reference clock from the reference oscillator from the comparison result. A first read clock from the first clock generation means; Selection means for inputting the second read clock from the second clock generation means, selecting and outputting the read clock of the storage means based on an instruction from the control means, and timing of writing data to the storage means. The read timing is monitored, and when the read timing deviates from the write timing, an abnormality is notified to the phase monitoring means, and when the phase monitoring means notifies the abnormality, the read clock of the storage means is changed to the first clock. And a control unit that gives an instruction to change from one read clock to the second read clock. 2. The phase monitoring means reads a write address indicating a write start position of data generated by dividing a write clock to the storage means, and reading data generated by dividing a read clock. When the phase difference from the read address indicating the start position is larger or smaller than a predetermined reference value, the count value of the counting means is added and the count value is notified to the control means. 1. The data receiving circuit according to 1. 3. The data receiving circuit receives the high-speed transmission signal from the outside of the device, and uses an in-device clock generated from the master clock,
Only the overhead portion of the ONET / SDH frame format has no clock, and the data with the data of the overhead portion removed is generated and output, and the tooth loss clock is used as the write clock of the storage means. 3. The data receiving circuit according to claim 1, further comprising a separating unit that writes the data from which the data has been removed into the storage unit. 4. The second clock generation means is a DPL
L (Digital Phase Locked Loo
4. The data receiving circuit according to claim 1, wherein the data receiving circuit is a p) circuit. 5. SONET / SD input from outside the device
H A data receiving method of a data receiving circuit for extracting a low-speed transmission signal from a high-speed transmission signal, wherein a first read clock for reading data from a storage unit storing the high-speed transmission signal is a master clock from outside the device. A first clock generation step of generating by dividing the frequency of a clock signal used for the low-speed transmission signal; a write clock to the storage means; and a reference clock from a reference oscillator, A second clock generation step of generating a second read clock by comparing the phases of the second read clocks and performing phase control using the reference clock from the reference oscillator based on the comparison result; A read clock for reading data from the first read clock and the second read clock; A selection step of selecting with a read clock, a read step of reading data from the storage means using the read clock selected in the selection step, and a timing of writing data to the storage means and a read timing of the data are monitored. And a phase monitoring step of notifying an abnormality when a read timing is deviated from a write timing, and the selection step, when the abnormality is notified from the phase monitoring step, a read clock of the storage means. Is switched from the first read clock to the second read clock. 6. The phase monitoring step includes: a write address indicating a write start position of data generated by dividing a write clock to the storage means; and reading data generated by dividing a read clock. When the phase difference with the read address indicating the start position is larger or smaller than a predetermined reference value, the count value of the counting means is added, and the abnormality is detected by comparing the count value with a predetermined threshold value. The data receiving method according to claim 5, wherein