JPH0870289A - Data transmission system, stuff multiplex transmitter and receiver used therefor - Google Patents

Abstract

PURPOSE: To attain stable operation even on the occurrence of a fault in a transmission line with low power consumption with a small size and to minimize the effect of jitter in the cascade connection. CONSTITUTION: Input data from a terminal equipment 8 to a communication node are written in a buffer memory in a stuff multiplex transmission section 10, in which a prescribed additional bit is inserted and the resulting data are sent to a transmission line 6. The data are received by an opposite station node, in which the additional bit is eliminated and the resulting data are written in a buffer memory in a stuff multiplex reception section 20, in which data before stuff multiplex are reproduced. In the position reset operation of a write/ read clock signal in the stuff multiplex transmission section 10, a position reset service code as the additional bit is inserted in transmission data and the result is sent to an opposite station. A stuff multiplex reception section 20 of the opposite station executes the position reset operation similarly to that.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system, and more particularly to a data transmission system using a staff synchronous multiplex technique adopted in a digital communication system.

[0002]

2. Description of the Related Art As is well known, the stuff synchronization method is a kind of synchronization method used in the field of digital communication using a time division multiplex communication method. In this stuff synchronization method, the basic repetition frequency of the synchronization signal is selected to be slightly higher than that of the original signal (asynchronous signal), and an invalid bit called a stuff pulse that does not transmit information to the synchronization signal as necessary. Is provided, the reading of the asynchronous signal is stopped for one bit, and the phase deviation is corrected. The position information of the stuff pulse is separately transmitted to the receiving side, and based on the information, the receiving side destuffs it and corrects the phase change to reproduce the original asynchronous signal.

Conventionally, as a device for realizing the stuff synchronization system as described above, a device described in, for example, "Digital Communication Circuit" (Sangyo Tosho Co., Ltd., February 1990, pages 122 to 124) is known. ing. Hereinafter, the conventional stuff synchronization technique disclosed in the above document will be described with reference to FIGS. 17 and 18.

FIG. 17 shows a conventional stuff multiplex transmission apparatus described in the above document. In FIG. 17, this stuff multiplex transmission device includes a buffer memory 101,
Phase comparator 102 and stuff & frame control circuit 10
3, additional bit generation circuit 104, and multiplexing circuit 105
Output clock oscillator 106 and AND gate 107
And a prohibition gate 108.

Next, the operation of the stuff multiplex transmission device shown in FIG. 17 will be described. First, in the buffer memory 101,
Input data and an input clock signal are given from a terminal (a personal computer or the like) not shown. The input clock signal is given to the buffer memory 101 as a write clock signal. Therefore, the input data from the terminal is stored in the buffer memory 101 in synchronization with the timing of the input clock signal. The output clock oscillator 106 synchronizes with the transmission clock of the transmission line L,
It also produces an output clock signal having a higher frequency than the input lock signal. This output clock signal is supplied to the buffer memory 101 as a read clock signal via the prohibition gate 108. Therefore, data is read from the buffer memory 101 in synchronization with the output clock signal and at a speed faster than that at the time of storage.

The phase comparator 102 includes a buffer memory 10
The phase difference between the write clock signal of 1 and the read clock signal is constantly monitored, and when the difference becomes less than a certain value (that is, immediately before the read clock signal overtakes the write clock signal), the stuff bit is inserted into the frame. The request is output to the stuff & frame control circuit 103. Accordingly, the stuff & frame control circuit 103
A read inhibit pulse is generated and output to the inhibit gate 108. The inhibition gate 108 is closed in response to the read inhibition pulse, and inhibits the output clock signal from the output clock oscillator 106 to the buffer memory 101. As a result, the output clock signal provided to the buffer memory 101 is in a missing state. In this missing portion, meaningless data, that is, the stuff bit is read from the buffer memory 101.

When an additional bit for transmitting information such as an alarm to the partner station is transmitted, the additional bit generating circuit 1
04 generates an additional bit at a predetermined position in the frame notified from the stuff & frame control circuit 103.
This additional bit is inserted into the data read from the buffer memory 101 in the AND gate 107. The multiplexing circuit 105 time-division-multiplexes the output data of the AND gate 107 with the output data from another stuff multiplex transmission device (not shown), and sends out the data onto the transmission line L.

Each signal multiplexed and transmitted on the transmission line L is composed of periodically continuous frames, and each frame has an information section for carrying data, a frame synchronization flag for identifying the frame, and transmission. It is composed of a service encoding unit including road monitoring information and the like. The service code portion also includes stuff bits used for synchronization when the input data from the terminal is multiplexed on the transmission line L.

FIG. 18 shows a conventional stuff multiplex receiver described in the above-mentioned document. In FIG.
This stuff multiplex reception apparatus includes a separation circuit 201, a frame synchronization circuit 202, and an additional bit removal control circuit 203.
A buffer memory 204, a PLL (Phase Locked Loop) circuit 205, and an inhibit gate 206. The PLL circuit 205 is used for the phase comparator 20.
5a, a low pass filter 205b, and a VCO (voltage controlled oscillator) 205c.

Next, the operation of the stuff multiplex receiver shown in FIG. 18 will be described. The demultiplexing circuit 201 demultiplexes a plurality of signals multiplexed and transmitted on the transmission line L into reception data and a reception clock signal for each stuff multiplex reception device. The frame synchronization circuit 202 monitors the received data. Further, the frame synchronization circuit 202 detects frame synchronization by counting the received clock signals. The additional bit removal control circuit 203 includes the frame synchronization circuit 20.
When the detection result of the frame synchronization is obtained from 2, the additional bit removing pulse is generated at the timing when the additional bits other than the information bits appear in the reception clock signal according to the predetermined frame structure, and the pulse is output to the prohibiting gate 206. The inhibit gate 206 is closed in response to the additional bit removal pulse to remove additional bits from the received clock signal.
As a result, the reception clock signal is converted into an input clock signal in which the portion from which the additional bits have been removed is in a toothless state. The input clock signal is given to the buffer memory 204 as a write clock signal. Therefore, the reception data is accumulated in the buffer memory 204 at the timing synchronized with the input clock signal.

On the other hand, in the PLL circuit 205, the phase difference between the write clock signal and the read clock signal of the buffer memory 204 is detected by the phase comparator 205a, and the output of the phase comparator 205a is smoothed by the low pass filter 205b. , An output clock signal having a frequency according to the output voltage of the low pass filter 205b is input to the VCO 205.
It occurs at c. As a result, the write clock signal having the missing part is smoothed, and the output clock having the same frequency as the input clock signal input to the stuff multiplex transmission device 100 of FIG. 17 (clock signal input from a terminal not shown). It is reproduced as a signal. This output clock signal is given to the buffer memory 204 as a read clock signal. Therefore, the buffer memory 20
From 4, the output data is read in synchronization with the output clock signal.

[0012]

According to the conventional stuff synchronization method described above, the buffer memory 10 on the transmission side is provided.
Since writing and reading of data to and from the buffer memory 204 of 1 and the receiving side are performed serially for each bit, if the data transmission speed on the transmission line L becomes high, many high-speed elements such as ECL must be used. I won't. However, since high-speed elements such as ECL have a low degree of integration, using a large number of such elements causes a problem that the circuit scale of the buffer memories 101 and 204 becomes large and the power consumption becomes large.

Further, in the conventional stuff multiplex receiver shown in FIG. 18, the read clock signal given to the buffer memory 204 is reproduced using the PLL circuit 205 based on the phase difference from the write clock signal. For example, when an abnormality occurs in the transmission line L and the frame synchronization is lost, the write clock signal generated based on the frame structure becomes abnormal, and the read clock that is reproduced by smoothing the write clock signal. The signal will also be abnormal. As a result, the write clock signal and the read clock signal deviate from the predetermined positional relationship, and the read clock signal overtakes the write clock signal,
There is a risk that a so-called burst error may occur in which all bits are in error.

Further, in the case of a network in which the stuff multiplex receivers and the stuff multiplex transmitters are connected in cascade, conventionally, a clock regenerated in the stuff multiplex receiver is used, and the clock is used in the next stage. Data will be transmitted to the transmission line. However,
Since the stuff jitter is superimposed on the recovered clock, the stuff jitter accumulates and superimposes on the recovered clock in the downstream devices connected in cascade, which causes a problem in reliability. .

Therefore, a first object of the present invention is to provide a stuff multiplex transmission apparatus and a reception apparatus which are small in size and consume less power. A second object of the present invention is to provide data capable of promptly restoring the relationship between the read clock signal and the write clock signal to a predetermined relationship when the transmission path becomes stable even when an abnormality occurs in the transmission path. It is to provide a transmission system. A third object of the present invention is to provide a data transmission system capable of minimizing the accumulation of stuff jitter in a network in which a stuff multiplex transmitter and a stuff multiplex receiver are connected in a ring shape. .

[0016]

The invention according to claim 1 is
A stuff multiplexing transmitter that stuff-multiplexes input data serially input in synchronization with an input clock signal and serially outputs each frame on a transmission line that operates asynchronously with the input clock signal.
/ M frequency division means for generating a write clock signal by frequency division / m, serial / parallel conversion means for converting input data into parallel data having an m-bit width, and an input clock synchronized with the transmission clock signal on the transmission path. Output clock signal generating means for generating an output clock signal having a frequency higher than that of the signal, 1 / n frequency dividing means for generating a read clock signal by dividing the output clock signal by 1 / n, at least k bits (k> n) , M) for temporarily storing and holding the data, and in synchronization with the write clock signal, the write control means for writing the output data of the serial / parallel conversion means into the memory means in order of m bits in synchronization with the read clock signal. Read control means for reading data of a bit width (0 to n bit width) corresponding to the frame structure from the storage means, Phase difference detection means for detecting a phase difference between the clock signal and the read clock signal, data read from the storage means is detected at a predetermined frame position or by the phase difference detection means. When the phase difference becomes less than or equal to a predetermined value, an additional bit is inserted and parallel data having an n-bit width is output, and parallel data having an n-bit width output from the additional bit inserting means is converted into serial data. It is equipped with parallel / serial conversion means for converting to.

The invention according to claim 2 is the invention according to claim 1, further comprising position reset means for resetting the positional relationship between the write clock signal and the read clock signal to a predetermined positional relationship. And

According to a third aspect of the invention, in the second aspect of the invention, the additional bit inserting means is predetermined for the data read from the storage means when the position resetting means executes the position resetting operation. The service code for position reset is inserted at the frame position.

According to a fourth aspect of the present invention, the stuff-multiplexed data and clock signal are received from the transmission line, and the received data and the received clock signal are converted into original data and original clock signal before stuff-multiplexing. Stuff multiplex receiver of the
/ N frequency-dividing means for generating a write clock signal by frequency division, serial / parallel conversion means for converting received data into parallel data having an n-bit width, and determination means for determining the insertion position of the additional bit in the received data. Read clock generation means for generating a read clock signal based on the determination result of the determination means, at least k bits (k>
(n, m) data is temporarily stored and held, and the additional bit is removed from the output data of the serial / parallel conversion means based on the determination result of the determining means, and the data from which the additional bit is removed is removed. M from the storage means in synchronization with the write control means for writing to the storage means in synchronization with the write clock signal and the read clock signal.
A read control unit for sequentially reading parallel data having a bit width is provided.

According to a fifth aspect of the invention, in the invention of the fourth aspect, when the determining means determines that the position reset service code is inserted in the received data, the write clock signal and the read clock signal are between It is further characterized by further comprising a position resetting means for resetting the positional relationship of (1) to a predetermined positional relationship.

According to a sixth aspect of the present invention, in the fifth aspect of the invention, the parallel data having an m-bit width constitutes a block code composed of a data code, a control code and an invalid code,
In the block code decoding unit that restores the parallel data read by the read control unit to the original data, and the block code decoding unit, when invalid codes are continuously received, the positional relationship between the write clock signal and the read clock signal is shown. It is characterized by further comprising position reset means for resetting to a predetermined positional relationship.

According to a seventh aspect of the present invention, there is provided a data transmission system in which a plurality of communication nodes each having a terminal connected thereto are communicably coupled to each other through a ring type transmission line, and each communication node is connected to Stuff-multiplexing device that stuff-multiplexes input data that is serially input in synchronism with the input clock signal and serially outputs each frame on a transmission line that operates asynchronously with the input clock signal, and stuff-multiplexing is performed from the transmission line. And a stuff multiplex receiver for converting the received data and the received clock signal into the original data and the original clock signal before the stuff multiplex,
The transmission path is selected so that the normal system used during normal operation and the transmission direction are opposite to those of the normal system, and when an error occurs in the transmission path, it cooperates with the normal system and loops back before the abnormal position. The stuff multiplex receiver comprises a 1 / n frequency dividing means for frequency-dividing the received clock signal by 1 / n to generate a write clock signal,
A serial / parallel conversion means for converting the received data into parallel data having an n-bit width, a determination means for determining the insertion position of the additional bit in the received data, and a read clock for generating a read clock signal based on the determination result of the determination means. Generating means and at least k bits (k>
(n, m) storage means for temporarily storing and holding data,
Based on the determination result of the determination means, the additional bit is removed from the output data of the serial / parallel conversion means, and
Write control means for writing the data from which the additional bits are removed to the storage means in synchronization with the write clock signal, and m from the storage means in synchronization with the read clock signal.
A positional relationship between the write clock signal and the read clock signal when the read control means for sequentially reading parallel data having a bit width and the determination means determine that the position reset service code is inserted in the received data. Position resetting means for resetting the position to a predetermined positional relationship, and in the backup system, a code having the same logic as the position reset service code is set in advance in all transmission line codes, whereby the transmission line When the normal system and the standby system cooperate with each other to form an emergency transmission line when an abnormality occurs, the stuff multiplex receiver in the downstream communication node looped back changes the code set in the standby system to the position reset code. By receiving as a positional relationship between the write clock signal and the read clock signal by the internal position reset means. Characterized by resetting a predetermined positional relationship.

According to an eighth aspect of the present invention, there is provided a data transmission system in which a plurality of communication nodes, each of which is connected to a terminal, are communicably coupled to each other via a ring type transmission line, and each communication node is a transmission line. A stuff multiplex receiver that receives the stuff-multiplexed data and clock signal from the stuff-multiplexer and converts them to the original data and the original clock signal before stuff-multiplexing, and an operation that generates an operating clock with a frequency approximately equal to the input clock from the terminal A clock source and a first elastic buffer that stores input data that is input in synchronization with an input clock signal from a terminal in synchronization with the input clock signal and reads out stored data in synchronization with an operation clock, and a stuff The original data output from the multiplex receiver is stored in synchronization with the original clock signal and synchronized with the operating clock. Stuff that stuff-multiplexes the data read from the second elastic buffer for reading stored data and the first or second elastic buffer for each frame and serially outputs the data on a transmission line that operates asynchronously with the operation clock. And a multiplex transmission device.

[0024]

According to the first aspect of the present invention, since writing and reading of data to and from the storage means are performed in parallel, the power consumption of the storage means is low and the integration degree is high even if the transmission speed of the transmission line is high. It can be composed of high and low speed circuit elements. As a result, it is possible to reduce the size and power consumption of the device.

According to the second aspect of the present invention, by providing the position resetting means for resetting the positional relationship between the write clock signal and the read clock signal to a predetermined positional relationship, at the time of starting communication or restarting. In, the phase of the write clock signal and the read clock signal can be matched, and the occurrence of burst errors and the like can be prevented.

In the invention according to claim 3, when the position resetting means executes the position resetting operation, the position resetting service code is inserted into the data read from the storing means at a predetermined frame position. As a result, it is possible to instruct the communication partner station to execute the position reset.

According to the fourth aspect of the present invention, since the data writing and the data reading are performed in parallel to the storage means, even if the transmission speed of the transmission line is high, the storage means consumes less power and has a high degree of integration. It can be composed of high and low speed circuit elements. As a result, it is possible to reduce the size and power consumption of the device.

In the invention according to claim 5, when the judging means judges that the position reset service code is inserted in the received data, the positional relationship between the write clock signal and the read clock signal is determined to be predetermined. Since the position is reset, the position can be reset internally in response to the position reset operation in the stuff multiplex transmission device at the transmission destination.

In the invention according to claim 6, when the block code decoding section continuously receives invalid codes,
Since the position resetting means resets the positional relationship between the write clock signal and the read clock signal to a predetermined positional relationship, it becomes possible to promptly perform the position reset when a device abnormality occurs.

In the invention according to claim 7, when an abnormality occurs in the transmission line and an emergency transmission line is formed by the normal system and the standby system, the stuff multiplex reception apparatus in the downstream communication node looped back. The internal position reset means can reset the positional relationship between the write clock signal and the read clock signal to a predetermined positional relationship by receiving a code preset in the standby system as a position reset code. it can. Therefore, even when an abnormality occurs in the transmission path, the write clock signal and the read clock signal of the storage means always operate with a constant interval, and stable operation can be performed without causing a burst error in the reproduced data. It will be possible.

In the invention according to claim 8, the input data from the terminal is stored in the first elastic buffer. In addition, the data received from the transmission line is stored in the second elastic buffer after being converted into the original data. The first elastic buffer stores data in synchronization with the input clock from the terminal, and the second elastic buffer stores data in the original clock obtained from the clock received from the transmission path. It is done in synchronization with. The data read from the first or second elastic buffer is transmitted to the transmission path by stuff multiplexing. Each communication node is provided with an independent operation clock source, and reading of data from the first and second elastic buffers is performed in synchronization with the operation clock generated from this operation clock source. This makes it possible to reduce stuff jitter, which is a problem when the stuff multiplex transmission device and the stuff multiplex reception device are continuously connected.

[0032]

【Example】

(Embodiment 1) FIG. 1 is a block diagram showing the configuration of a ring type transmission system using a stuff multiplex transmission apparatus and a reception apparatus according to the first embodiment of the present invention. In FIG. 1, a plurality of communication nodes 500a to 500d are communicatively coupled to each other by a stuff-multiplexed ring type trunk transmission line 6. Also, each communication node 500a-
One or a plurality of terminals (personal computers, etc.) 8 are connected to 500d via a branch transmission line 7.

Each of the communication nodes 500a to 500d has
Transmission line control unit 300 for controlling the transmission state of the main transmission line 6
And a terminal accommodating unit 400 for performing data input / output interface with the terminal 8, and transmitting data from the terminal 8 to the trunk transmission line 6 using a stuff multiplexing technique, including control bits such as stuff bits. A staff multiplex transmission unit 10 having a function of transmitting, and a staff multiplex reception unit having a function of deleting control bits such as stuff bits from data received from the trunk transmission line 6 and extracting only an information unit to notify the terminal accommodating unit 400. 20 and 20 are provided.

As the main transmission line 6, two systems such as a normal system 61 and a standby system 62 are prepared. The transmission direction of the standby system 2 is selected to be opposite to that of the normal system 61.
Communication during normal operation is performed using the normal system 61.
When an abnormality occurs in the transmission line, as shown in FIG. 2, the normal system 61 and the backup system 62 cooperate to form an emergency transmission line looped back before the position where the abnormality occurs, This avoids communication failures.

The frame structure of the normal system 61 in the main transmission line 6 is generated by the stuff multiplex transmission unit 10 in the upstream communication node in each transmission line. For example, the stuff multiplex transmission unit 10 in the communication node 500a generates a frame transmitted in the normal system 61 between the communication nodes 500a and 500d. In normal operation, the backup system 62 of the trunk transmission line 6 does not have a frame structure, and all the bits, that is, the transmission line code, are set to "1".
Controlled in.

As will be described later, the stuff multiplex reception section 20 in each communication node is provided with a position reset circuit, and when a frame in which the position reset service code is set to "1" is received, the internal buffer memory is written. It has a function of resetting the clock signal and the read clock signal to predetermined positions.

FIG. 3 is a block diagram showing the configuration of one stuff multiplex transmission device 100 included in the stuff multiplex transmission unit 10 shown in FIG. It should be noted that such a staff multiplex transmission device 100 is used for the terminal 8 connected to the communication node.
It is provided for each of. In FIG. 3, the stuff multiplex transmission device 100 includes a 1 / m frequency divider 111,
Serial / parallel converter 112 and buffer memory 1
13, output clock oscillator 114, and 1 / n frequency divider 1
15, a phase comparator 116, a stuff & frame control circuit 117, a read bit control circuit 118, an additional bit generation circuit 119, and a parallel / serial converter 1.
20 and a position reset instruction circuit 121.
It should be noted that the buffer memory 113 includes the selection signal generator 11
3a, transmission input distributor 113b, and memory circuit 113
c, the transmission output selector 113d, and the parallel port 1
13e and.

FIG. 4 is a block diagram showing in more detail the configuration of the write side in the buffer memory 113 of FIG. In FIG. 4, the selection signal generation circuit 113a includes 1
The write clock signal from the / m frequency divider 111 and the reset pulse from the position reset instruction circuit 121 are applied. The selection signal generation circuit 113a generates k / m selection signals. Note that k is selected to be an integral multiple of m.

The memory circuit 113c is composed of k D-type flip-flops F (1) to F (k) arranged in parallel. These k D-type flip-flops are divided into k / m groups each having m pieces. The k / m selection signals output from the selection signal generation circuit 113a are applied to the respective clock terminals of the D-type flip-flops belonging to the corresponding groups. For example, the first selection signal is given to each clock terminal of the D-type flip-flops F (1) to F (m) belonging to the first group. The second selection signals are D-type flip-flops F (m + 1) to F belonging to the second group.
It is given to each clock terminal of (2 m). Similarly, the k / mth selection signals are flip-flops F (k−m + 1) to F belonging to the k / mth group.
(K) is given to each clock input terminal.

The transmission input distributor 113b distributes the m-bit parallel data output from the serial / parallel converter 112 to the D flip-flops of each group of the memory circuit 113c. For example, the first bit data of the serial / parallel converter 112 is the first D-type flip-flops F (1) and F (m + 1) of each group.
,, F (k-m + 1) data input terminal.
The data of the second bit is the second D-type flip-flops F (2), F (m + 2) ..., F of each group.
It is given to the data input terminal of (km + 2). Similarly, the m-th bit data is the m-th D-type flip-flop F (m), F (2m) ..., F of each group.
It is given to the data input terminal of (k).

FIG. 5 is a block diagram showing the structure of the read side in the buffer memory 113 of FIG. 3 in more detail. In FIG. 5, the transmission output selector 113d is composed of n selectors S (1) to S (n).
Each of the selectors S (1) to S (n) has a memory circuit 1
Parallel data of k bits is provided in parallel from the D-type flip-flops F (1) to F (m) of 13c. In addition, each of the selectors S (1) to S (n) is supplied from the read bit control circuit 118 with a pointer value representing the leading value of the read bit and length data representing the read bit width. Each of the selectors S (1) to S (n) also has a function of decoding the pointer value and the bit width data, and selects 1-bit data from the k-bit parallel data based on the decoding result. , To the parallel port 113e. The additional bit data from the additional bit generating circuit 119 is also applied to the parallel port 113e. Parallel port 113e
Is configured to combine the output data of the selectors S (1) to S (n) and the additional bit data given from the additional bit generation circuit 119, output n-bit parallel data, and give it to the parallel / serial converter 120.

FIG. 6 is a block diagram showing the configuration of one stuff multiplex receiving apparatus 200 included in the stuff multiplex receiving section 20 shown in FIG. It should be noted that such a staff multiplex reception device 200 is provided in the terminal 8 connected to the communication node.
It is provided for each of. In FIG. 6, the stuff multiplex reception device 200 includes a 1 / n frequency divider 211,
Serial / parallel converter 212, frame synchronization circuit 213, additional bit removal control circuit 214, write bit control circuit 215, buffer memory 216, P
An LL circuit 217, a position reset circuit 218, and a block code decoding unit 219 are provided. The buffer memory 216 includes a reception input selector 216a, a memory circuit 216b, a reception output selector 216c, and a ring counter 216d. In addition, the PLL circuit 217
Is a phase comparator 217a and a low pass filter 217b.
And VCO 217c.

FIG. 7 is a block diagram showing in more detail the configuration of the write side in the buffer memory 216 of FIG. In FIG. 7, the reception input selector 216a is composed of k selectors S ′ (1) to S ′ (k). The memory circuit 216b is composed of k D-type flip-flops F ′ (1) to F ′ (k). Each of the selectors S ′ (1) to S ′ (k) is provided with n-bit parallel data from the serial / parallel converter 212 in parallel. Also, the selector S '
The outputs of the corresponding D-type flip-flops F ′ (1) to F ′ (k) are fed back and input to (1) to S ′ (k), respectively. Furthermore, each selector S '(1)
The write bit control circuit 215 supplies a pointer value representing the leading value of the write bit and length data representing the write bit width to S ′ (k). Each of the selectors S ′ (1) to S ′ (k) also has a function of decoding the pointer value and the bit width data, and based on the decoding result, feedback of n-bit parallel data and the corresponding D-type flip-flop. 1-bit data is selected from the inputs and output to the data terminals of the corresponding D-type flip-flops F ′ (1) to F ′ (k). Also, each D-type flip-flop F ′
A write clock signal is applied from the 1 / n frequency divider 211 to the clock terminals (1) to F ′ (k).

FIG. 8 is a block diagram showing the configuration of the receiving side in the buffer memory 216 of FIG. 6 in more detail.
In FIG. 8, the reception output selector 216c is composed of m selectors S ″ (1) to S ″ (m). The output of the memory circuit 216b is provided to every selector S "(1) to S" (m) every m bits. For example, the selector S ″ (1) has the first bit and the m + 1th bit.
The output of the bit, ..., The (k−m + 1) th bit is given. Further, the selector S ″ (2) is provided with the output of the second bit, the m + 2th bit, ..., The k−m + 2th bit. An output of 2m bits, ..., Kth bit is given. The ring counter 216d is supplied with the output clock signal of the PLL circuit 217 and the reset pulse from the position reset circuit 218. The ring counter 216d counts the output clock signal of the PLL circuit 217, and the count signal is given to each of the selectors S ″ (1) to S ″ (m) as a selection bit instruction signal. Each selector S "(1) to S"
(M) selects and outputs the predetermined bit input according to the count signal from the ring counter 216d.

FIG. 9 shows the conversion contents of a 4B5B block code in which 4-bit data is converted into a 5-bit transmission line code as a transmission line code, as an example of the block code. In FIG. 9, a data section 91 indicates a set of transmission path codes converted when the original signal is data, a control section 92 indicates a set of codes used as a control code as a transmission path code, and an invalid section 93 indicates It refers to a set of codes that are not used as transmission line codes. In FIG. 9, the first 1 bit (the leftmost bit) of the internal data representation is a bit indicating the data part, the control part, or the invalid part, and has no meaning as data.

FIG. 10 is a timing chart for explaining the operation at the time of writing data in the stuff multiplex transmission device 100 shown in FIG. FIG. 11 is a timing chart for explaining an operation at the time of reading data in the stuff multiplex transmission device 100 shown in FIG. FIG. 12 is a timing chart for explaining the operation at the time of writing data in the stuff multiplex reception device 200 shown in FIG. FIG. 13 is a timing chart for explaining the operation at the time of reading data in the stuff multiplex reception device 200 shown in FIG. Below, these Figure 1
The operation of the ring type transmission system shown in FIG. 1 will be described with reference to FIGS.

It is now assumed that the terminal 8 belonging to a certain communication node 500a has data to be transmitted to the terminal 8 of another communication node. This data is input to the corresponding stuff multiplex transmission device 100 in the stuff multiplex transmission unit 10 via the branch line 7 and the terminal accommodating unit 400 together with the clock signal.

(1) Data Writing Operation in Stuff Multiplexing Transmitter 100 The input data from the terminal 8 input to the stuffing multiplex transmitter 100 is converted into m-bit parallel data by the serial / parallel converter 112, and thereafter, It is given to the transmission input distributor 113b. On the other hand, the input clock signal from the terminal 8 is 1 / m frequency-divided by the 1 / m frequency divider 111 and then given to the selection signal generation circuit 113a as a write clock signal. Selection signal generation circuit 113a
As shown in FIG. 10, each has the same period (1 /
a period obtained by dividing the output of the m divider 111 by k / m),
In addition, k / m selection signals whose phases are shifted from each other by one cycle are generated. As described above, the selection signal generation circuit 113
The k / m selection signals output from a are stored in the memory circuit 1
13c is given to each clock terminal of the D-type flip-flop belonging to the corresponding group. Further, the transmission input distributor 113b is a serial / parallel converter 112.
The m-bit parallel data input from is distributed to the D flip-flops of each group of the memory circuit 113c.

When the first selection signal of the selection signal generation circuit 113a becomes high level, as shown in FIG. 10, the D-type flip-flops F (1) to F (m) of the first group in the memory circuit 113c are turned on. The first parallel data selected and fetched from the serial / parallel converter 112 is stored and held. Next, the selection signal generation circuit 113a
When the second selection signal of the above becomes high level, the second group of D-type flip-flops F (m + 1) to F (2m) in the memory circuit 113c are selected and the next parallel data from the serial / parallel converter 112 is selected. Capture and store. Similarly, as the selection signals of the selection signal generation circuit 113a sequentially become high level, the D-type flip-flops belonging to the corresponding group are selected and the parallel data from the serial / parallel converter 112 are sequentially output. Capture and retain memory.

(2) Data read operation in the stuff multiplex transmission device 100 The output clock oscillator 114 synchronizes with the transmission clock of the trunk transmission line 6 and outputs an output clock signal having a higher frequency than the input clock signal from the terminal 8. appear. This output clock signal is output to 1 by the 1 / n frequency divider 115.
After being divided by / n, it is given to the read bit control circuit 118 as a read clock signal. The stuff & frame control circuit 117 also adjusts the memory circuit 113 according to the frame structure of data to be transmitted to the trunk transmission line 6.
The bit width of the data read from c is notified to the read bit control circuit 118. In response, the read bit control circuit 118, as shown in FIG.
From the selectors S (1) to S (1) to S (1) in the transmission output selector 113d at the timing of synchronizing the pointer value indicating the leading bit position of the data read from
Output to (n).

The length data output from the read bit control circuit 118 takes any value from 0 to n. The pointer value output from the read bit control circuit 118 is updated by adding the immediately preceding length data. For example, when the current pointer value is "1" and the length data is "n", the next pointer value is "n + 1". When the current pointer value is "n + 1" and the length data is "n-3", the next pointer value is "2n-2".

Now, assuming that the pointer value is "1" and the length data is "n", the pointer value and the length data are decoded by the selectors S (1) to S (n). As a result, the selector belonging to the range corresponding to the bit width designated by the length data from the position corresponding to the pointer value recognizes that the read data from the memory circuit 113c should be selected and output. in this case,
The selectors S (1) to S (n) recognize that the read data from the memory circuit 113c should be selected and output. That is, the selectors S (1) to S (n) respectively select the storage information of the D-type flip-flops F (1) to F (n) in the memory circuit 113c and output it to the parallel port 113e. Therefore, n-bit data is read from the memory circuit 113d.

D-type flip-flops F (1) to F (n)
When the reading from is completed, the pointer value is updated to the value "n + 1" obtained by adding the immediately preceding length data "n". At this time, if an additional bit is to be inserted into the last 2 bits of the n-bit parallel data output from the parallel port 113e, the length data is "n-
2 ”. The pointer value "n + 1" and the length data "n-2" are decoded by the selectors S (1) to S (n), and the selectors S (1) to S (n-2) are decoded.
Recognizes that the read data from the memory circuit 113c should be selected and output. That is, the selector S
(1) to S (n-2) respectively select the storage information of the D-type flip-flops F (n + 1) to F (2n-1) and output them to the parallel port 113e. At this time, the other selectors S (n-1) and S (n) do not select any stored information of the D-type flip-flops F (1) to F (k). Therefore, n-2 bits of data are read from the memory circuit 113d.

On the other hand, the additional bit generation circuit 119 generates two additional bits at a predetermined position in the frame notified by the stuff & frame control circuit 117. This additional bit is given to the parallel port 113e. As a result, the parallel port 113e outputs n-bit parallel data with the additional 2 bits inserted. Similarly, data of a predetermined bit width is sequentially read from the corresponding bit position from the memory circuit 113d in accordance with the pointer value and the length data designated by the read bit control circuit 118. According to the above, a predetermined number of additional bits are inserted and output.

(3) Stuff bit insertion operation in the stuff multiplex transmission device 100 The phase comparator 116 writes the write clock signal (output signal of the 1 / m frequency divider 111) of the buffer memory 113 and the read clock signal (1 / n amount). The output signal from the frequency divider 115) is constantly monitored, and if the difference is less than a certain value (that is, immediately before the read clock signal overtakes the write clock signal), a request to insert the stuff bit into the frame is issued. Output to the stuff & frame control circuit 117. In response to the request from the phase comparator 116, the stuff & frame control circuit 117 inserts the stuff bit and the frame position where the stuff bit should be inserted into the read bit control circuit 118 and the additional bit generation circuit 119. Notice. In response, the read bit control circuit 118 outputs the length data having a predetermined value of "n-1" or less to the transmission output selector 113d. Further, the additional bit generation circuit 119 generates a stuff insertion pulse as shown in FIG. 11 at the frame position where the stuff bit is inserted. This stuffing pulse is applied to the parallel port 113e and is inserted as 1-bit stuff bit into the data (parallel data of n-1 bits or less) read from the memory circuit 113c.

As described above, immediately before the read clock signal overtakes the write clock signal, the memory circuit 11
By inserting the stuff bit in the read data from 3c, it is possible to prevent the reading speed of the memory circuit 113c from being substantially reduced, and prevent the memory circuit 113c from becoming empty and reading erroneous data.

(4) Reset Operation in Stuff Multiplexing Transmitter 100 At the start of communication, a transmission start signal is given from the transmission path controller 300 to the position reset instruction circuit 121 of the stuff multiplex transmitter 100. In response, the position reset instruction circuit 121 causes the stuff & frame control circuit 117
A reset pulse is generated at the beginning of the frame determined from the output of 1) and output to the selection signal generation circuit 113a, the read bit control circuit 118, and the additional bit generation circuit 119. The selection signal generation circuit 113a is reset in response to this reset pulse, and restarts the generation operation of the selection signal from the next rising edge of the write clock signal from the 1 / m frequency divider 111. On the other hand, the read bit control circuit 118 resets the pointer value to the initial value in response to the reset pulse. As a result, the positional relationship between the write clock signal and the read clock signal in the buffer memory 113 is reset to the predetermined positional relationship.

Further, the read bit control circuit 118 is
To insert a position reset service code for instructing the communication partner station to execute a position reset,
The length data having a predetermined value of "n-1" or less is output to the transmission output selector 113d. On the other hand, the additional bit generation circuit 119 generates the service code “1” at the frame position previously assigned to the position reset service code. According to this service code "1"
Is supplied to the parallel port 113e, and the memory circuit 1
It is inserted into the data read from 13c.

N output from the parallel port 113e
The bit parallel data is given to the parallel / serial converter 120 and converted into serial data. This serial data is synchronized with the output clock signal output from the output clock oscillator 114, and has a higher frequency than the serial data input from the terminal 8. The serial data output from the parallel / serial converter 120 is given to the transmission path control unit 300, is multiplexed with the transmission data from the other stuff multiplex transmission device 100 included in the stuff multiplex transmission unit 10, and is multiplexed into the main line transmission line 6 Is sent to the normal system 61.

(5) Data Writing Operation in Stuff Multiplexing Reception Device 200 The data transmitted on the normal system 61 of the trunk transmission line 6 is received by the transmission line control unit 300 in the communication node of the communication partner and It is separated into a reception clock signal. The separated reception data is converted into n-bit parallel data by the serial / parallel converter 212. On the other hand, the separated reception clock signal is frequency-divided by 1 / n by the 1 / n frequency divider 211 to generate a write clock signal. The outputs of the serial / parallel converter 212 and the 1 / n frequency divider 211 are the frame synchronization circuit 21.
3 to secure the frame synchronization.

When the frame synchronization circuit 213 recognizes the head of the frame, the service code part other than the information part forming the frame is deleted. The control circuit 215 is notified. In response, the write bit control circuit 215 specifies the number of bits to be written in the memory circuit 216b for the reception input selector 216a. That is, the write bit control circuit 215
Outputs a pointer value representing the leading value of the write bit and length data representing the write bit width, and each selector S ′ (1) to
Give to S '(k).

The length data output from the write bit control circuit 215 takes any value from 0 to n. The pointer value output from the write bit control circuit 215 is updated by adding the immediately preceding length data. For example, when the current pointer value is "1" and the length data is "n", the next pointer value is "n + 1". When the current pointer value is "n + 1" and the length data is "n-3", the next pointer value is "2n-2".

Now, assuming that the pointer value is "1" and the length data is "n", the pointer value and the length data are decoded by the selectors S '(1) to S' (k). As a result, the selector belonging to the range corresponding to the bit width designated by the length data from the position corresponding to the pointer value is the serial / parallel converter 215.
It is recognized that n-bit parallel data from is to be selected and output. In this case, the selectors S '(1) to S'
(N) recognizes that n-bit parallel data from the serial / parallel converter 215 should be selected and output. That is, the selectors S ′ (1) to S ′ (n) respectively select the first bit to the nth bit of the n-bit parallel data, and the corresponding D-type flip-flop F ′.
(1) to F ′ (n). At this time, the other selectors S ′ (n + 1) to S ′ (k) select the outputs fed back from the corresponding D-type flip-flops F ′ (n + 1) to F ′ (k), and the corresponding D Type flip-flops F ′ (n + 1) to F ′ (k).

Each D-type flip-flop F '(1) to F' (k) in the memory circuit 216b has a 1 / n frequency divider 2
In synchronization with the write clock signal from 11, the outputs of the corresponding selectors S ′ (1) to S ′ (k) are stored and held. Therefore, in the above case, only the D-type flip-flops F ′ (1) to F ′ (n) store and hold the n-bit parallel data from the serial / parallel converter 212,
Other D-type flip-flops F '(n + 1) to F' (k)
The memory content of is not changed.

D-type flip-flops F '(1) to F'
When the writing to (n) is completed, the pointer value is updated to the value "n + 1" obtained by adding the immediately preceding length data "n". At this time, the serial / parallel converter 211
If, for example, the last 2 bits of the n-bit parallel data from 1 to 2 are additional bits, the length data will be "n-2". The pointer value “n + 1” and the length data “n-2” are stored in the selectors S ′ (1) to S ′ (1).
Decoded by S '(k), selector S' (n +
1) to S '(2n-1) are serial / parallel converters 2
Recognize that n-bit parallel data from 15 should be selected and output. That is, the selector S '(n + 1)
~ S '(2n-1) selects the 1st bit to the n-2th bit of the n-bit parallel data, and the corresponding D-type flip-flops F' (n + 1) to F '(2n-).
Output to 1). Therefore, the D-type flip-flop F '
The first bit to the n-2th bit of the n-bit parallel data are written in (n + 1) to F '(2n-1). At this time, the other selectors S '(1) to S' (n), S '(2
n) to S '(k) are respectively corresponding D-type flip-flops F' (1) to F '(n) and F' (2n) to F '.
The output fed back from (k) is selected and the corresponding D-type flip-flops F ′ (1) to F ′ (n), F ′ are selected.
Re-enter in (2n) to F '(k). Therefore, the D-type flip-flops F ′ (1) to F ′ (n) and F ′ (2n) to
The stored contents of F '(k) are not rewritten. As described above, the first bit to the (n−2) th bit of the n-bit parallel data, excluding the last two additional bits, are written in the memory circuit 216b. And so on
Only the information bits from which the additional bits have been removed are written in the memory circuit 216b in synchronization with the write clock signal from the 1 / n frequency divider 211.

(6) Read Clock Reproducing Operation in Stuff Multiplexing Receiver 200 In the PLL circuit 217, the above-mentioned length data is given from the write bit control circuit 215 to one input end of the phase comparator 217a, and the other input end thereof. Is VCO2
An output clock signal is given from 17c. The phase comparator 217a generates a write clock signal in which the additional bit removed portion is missing based on the length data provided from the write bit control circuit 215. Then, the phase comparator 217a detects the phase difference between the generated write clock signal and the output clock signal from the VCO 217c. The detection output of the phase comparator 217a is smoothed by the low pass filter 217b. VCO
217c generates an output clock signal having a frequency according to the output voltage of the low pass filter 217b. As a result, the write clock signal having the missing tooth portion is smoothed, and the input clock signal from the terminal 8 (see FIG. 3).
Is reproduced as an output clock signal having the same frequency as.

The output clock signal reproduced by the PLL circuit 217 as described above is used as the read clock signal in the ring counter 216d in the buffer memory 216.
Given to. Therefore, the stored data is read from the memory circuit 216b in synchronization with the read clock signal. The operation of reading data from the memory circuit 216b will be described below.

(7) Data Read Operation in Stuff Multiplexing Reception Device 200 The ring counter 216d counts the read clock signal from the PLL circuit 217 to output a multi-bit count signal as shown in FIG. The count signal corresponds to each selector S ″ of the reception output selector 216c.
The selectors S ″ (1) to S ″ (m) are provided as selection bit instruction signals to (1) to S ″ (m). Each selector S ″ (1) to S ″ (m) is input from the input port corresponding to the count value indicated by the count signal of the ring counter 216d. For example, when the count value indicated by the count signal of the ring counter 216d is “0”, the selectors S ″ (1) to S ″ are selected and output.
(M) selects and outputs the output of each of the D-type flip-flops F ′ (1) to F ′ (m) input from the first input port. In addition, the ring counter 216d
When the count value indicated by the count signal of “1” becomes “1”, each of the selectors S ″ (1) to S ″ (m) receives a D-type flip-flop F ′ input from the second input port.
Outputs of (m + 1) to F '(2m) are selected and output.
Similarly, data is sequentially read from the memory circuit 216b in m bits.

The output data read from the memory circuit 216b by the reception output selector 216c is decoded by the block code decoding unit 219 and then parallel / serial converted by the terminal accommodating unit 400 of FIG. Given. In addition, the output clock signal reproduced by the PLL circuit 217 is stored in the terminal accommodating portion 400 of FIG.
After being multiplied, it is given to the corresponding terminal 8.

(8) Reset Operation in Stuff Multiplexing Reception Device 200 The additional bit removal control circuit 214 sets the frame position of the predetermined position reset service code to the position reset circuit 2 based on the output of the frame synchronization circuit 213.
Notify 18. The position reset circuit 218 receives the serial / serial signal based on the notification from the additional bit removal control circuit 214.
The bit data at the corresponding frame position is fetched and secured from the parallel converter 212. If the position reset service code set to “1” is received, the position reset circuit 218 generates a reset pulse as shown in FIG. 13 at the start of the frame based on the output of the frame synchronization circuit 213. Then, the data is output to the write bit control circuit 215 and the ring counter 216d. In response, the write bit control circuit 215 resets the pointer value given to the reception input selector 216a to the initial value. The initial value in this case is selected such that writing to the memory circuit 216b and reading from the memory circuit 216b do not overlap with each other. On the other hand, the ring counter 216d is
The count value of the read clock signal is reset to the initial value (see FIG. 13). As a result, at the start of communication or the like, the positional relationship between the write clock signal and the read clock signal in the buffer memory 216 is quickly reset to the predetermined positional relationship, and the occurrence of burst errors can be prevented.

(9) Operation when abnormality occurs in equipment The block code decoding unit 219 causes the reception output selector 21 to operate.
When decoding the output data from 6c, only the code shown in the data section 91 or the control section 92 is detected during normal operation, but if an abnormality occurs in the stuff multiplex transmitting apparatus or the stuff multiplex receiving apparatus, block The code decoding unit 219 continuously detects the invalid unit 93. When the invalid portion 93 is continuously detected,
At the same time as being notified to the monitoring unit (not shown) of the communication node, the position reset circuit 218 has an abnormality in the positional relationship between the write clock signal and the read clock signal of the buffer memory 216 due to the abnormality. Be notified. As a result, a reset pulse is generated from the position reset circuit 218, so that it is possible to prevent a burst error when an abnormality occurs in the device.

(10) Operation When Abnormality Occurs in Trunk Line 6 As shown in FIG. 2, for example, communication nodes 500a and 500
The operation in the case where an abnormality occurs in the trunk transmission line 6 between the point b and b will be described. In this case, the communication nodes 500a and 500
The loop b has a loopback configuration in which the normal system 61 and the standby system 62 of the trunk transmission line 6 are utilized. At this time, the frame transmitted through the backup system 62 is the communication node 50.
0b is a frame generated in the internal stuff multiplex transmission device 100, and the frame is the communication node 5
00c and 500d are relayed and received by the stuff multiplex reception device 200 inside the communication node 500a. Here, the stuff multiplex reception device 200 of the communication node 500a receives the regular frame initially generated in the backup system 62, and then receives the regular frame generated by the communication node 500b. Therefore, in the stuff multiplex reception apparatus 200 that has received consecutive "1" s, the read clock signal reproduced by the PLL circuit 217 becomes temporarily unstable due to the discontinuous frame structure. However, since the received signals are all "1" in succession, the bit portion initially assigned to the position reset service code also becomes "1". As a result, when the stuff multiplex reception device 200 in the communication node 500a that receives this received data is set in the loopback configuration, the position reset circuit 218 causes the buffer memory 216 at the beginning of the frame to be subsequently received. The relationship between the write clock signal and the read clock signal is reset to a predetermined position. Therefore,
After that, it is possible to avoid the occurrence of a burst error in the stuff multiplex reception device 200, and it is possible to obtain a communication node that does not malfunction even when the operation is restarted after a transmission line failure occurs.

(Embodiment 2) FIG. 14 is a block diagram showing the configuration of a ring type transmission system using a stuff multiplex transmission apparatus and a reception apparatus according to the second embodiment of the present invention. In FIG. 14, a plurality of communication nodes 161a-16
1c is a stuff-multiplexed ring type trunk transmission line 16
Are communicatively coupled to each other by. Further, one or a plurality of terminals (personal computers or the like) 162 are connected to each of the communication nodes 161a to 161c via a branch transmission line 160.

Each of the communication nodes 161a to 161c multiplexes a plurality of synchronized low-order group signals with a demultiplexer 163 which receives the time-division-multiplexed signals and separates them into a plurality of low-order group signals. Multiplexing unit 164 for transmitting to transmission path 160
And a plurality of low-order group signal processing units 165 that process the separated low-order group signals.

The low-order group processing section 165 includes a stuff multiplex reception section 166 for receiving a stuff-multiplexed signal including a PLL 167 used for reproducing a reception clock and reproducing the clock and data, and an asynchronous data. A terminal accommodating a terminal 162 including a stuff multiplex transmission unit 168 which synchronizes with a transmission line clock and performs stuff multiplexing transmission, an operation clock source 169 independently prepared, and a PLL 171 which reproduces a clock from transmission data from the terminal. The first elastic buffer 172 in which the data received from the terminal 162 is written according to the clock reproduced by the accommodating unit 170 and the PLL 171, and is read according to the operation clock generated by the operation clock source 169.
And the second elastic buffer 173 in which the data received via the transmission path 160 is written according to the clock reproduced by the PLL 167 and is read according to the operation clock generated by the operation clock source 169.
And the outputs of the first and second elastic buffers 172 and 173 are input to the stuff multiplex transmission unit 168.
Alternatively, the switch unit 1 for allocating to the terminal accommodating unit 170
And 74. The first and second elastic buffers 172 and 173 are configured by a FIFO (first in / first out) memory or the like.

Each communication node 1 having the above configuration
61a to 161c, the stuff multiplex reception unit 166
Receives the signal separated by the demultiplexer 163. The PLL 167 regenerates the reception clock based on the received signal. The reproduced reception clock is used for writing data in the second elastic buffer 173. That is, the stuff multiplex reception unit 166
The data received in (1) is written in the second elastic buffer 173 in synchronization with the reception clock reproduced by the PLL 167. The data stored in the second elastic buffer 173 is the operation clock source 169.
Is read out in synchronization with the operation clock generated in step S1, and sent to the switch unit 174.

The terminal accommodating section 170 reproduces a clock in the PLL 171 based on the signal received from the terminal 162 via the transmission path 160. This recovered clock is the first
It is used to write data to the elastic buffer 172 of the. That is, the received data from the terminal 162 is written in the first elastic buffer 172 in synchronization with the clock reproduced by the PLL 171. The data stored in the first elastic buffer 172 is read in synchronization with the operation clock 169 generated by the operation clock source 169 and sent to the switch unit 174.

FIG. 15 shows the format of data sent via the first elastic buffer 172 or the second elastic buffer 173. As shown, a preamble field is added to the beginning of the data.

As shown in FIG. 16, the first elastic buffer 172 and the second elastic buffer 173, when writing data, start writing from the head of the buffer and finish writing to the center of the buffer. The reading starts with. Due to the speed difference between the write clock and the read clock, the read pointer moves in the “+” direction when the write clock speed is faster. When the read clock speed is faster, the read pointer moves in the "-" direction. The capacity of the elastic buffer is defined as a capacity that does not overflow, based on the data length and the speed difference between the read clock and the write clock. When the write clock is faster, the data length becomes shorter when passing through the elastic buffer, so the preamble field is reduced. on the other hand,
If the read clock is faster, the data length will be longer when passing through the elastic buffer.
Add a preamble field. By doing so, it is possible to synchronize only the timing with the operation clock while keeping the data content.

During normal operation, the output data from the second elastic buffer 173 is sent to the terminal accommodating section via the switch section 174, and the output data from the first elastic buffer 172 is sent to the stuff multiplex transmission section 16.
Sent to 8.

The stuff multiplex transmission section 168 performs synchronization by stuff multiplex based on the data synchronized with the operation clock generated by the operation clock source 169, and the multiplexing section 164
Send to. The multiplexing unit 164 multiplexes the transmitted signals and sends them to the transmission path.

The operation clock sources 169 provided in all communication nodes are selected to have substantially the same oscillation frequency. The recovered clock reproduced by the PLL 167 in the stuff multiplex reception unit 166 has the stuff jitter superimposed on the operation clock in the low order group signal processing unit 165 that uses one time slot time-division multiplexed in the upstream communication node. It becomes a clock. However, this reproduction clock is only used for writing data to the second elastic buffer 173. That is, since the subsequent processing is realized based on the operation clock from the operation clock source 169 provided inside the communication node 161,
It is possible to minimize the influence of stuff jitter.

When an abnormality occurs in the terminal 162 or the transmission path 160, the terminal accommodating section 170 detects a reception signal disconnection and notifies the switch section 174 of this. Switch part 1
74 will change its connection when it receives this signal,
The output from the first elastic buffer 172 is connected to the terminal accommodating section 170, and the output from the second elastic buffer 173 is connected to the stuff multiplex transmitting section 168. This allows the terminal 162 to be separated from the ring network.

In the stuff multiplex transmission section 168, since the stuff multiplex synchronization is performed, it is necessary to count the difference between the transmission path clock and the clock of the transmission data for each transmission path frame, but the output from the switch 174 is Whether the data is from the terminal 162 or the stuff multiplex reception unit 166, the operation clock source 169
It is synchronized with the operating clock from. Therefore, the stuff multiplex transmission unit 168 only needs to continue to monitor the difference between the operation clock from the operation clock source 169 and the transmission path clock when performing the synchronization by the stuff multiplexing, and the transmission path 160 or the terminal 162 has an abnormality. Even in the case of occurrence of, it is possible to always multiplex the synchronized data.

[0085]

According to the first aspect of the present invention, since the data writing and the data reading are performed in parallel to the storage means, the storage means consumes less power and is integrated even if the transmission speed of the transmission line is high. It can be composed of high-speed and low-speed circuit elements. As a result, it is possible to reduce the size and power consumption of the device.

According to the second aspect of the invention, the position resetting means for resetting the positional relationship between the write clock signal and the read clock signal to a predetermined positional relationship is provided. At the time of restart, the write clock signal and the read clock signal can be aligned in phase, and the occurrence of burst errors and the like can be prevented.

According to the third aspect of the invention, when the position resetting means executes the position resetting operation, the position resetting service code is inserted into the data read from the storing means at a predetermined frame position. Therefore, the communication partner station can be instructed to execute the position reset.

According to the invention of claim 4, the writing and reading of data to and from the storage means are performed in parallel, so that even if the transmission speed of the transmission path is high, the storage means consumes less power and has a high degree of integration. It can be composed of high and low speed circuit elements. As a result, it is possible to reduce the size and power consumption of the device.

According to the fifth aspect of the present invention, when the determining means determines that the position reset service code is inserted in the received data, the positional relationship between the write clock signal and the read clock signal is predetermined. Since the position is reset, the position can be reset internally in response to the position reset operation in the stuff multiplex transmission device at the transmission destination.

According to the sixth aspect of the present invention, when the block code decoding section continuously receives invalid codes, the position resetting means determines the positional relationship between the write clock signal and the read clock signal by a predetermined positional relationship. Since it is reset to, it is possible to promptly perform the position reset when the device abnormality occurs.

According to the seventh aspect of the present invention, when an abnormality occurs in the transmission line and an emergency transmission line is formed by the normal system and the standby system, the stuff multiplex reception device is looped back in the downstream communication node. Receives a code preset in the standby system as a code for position resetting, so that the internal position resetting means automatically resets the positional relationship between the write clock signal and the read clock signal to a predetermined positional relationship. It Therefore, even when an abnormality occurs in the transmission path, the write clock signal and the read clock signal of the storage means always operate with a constant interval, and stable operation can be performed without causing a burst error in the reproduced data. It will be possible.

According to the invention of claim 8, the recovered clock from the transmission line on which the stuff jitter is superimposed is used only for writing the data in the second elastic buffer, so that a plurality of nodes are connected. It is possible to minimize the effect of stuff jitter even on a network. Further, since the data received from the terminal is handled in synchronization with the operation clock inside the communication node via the first elastic buffer, for example, when an abnormality occurs in the terminal or a branch line, its output destination is output. Even if is switched, it is possible to perform processing that does not affect the synchronization processing in the stuff multiplex transmission device.

[0093]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a ring type transmission system using a stuff multiplex transmission apparatus and a reception apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a loopback configuration at the time of a transmission line failure in the transmission system of FIG.

3 is a block diagram showing a configuration of one stuff multiplex transmission device included in a stuff multiplex transmission unit 10 in FIG.

4 is a block diagram showing in more detail the configuration of the write side in the buffer memory 113 of FIG.

5 is a block diagram showing in more detail the configuration of the read side in the buffer memory 113 of FIG.

6 is a block diagram showing a configuration of one stuff multiplex reception device included in a stuff multiplex reception unit 20 in FIG.

7 is a block diagram showing in more detail the configuration of the write side in the buffer memory 216 of FIG.

8 is a block diagram showing in more detail the configuration of the read side in the buffer memory 216 of FIG.

FIG. 9 is a diagram showing the contents of a 4B5B block code.

10 is a timing chart for explaining an operation at the time of writing data in the stuff multiplex transmission device 100 shown in FIG.

11 is a timing chart for explaining an operation at the time of reading data in the stuff multiplex transmission device 100 shown in FIG.

12 is a timing chart for explaining an operation at the time of writing data in the stuff multiplex reception device 200 shown in FIG.

13 is a timing chart for explaining an operation at the time of reading data in the stuff multiplex reception device 200 shown in FIG.

FIG. 14 is a block diagram showing a configuration of a ring type transmission system using a stuff multiplex transmission apparatus and a reception apparatus according to a second embodiment of the present invention.

15 is a first elastic buffer 172 or a second elastic buffer 173 in FIG.
It is a figure which shows the format of the data transmitted via.

16 is a diagram for explaining an operating state of the elastic buffer in FIG.

FIG. 17 is a block diagram showing a configuration of a conventional stuff multiplex transmission device.

FIG. 18 is a block diagram showing a configuration of a conventional stuff multiplex reception device.

[Explanation of symbols]

 10 ... Staff multiplex transmitter 20 ... Staff multiplex receiver 6 ... Trunk transmission line 61 ... Normal system 62 ... Standby system 7 ... Branch line transmission line 8 ... Terminal 300 ... Transmission line control unit 400 ... Terminal accommodating unit 500a to 500c ... Communication node 91 ... Data part 92 ... Control part 93 ... Invalid part 111 ... 1 / m frequency divider 112 ... Serial / parallel converter 113 ... Buffer memory 113a ... Selection signal generating circuit 113b ... Transmission input distributor 113c ... Memory circuit 113d ... Transmission Output selector 113e ... Parallel port 114 ... Output clock oscillator 115 ... 1 / n frequency divider 116 ... Phase comparator 117 ... Stuff & frame control circuit 118 ... Read bit control circuit 119 ... Additional bit generation circuit 120 ... Parallel / serial converter 121 ... Position reset instruction circuit 211 ... 1 / n frequency divider 21 Parallel / serial converter 213 Frame synchronization circuit 214 Additional bit removal circuit 215 Write bit control circuit 216 Buffer memory 216a Reception input selector 216b Memory circuit 216c Reception output selector 216d Ring counter 217 PLL circuit 217a ... phase comparator 217b ... low-pass filter 217c ... VCO 218 ... position reset circuit 16 ... trunk transmission line 160 ... branch transmission lines 161a to 161c ... communication node 162 ... terminal 163 ... demultiplexing unit 164 ... multiplex transmission unit 165 ... low Next group signal processing unit 166 ... Stuff multiplex reception unit 167, 171 ... PLL 168 ... Stuff multiplex transmission unit 169 ... Operating clock source 170 ... Terminal accommodating unit 172 ... First elastic buffer 173 ... Second elastic buffer § 174 ... switch unit

Claims (8)

[Claims] 1. A stuff multiplex transmission device for stuff-multiplexing input data serially input in synchronization with an input clock signal, and serially outputting frame by frame on a transmission line that operates asynchronously with the input clock signal. 1 / m frequency dividing means for dividing the input clock signal by 1 / m to generate a write clock signal, serial / parallel converting means for converting the input data into parallel data having an m-bit width, transmission clock on the transmission path Output clock signal generating means for generating an output clock signal having a frequency higher than that of the input clock signal in synchronization with the signal; 1 / n minute for dividing the output clock signal by 1 / n to generate a read clock signal Peripheral means, storage means for temporarily storing and holding at least k-bit (k> n, m) data, the write clock In synchronization with the lock signal, the serial /
A write control means for writing output data of the parallel conversion means to the storage means in order of m bits, and a bit width (0 to n bit width) corresponding to a frame structure from the storage means in synchronization with the read clock signal.
Read-out control means for reading out data, phase-difference detection means for detecting a phase difference between the write-clock signal and the read-clock signal, at a predetermined frame position with respect to the data read out from the storage means. An additional bit inserting means for inserting an additional bit and outputting parallel data having an n-bit width when the phase difference detected by the phase difference detecting means becomes equal to or less than a predetermined value, and output from the additional bit inserting means A stuff multiplex transmission device comprising parallel / serial conversion means for converting parallel data having an n-bit width to serial data. 2. The stuff multiplex transmission device according to claim 1, further comprising position reset means for resetting a positional relationship between the write clock signal and the read clock signal to a predetermined positional relationship. 3. The additional bit inserting means, when the position resetting means performs a position resetting operation, adds a position resetting service code to a data read from the storing means at a predetermined frame position. The stuff multiplex transmission device according to claim 2, wherein the stuff multiplex transmission device is inserted. 4. A stuff multiplex receiving device for receiving stuff-multiplexed data and clock signals from a transmission line and converting these received data and received clock signals into original data and original clock signals before stuff-multiplexing. A 1 / n frequency dividing unit that divides the received clock signal by 1 / n to generate a write clock signal; a serial / parallel conversion unit that converts the received data into parallel data having an n-bit width; Determining means for determining the insertion position of the additional bit in, read clock generating means for generating a read clock signal based on the determination result of the determining means, and temporarily storing and holding at least k bits (k> n, m) of data Storage means for outputting the output of the serial / parallel conversion means based on the determination result of the determination means The additional bit is removed from the data, and the data from which the additional bit is removed is written to the storage means in synchronization with the write clock signal, and the write control means is synchronized with the read clock signal. A stuff multiplex reception device comprising a read control means for sequentially reading parallel data having a bit width. 5. The positional relationship between the write clock signal and the read clock signal is set to a predetermined positional relationship when the determination means determines that a position reset service code is inserted in the received data. The stuff multiplex reception device according to claim 4, further comprising position reset means for resetting. 6. A block code decoding unit that restores the parallel data read by the read control unit to original data, wherein the m-bit-width parallel data forms a block code composed of a data code, a control code, and an invalid code. Further, the block code decoding unit further includes position reset means for resetting a positional relationship between the write clock signal and the read clock signal to a predetermined positional relationship when the invalid code is continuously received. The stuff multiplex reception apparatus according to claim 5, comprising. 7. A data transmission system in which a plurality of communication nodes, each of which is connected to a terminal, are communicatively coupled to each other through a ring type transmission line, each communication node being an input clock signal from the terminal. A stuff-multiplexing device that stuff-multiplexes input data serially input in synchronization with each other and serially outputs each frame on the transmission line that operates asynchronously with the input clock signal; and stuff-multiplexed data from the transmission line. And a stuff multiplex receiving device for receiving the clock signal and converting the received data and the received clock signal into the original data before the stuff multiplexing and the original clock signal, the transmission line being used during normal operation. The normal system and the transmission direction of the normal system are opposite to each other, and the The stuff multiplex reception device divides the reception clock signal by 1 / n, and a standby system that cooperates with the normal system to form an emergency transmission line looped back before the position where the abnormality occurs. 1 / n frequency dividing means for generating a write clock signal, serial / parallel converting means for converting the received data into parallel data having an n-bit width, and determining means for determining an insertion position of an additional bit in the received data, A read clock generation unit that generates a read clock signal based on the determination result of the determination unit, a storage unit that temporarily stores and holds at least k-bit (k> n, m) data, and a determination result of the determination unit Based on the above, the additional bits are removed from the output data of the serial / parallel conversion means, and A write control unit that writes to the storage unit in synchronization with a write clock signal; a read control unit that sequentially reads parallel data of m-bit width from the storage unit in synchronization with the read clock signal; and the determination unit. Position reset means for resetting the positional relationship between the write clock signal and the read clock signal to a predetermined positional relationship when it is determined that the position reset service code is inserted in the received data. In the standby system, all the transmission line codes are set in advance with a code having the same logic as the position reset service code, whereby the normal system and the standby system are set when an abnormality occurs in the transmission line. When the emergency transmission path is formed in cooperation with each other, the loopback is performed in the downstream communication node. The tuff multiplex receiving device receives the code set in the standby system as the position reset code so that the internal position resetting means determines a positional relationship between the write clock signal and the read clock signal. Characterized by resetting to the positional relationship of
Data transmission system. 8. A data transmission system in which a plurality of communication nodes, each of which is connected to a terminal, are communicatively coupled to each other through a ring type transmission line, wherein each of the communication nodes is stuff-multiplexed from the transmission line. Stuff multiplex reception device for receiving the data and the clock signal, and converting them to the original data and the original clock signal before the stuff multiplex; Storing input data input in synchronization with an input clock signal from the terminal in synchronization with the input clock signal,
First to read stored data in synchronization with the operation clock
Elastic buffer, and a second elastic buffer for storing the original data output from the stuff multiplex reception device in synchronization with the original clock signal and reading the stored data in synchronization with the operation clock. A stuff multiplexing transmitter that stuff-multiplexes the data read from the first or second elastic buffer on a frame-by-frame basis and serially outputs the data on the transmission path that operates asynchronously with the operation clock. Transmission system.