JPH0738543A - Elastic memory circuit - Google Patents

Abstract

PURPOSE:To provide an elastic memory circuit which can be immediately operated in a stable operating state at the time of recovery to a normal operating state and can suppress the increase of output jitter at a path terminating point while decreasing useless stuff sending operations. CONSTITUTION:A write address counter 2 generates a write address S7. On the other hand, a read address counter 3 generates a read address S8. A memory circuit 1 is provided for storing write data S1, LOP detect signal S2 and P-AIS detect signal or the like, stores data in a storage area designated by the write address S7 and outputs data in a storage area designated by the read address S8. In a warning state (in the state of inputting a P-AIS transmission control signal S6), the write address counter 2 and the read address counter 3 preset the write address S7 and the read address S8 at respectively different prescribed values.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, a Synchronous Digital Hierar (SDH).
The present invention relates to an elastic memory circuit applied to a pointer replacement circuit of a multi-terminal device or a cross-connect device conforming to chy).

[0002]

2. Description of the Related Art An elastic memory circuit is used in a pointer replacement circuit of a multi-terminal station device or a cross-connect device. The elastic memory circuit has a write address counter and a read address counter, respectively, and can write and read independently. However, if writing and reading were performed completely independently, data loss and double reading would occur, so control is performed so that the phase relationship between the write address and read address is in a predetermined state. is doing.

However, input interruption, loss of frame synchronization,
Loss Of Pointer (LOP), PathAlarm Indication S
When an alarm state such as ignal (P-AIS) occurs, the write address counter and the read address counter enter the free run state. Therefore, when the alarm state returns to the normal operation state, the phase relationship between the write address and the read address is indefinite.

In the pointer replacement circuit, when the phase relationship between the write address and the read address is out of the predetermined state, a positive stuff or a negative stuff sending operation is executed to bring the phase relationship into the predetermined state. Control to become.

Here, in SDH, due to the CCITT regulations, the staff sending operation can be executed only once in four frames. Therefore, it takes [4 frames] × [125 μs] × [required number of stuff sending operations] until the phase relationship between the write address and the read address returns to the predetermined state after returning from the alarm state to the normal operation state. I need time. Further, when the stuffing operation is executed, there is a problem that the output jitter at the path termination point increases.

[0006]

As described above, in the conventional elastic memory circuit, since the phase relationship between writing and reading becomes undefined in an abnormal state, writing and reading are performed when returning to the normal operation state. There is a possibility that the phase difference between and is not in the prescribed state, and it is necessary to control the phase difference between writing and reading to the prescribed state after returning to the normal operating state. There was a problem that it took time to reach a stable operating state. Further, when the stuff sending operation is performed to control the phase difference between writing and reading to a predetermined state, there is a problem that output jitter at the path termination point increases.

The present invention has been made in consideration of such circumstances, and an object thereof is to enable immediate operation in a stable operation state when returning to a normal operation state, Another object of the present invention is to provide an elastic memory circuit that can reduce wasteful stuffing operation and suppress an increase in output jitter at the path termination point.

[0008]

In order to achieve the above object, the present invention provides a memory means for storing data, such as a memory circuit, and a writing position of data to the memory means in a predetermined order. For example, write control means such as a write address counter that sequentially changes, and read control means such as a read address counter that sequentially changes the read position of data from the memory means in the predetermined order, for example, input disconnection and frame synchronization loss. , LOP
And when a predetermined abnormality such as P-AIS occurs,
The write control means and the read control means are preset so that the phase difference between the data writing position and the data reading position becomes a predetermined state when the normal state is restored later.

[0009]

By taking such means, the data is written in the memory means in accordance with the write position which is sequentially changed by the write control means in a predetermined order. Further, the data stored in the memory means is read from the memory means in accordance with the read position which is sequentially changed by the read control means in a predetermined order. When a predetermined abnormality occurs, the write control means and the read control means are preset so that the phase difference between the data writing position and the data reading position becomes a predetermined state when the normal state is restored. It

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an elastic memory circuit according to this embodiment. As shown in this figure, the elastic memory circuit of this embodiment comprises a memory circuit 1, a write address counter 2, a read address counter 3 and an address comparison circuit 4.

The elastic memory circuit is externally provided with write data S1, LOP detection signal S2, P-AI.
An S detection signal S3, a write clock S4, a read clock S5 and a P-AIS transmission control signal S6 are given. Of these signals, the write data S1, the LOP detection signal S2, the P-AIS detection signal S3, and the write clock S4 are input to the memory circuit 1. The write clock S4 and the P-AIS transmission control signal S6 are input to the write address counter 2, and the read clock S5 and the P-AIS transmission control signal S6 are input to the read address counter 3.

The write address counter 2 generates a write address S7. The write address counter 2 changes the value of the write address S7 in synchronization with the write clock S4. On the other hand, the read address counter 3 generates the read address S8. Read address counter 3
Is read address S8 in synchronization with read clock S5.
Change the value of. The write address counter 2 and the read address counter 3 have a function of presetting the value of the write address S7 and the value of the read address S8 to different predetermined values based on the state of the P-AIS transmission control signal S6.

The memory circuit 1 includes write data S1 and LO.
The P detection signal S2 and the P-AIS detection signal S3 are written in the storage area designated by the write address S7.
The contents of the storage area designated by the read address S8 are the read data S9, the LOP detection signal S10, and the P
-It is output to the outside as the AIS detection signal S11.

The address comparison circuit 4 has a write address S.
The value of 7 and the value of the read address S8 are compared, and when the phase difference is out of the predetermined range, the positive stuff sending request signal S12 or the negative stuff sending request signal S13 is generated,
Output to the outside.

FIG. 2 is a block diagram showing a detailed configuration of the write address counter 2 and the read address counter 3. Since the write address counter 2 and the read address counter 3 have the same configuration, the drawing is common, and the reference numerals are different from each other. As shown in this figure, the write address counter 2 includes the counter circuit 5 and the preset value. It comprises a setting circuit 7. The read address counter 3 is composed of a counter circuit 6 and a preset value setting circuit 8.

In the counter circuit 5 of the write address counter 2, the write clock S4 is input to the clock input terminal and the P-AIS transmission control signal S is input to the preset signal input terminal.
6 is input respectively. And at the data input terminal,
The preset value S generated by the preset value setting circuit 7
14 has been entered. The preset value setting circuit 7 generates a preset predetermined value as the preset value S14.

In the counter circuit 6 of the read address counter 3, the read clock S5 is provided at the clock input terminal and the P-AIS transmission control signal S is provided at the preset signal input terminal.
6 is input respectively. And at the data input terminal,
The preset value S generated by the preset value setting circuit 8
15 has been entered. The preset value setting circuit 8 generates a preset value S15 which is different from the preset value S14 and which is set in advance.

FIG. 3 is a block diagram showing the configuration of a pointer replacement circuit configured by applying the elastic memory circuit configured as described above. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the figure, reference numeral 10 is an elastic memory circuit having the configuration shown in FIG. The pointer replacement circuit is the elastic memory circuit 10
The input disconnection detection circuit 11 and the frame synchronization circuit 1 are provided around the
2, reception frame counter 13, pointer processing circuit 1
4, write clock generation circuit 15, P-AIS transmission control circuit 16, pointer generation circuit 17, read clock generation circuit 18, transmission frame counter 19, and multiplexing circuit 2.
It is composed of 0s.

The input disconnection detection circuit 11 uses the write data S1.
Of the received data S1-1 is monitored, and when the input is disconnected, the input disconnection detection signal S20 is output.
The input disconnection detection signal S20 is supplied to the frame synchronization circuit 12,
It is input to the pointer reception processing unit 14 and the P-AIS transmission control circuit 16.

The frame synchronizing circuit 12 receives the received data S1.
The frame synchronization pattern is detected from within -1, and the frame synchronization pattern detection signal S21 is output at the time of detection. Further, the frame synchronization circuit 12 monitors whether or not the frame synchronization pattern is detected at the timing of the frame pulse S22 output from the reception frame counter 13, and the frame synchronization pattern is detected at the timing of the frame pulse S22. If not, the out-of-frame detection signal S23 is output. The frame synchronization pattern detection signal S21 is input to the reception frame counter 13. The out-of-frame detection signal S23 is sent to the pointer reception processing circuit 14 and the P-AIS.
It is input to the sending control circuit 16.

The reception frame counter 13 performs bit counting based on the frame synchronization pattern detection signal S21,
Frame pulse S22 and received frame address S2
5 is generated. The reception frame address S25 is used for the pointer reception processing circuit 14 and the write clock generation circuit 15.
Entered in.

The pointer reception processing circuit 14 separates the reception pointer from the reception data S1-1 based on the reception frame address S25, detects the reception pointer value, and Loss.
Of Pointer (LOP) detection, Path Alarm Indication Si
Perform gnal (P-AIS) detection, positive stuff detection, and negative stuff detection, respectively. Then, the pointer reception processing circuit 14 outputs the reception pointer value as the reception pointer value / reception frame phase signal S1-2. Also LOP or P
When -AIS is detected, the LOP detection signal S2 or the P-AIS detection signal S3 is output. Further, when positive stuff or negative stuff is detected, positive stuff detection signal S26 or negative stuff detection signal S27.
Are output respectively. The reception pointer value / reception frame phase signal S output from the pointer reception processing circuit 14
1-2, the LOP detection signal S2 and the P-AIS detection signal S3 are input to the elastic memory 10. Further, the positive stuff detection signal S26 and the negative stuff detection signal S
27 is input to the write clock generation circuit 15. The reception pointer value / reception frame phase signal S1-2 is a part of the write data S1. That is,
The reception data S1-1 and the reception pointer value / reception frame phase signal S1-2 form the write data S1.

The write clock generation circuit 15 is based on the received frame address S25, the positive stuff detection signal S26 and the negative stuff detection signal S27, and receives the received data S1-1 input to the elastic memory circuit 10 during the payload portion. Only the write clock S4 is output. The write clock S4 is input to the elastic memory circuit 10.

The P-AIS transmission control circuit 16 has an input disconnection detection signal S20, a frame desynchronization detection signal S23, and L.
The OP detection signal S10 and the P-AIS detection signal S11 are monitored, and P-
The AIS transmission control signal S6 is output. The P-AIS transmission control signal S6 is input to the elastic memory circuit 10, the pointer generation circuit 17, and the multiplexing circuit 20.

The pointer generation circuit 17 receives the reception pointer value / reception frame phase signal S9-2 and the transmission frame address S28 output from the transmission frame counter 19.
The send pointer value is calculated based on
Output as 9. Further, the pointer generation circuit 17, when the stuff sending request is made by the positive stuff sending request signal S12 or the negative stuff sending request signal S13,
Only when the stuff sending operation is not executed within the last three frames, the positive stuff sending control signal S30 or the negative stuff sending control signal S31 is output. The positive stuff sending control signal S30 and the negative stuff sending control signal S31 are input to the read clock generation circuit 18 and the multiplexing circuit 20. The sending pointer S29 is input to the multiplexing circuit 20.

The read clock generation circuit 18 outputs the read clock S5 based on the transmission frame address S28, the positive stuff sending control signal S30 and the negative stuff sending control signal S31 only during the period for outputting the payload portion. The read clock S5 is input to the elastic memory circuit 10.

The transmission frame counter 19 bit-counts according to a transmission frame pulse S32 and a transmission clock S33 given from the outside to generate a transmission frame address S28.

The multiplexing circuit 20 multiplexes the output pointer S29 on the output data S9-1 and then outputs it as the transmission data S34. When the P-AIS transmission control signal S6 is given, the multiplexing circuit 20 transmits the transmission data S3.
Fix 4 to all "1".

Next, the operation of the pointer replacement circuit configured as above will be described. First, the pointer replacement circuit of this embodiment is based on SDH, and the received data S
1-1 is framed according to the STM-0 frame having the frame configuration shown in FIG.

Now, the input is cut off, the frame synchronization is lost, and the LOP
When neither the P-AIS nor the P-AIS is in a normal operation state, the input disconnection detection circuit 11, the frame synchronization circuit 12, and the pointer reception processing circuit 14 detect the input disconnection detection signal S20, the out-of-frame detection signal S23, and LO.
The P detection signal S10 and the P-AIS detection signal S11 are not output. Therefore, the P-AIS transmission control circuit 16 does not output the P-AIS transmission control signal S6.

In this state, the frame synchronization circuit 1
2 and the reception frame counter 13 generate the reception frame address S25 while maintaining frame synchronization.

The pointer reception processing circuit 14 separates the reception pointer (H1 and H2 bytes in FIG. 3) from the reception data S1-1 based on the reception frame address S25, and detects the reception pointer value. The detected reception pointer value is output as the reception pointer value / reception frame phase signal S1-2. The pointer reception processing circuit 14 performs positive stuff detection and negative stuff detection based on the received pointer, and outputs the result as a positive stuff detection signal S26 or a negative stuff detection signal S27.

In the write clock generation circuit 15, a period during which the received data S1-1 input to the elastic memory circuit 10 is the payload portion based on the received frame address S25, the positive stuff detection signal S26 and the negative stuff detection signal S27. The write clock S4 is output only to.

Now, in the elastic memory circuit 10,
Write address counter 2 according to write clock S4
Sequentially changes the write address S7. Thus, the write data S1 (reception data S1-1 and reception pointer value / reception frame phase signal S1-2) input to the elastic memory circuit 10 is sequentially stored in the storage area of the memory circuit 1.

On the other hand, on the read side, the read address counter 3 sequentially changes the read address according to the read clock S5 output from the read clock generation circuit 18. Thus, the data stored in the storage area of the memory circuit 1 are sequentially read and output.

The write address S7 and the read address S8 are compared by the address comparison circuit 4, and the following control is performed so that the relative phase relationship between them is within a predetermined area.

FIG. 5 is a model diagram of the storage area of the memory circuit 1 showing the phase relationship between the write address S7 and the read address S8. As shown in this figure, the memory circuit 1
Has a storage area of 0 to m. In this case, the write address counter 2 and the read address counter 3 are
Specifically, it is a binary counter that can rotate from 0 to m, respectively.

In FIG. 5, the write address S7 = "0",
The signal input / output in the case of the read address S8 = “j” is illustrated. After that, the write address S7 is 1, 2, 3, ...
Is sequentially incremented, and when it reaches m, it returns to 0 again. Similarly, the read address S8 is j + 1, j +.
The number is sequentially incremented to 2, and when it reaches m, it returns to 0 next time. Repeat the above operation to
Performs first-out elastic memory operation.

In this case, in order to maximize the phase difference between the write address S7 and the read address S8, the read address S8 may be shifted by m / 2 from the write address S7. That is, the value "j" of the read address S8 when the write address S7 is "0" may be set to [m / 2]. Then, with a slight margin before and after the "j", i + 1 or more,
The region of k-1 or less is defined as the steady operation region. A region of i or less where the phase difference is smaller than the steady operation region is a negative stuffing operation region, and a region of k or more where the phase difference is large is a positive stuffing operation region.

The address comparison circuit 4 uses the write address S
If the phase difference of the read address with respect to 7 is in the steady operation area, neither the positive stuffing request signal S12 nor the negative stuffing request signal S13 is output. Therefore, the staff sending operation is not performed. However, when the phase difference of the read address with respect to the write address S7 deviates from the normal operation area, the address comparison circuit 4 determines whether the phase difference is the positive stuff sending operation area or the negative stuff sending operation area. Either the sending request signal S12 or the negative stuff sending request signal S13 is output.

The positive stuff sending request signal S12 or the negative stuff sending request signal S13 is sent to the pointer generating circuit 17.
Entered in. Then, the pointer generation circuit 17 depends on whether the input is the positive stuff transmission request signal S12 or the negative stuff transmission request signal S13 only when the stuff transmission operation is not executed within the last three frames. Then, either the positive stuffing control signal S30 or the negative stuffing control signal S31 is output.
Then, the read clock generation circuit 18 adjusts the read clock S5 based on the positive stuff sending control signal S30 or the negative stuff sending control signal S31, whereby the positive stuff or negative stuff sending operation is performed. Thus, the phase difference between the read address and the write address S7 is controlled so as to return to the steady operation region.

In the pointer generation circuit 17, the reception pointer value / reception frame phase signal S9-2 output from the elastic memory circuit 10 and the transmission frame address S28 output from the transmission frame counter 19.
The sending pointer value is calculated based on
It is output as 29. And this sending pointer S29
Is multiplexed with the output data S9-1 by the multiplexing circuit 20, and the replacement of the pointer is completed.

By the way, input interruption, loss of frame synchronization,
When either LOP or P-AIS is generated and detected by any of the input disconnection detection circuit 11, the frame synchronization circuit 12, and the pointer reception processing circuit 14, the input disconnection detection signal S20 and the frame synchronization loss detection signal S23. ,
LOP detection signal S10 and P-AIS detection signal S11
Is input to the P-AIS transmission control circuit 16.

Then, the P-AIS transmission control circuit 16
Outputs the P-AIS transmission control signal S6 in accordance with the alarm transfer diagram shown in FIG. In response to this, the multiplexing circuit 20 fixes the output at all “1”.

The P-AIS transmission control signal S6 output by the P-AIS transmission control circuit 16 is input to the write address counter 2 and the read address counter 3 of the elastic memory circuit 10. Further, in the write address counter 2 and the read address counter 3, the P-AIS transmission control signal S6 outputs the counter circuits 5, 6
Is input to the preset signal input terminal of. Thus, P
By outputting the P-AIS transmission control signal S6 from the -AIS transmission control circuit 16, the counter circuit 5 of the write address counter 2 and the counter circuit 6 of the read address counter 3 are preset.

By the way, for example, "0" is set in the preset value setting circuit 7 of the write address counter 2. Therefore, the counter circuit 5 of the write address counter 2 is preset to "0". Further, for example, “j” is set in the preset value setting circuit 8 of the read address counter 3. Therefore, the counter circuit 6 of the read address counter 3 is preset to "j".

If the alarm state continues, P-AIS
The P-AIS transmission control signal S6 continues to be output from the transmission control circuit 16. In this state, the preset signal is continuously input to the counter circuit 5 of the write address counter 2 and the counter circuit 6 of the read address counter 3, so that the respective count values are maintained at "0" and "j". .

When the abnormality is eliminated from this state and the normal operation state is restored, P from the P-AIS transmission control circuit 16 is returned.
-The output of the AIS transmission control signal S6 is stopped. As a result, the preset state of the counter circuit 5 of the write address counter 2 and the counter circuit 6 of the read address counter 3 is released, and the count operation is started.
At this time, the counter circuit 5 of the write address counter 2
Is 0, and the count value of the counter circuit 6 of the read address counter 3 is "j".
Therefore, the relative phase relationship between the write address S7 and the read address S8 immediately after returning to the normal operation state is an ideal state as shown in FIG.

Thus, according to this embodiment, at the time of returning from the alarm state to the normal operation state, the read address S8 exists in the steady operation area with respect to the write address S7. Therefore, it is possible to immediately and stably operate in a steady operation state. Further, the stuff pulse sending operation for controlling to the steady operation region is not performed, and the output jitter at the downstream path termination point does not increase.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the application of the elastic memory circuit according to the present invention is not limited to the pointer replacement circuit compliant with SDH.

Further, in the above embodiment, the preset value is set so that the phase difference between the write address and the read address becomes maximum, but the phase difference between the write address and the read address is a value within the steady operation region. It can be optional. In addition, various modifications can be made without departing from the scope of the present invention.

[0053]

According to the present invention, a memory means such as a memory circuit for storing data and a write address counter for sequentially changing the write position of data to this memory means in a predetermined order. Control means and read control means such as a read address counter for sequentially changing the read position of data from the memory means in the predetermined order, and a predetermined input interruption, loss of frame synchronization, LOP and P-AIS. When an abnormality occurs, the write control means and the read control means are preset so that the phase difference between the data write position and the data read position will be a predetermined state when the normal state is restored later. , It is possible to operate in a stable operating state immediately when returning to the normal operating state, and Reduce staff delivery operation the elastic memory circuit capable of suppressing the increase of the output jitter in the path terminating point.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an elastic memory circuit according to this embodiment.

FIG. 2 is a block diagram showing a detailed configuration of a write address counter 2 and a read address counter 3.

FIG. 3 is a block diagram showing a configuration of a pointer replacement circuit configured by applying the elastic memory circuit shown in FIG.

FIG. 4 is a frame structure of received data S1-1 (STM-
The figure which shows typically the frame structure of 0 frame).

FIG. 5 is a diagram showing a phase relationship between a write address S7 and a read address S8 in a model diagram of a storage area of the memory circuit 1.

FIG. 6 is an alarm transfer diagram showing an input / output relationship in a P-AIS transmission control circuit 16.

[Explanation of symbols]

 1 ... Memory circuit 2 ... Write address counter 3 ... Read address counter 4 ... Address comparison circuit 5,6 ... Counter circuit 7,8 ... Preset value setting circuit 10 ... Elastic memory circuit

Claims (1)

[Claims] 1. A memory means for storing data, a write control means for sequentially changing a write position of data to the memory means in a predetermined order, and a read position of data from the memory means to the predetermined position. The read control means for sequentially changing in sequence, and the write control means so that, when a predetermined abnormality occurs, the phase difference between the data write position and the read position becomes a predetermined state when the normal state is restored later. An elastic memory circuit comprising: and a preset means for presetting the read control means.