JP2003273484A - Connection structure - Google Patents
Connection structureInfo
- Publication number
- JP2003273484A JP2003273484A JP2002069287A JP2002069287A JP2003273484A JP 2003273484 A JP2003273484 A JP 2003273484A JP 2002069287 A JP2002069287 A JP 2002069287A JP 2002069287 A JP2002069287 A JP 2002069287A JP 2003273484 A JP2003273484 A JP 2003273484A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- layer
- insulating base
- base material
- connection structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は電子機器に使用され
る回路基板等に適用して好適な接続構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection structure suitable for application to a circuit board used in electronic equipment.
【０００２】[0002]
【従来の技術】従来の接続構造について説明すると、図
２は従来の接続構造を示す要部の拡大断面図で、ガラス
入り基板等の回路基板からなる絶縁基材５１は、平板状
をなし、この表面には、複数の金属層５２からなる半田
付け用のランド部Ｒ２が設けられている。2. Description of the Related Art A conventional connection structure will be described. FIG. 2 is an enlarged cross-sectional view of an essential part showing a conventional connection structure. An insulating base material 51 made of a circuit board such as a glass-filled board has a flat plate shape. On this surface, a soldering land portion R2 including a plurality of metal layers 52 is provided.
【０００３】そして、この金属層５２は、絶縁基材５１
上に形成され、表面が平滑なＣｕ層の第１下地金属層５
３、及びこの第１下地金属層５３上に形成され、表面が
平滑なＮｉ層の第２下地金属層５４と、この第２下地金
属層５４上に形成され、表面が平滑なＡｕ層からなる表
面金属層５５とで構成されている。The metal layer 52 is the insulating base material 51.
First underlying metal layer 5 formed on the upper surface of the Cu layer having a smooth surface
3 and a second underlayer metal layer 54 formed on the first underlayer metal layer 53 and having a smooth surface as an Ni layer, and an Au layer formed on the second underlayer metal layer 54 and having a smooth surface. And a surface metal layer 55.
【０００４】また、表面金属層５５の上面には、絶縁材
からなるレジスト層５６が形成されて、このレジスト層
５６によって、ランド部Ｒ２の領域が形成されている。
そして、Ｃｕ層からなる第１下地金属層５３は、ここで
は図示しないが、配線パターンとして絶縁基体５１上に
形成されたものとなっている。A resist layer 56 made of an insulating material is formed on the upper surface of the surface metal layer 55, and the resist layer 56 forms a region of a land portion R2.
Although not shown here, the first base metal layer 53 made of a Cu layer is formed on the insulating base 51 as a wiring pattern.
【０００５】ＩＣ部品やチップ抵抗等の電気部品、或い
は回路基板等からなる被接続部材５７が絶縁基材５１上
に載置され、半田５８によってランド部Ｒ２に接続され
て、接続構造が構成されている。A connected member 57 made of an IC component, an electric component such as a chip resistor, or a circuit board is placed on the insulating base material 51 and connected to the land portion R2 by the solder 58 to form a connection structure. ing.
【０００６】次に、このような構成を有する絶縁基材５
１の製造方法を説明すると、先ず、Ｃｕ層からなる第１
下地金属層５３によって所望の配線パターンが施された
絶縁基材５１を用意する。Next, the insulating base material 5 having such a structure
The manufacturing method of No. 1 will be described.
An insulating base material 51 provided with a desired wiring pattern by the base metal layer 53 is prepared.
【０００７】次に、半田付け用のランド部Ｒ２となる部
分の第１下地金属層５３上に、メッキによってＮｉ層か
らなる第２下地金属層５４を形成する。この時、平滑な
表面を有する第１下地金属層５３上に形成された第２下
地金属層５４の表面は、平滑な状態で形成される。Next, a second base metal layer 54 made of a Ni layer is formed by plating on the first base metal layer 53 in the portion which will become the land portion R2 for soldering. At this time, the surface of the second base metal layer 54 formed on the first base metal layer 53 having a smooth surface is formed in a smooth state.
【０００８】次に、第２下地金属層５４上に、メッキに
よってＡｕ層からなる表面金属層５５を形成する。この
時、平滑な表面を有する第２下地金属層５４上に形成さ
れた表面金属層５５の表面は、平滑な状態で形成され
る。このようにして絶縁基材５１の製造が行われる。Next, a surface metal layer 55 made of an Au layer is formed on the second base metal layer 54 by plating. At this time, the surface of the surface metal layer 55 formed on the second base metal layer 54 having a smooth surface is formed in a smooth state. In this way, the insulating base material 51 is manufactured.
【０００９】[0009]
【発明が解決しようとする課題】従来の接続構造は、平
滑な表面を有する表面金属層５５上に半田５８付けを行
うものであるため、表面金属層５５への半田５８の付着
強度が弱く、振動や衝撃等によって半田５８の剥がれ等
が生じるという問題がある。In the conventional connection structure, since the solder 58 is attached on the surface metal layer 55 having a smooth surface, the adhesion strength of the solder 58 to the surface metal layer 55 is weak, There is a problem that the solder 58 is peeled off due to vibration or shock.
【００１０】そこで、本発明は半田の付着強度が強く、
半田剥がれの無い接続構造を提供することを目的とす
る。Therefore, in the present invention, the adhesive strength of solder is strong,
It is an object of the present invention to provide a connection structure without solder peeling.
【００１１】[0011]
【課題を解決するための手段】上記課題を解決するため
の第１の解決手段として、平板状の絶縁基材と、この絶
縁基材上に形成された複数の金属層によって構成された
半田付け用ランド部とを備え、前記金属層は、前記絶縁
基材上に形成された下地金属層と、この下地金属層上に
形成された表面金属層で構成され、前記下地金属層の表
面を粗面となした上に、前記表面金属層を形成して、前
記表面金属層の表面を粗面となした構成とした。As a first means for solving the above-mentioned problems, as a first means for solving the problems, soldering composed of a flat insulating base material and a plurality of metal layers formed on the insulating base material is used. And a metal land layer formed on the insulating base material, and a surface metal layer formed on the base metal layer. The surface of the base metal layer is roughened. The surface metal layer was formed on the surface, and the surface of the surface metal layer was roughened.
【００１２】また、第２の解決手段として、前記下地金
属層は、前記絶縁基材上に形成されたＣｕ層からなる第
１下地金属層と、この第１下地金属層上に形成されたＮ
ｉ層からなる第２下地金属層とで構成されると共に、前
記表面金属層がＡｕ層で構成され、前記第１下地金属層
の表面を粗面となした上に、前記第２下地金属層と前記
表面金属層を順次形成して、前記表面金属層の表面を粗
面となした構成とした。As a second solution, the base metal layer is a first base metal layer made of a Cu layer formed on the insulating base material, and an N formed on the first base metal layer.
a second base metal layer composed of an i layer, the surface metal layer is composed of an Au layer, and the surface of the first base metal layer is roughened, and then the second base metal layer is formed. And the surface metal layer were sequentially formed to make the surface of the surface metal layer a rough surface.
【００１３】また、第３の解決手段として、前記絶縁基
材上に形成された前記下地金属層の表面がケミカルエッ
チングによって粗面に形成された。また、第４の解決手
段として、前記絶縁基材が回路基板で構成された。As a third solution, the surface of the base metal layer formed on the insulating base material is roughened by chemical etching. Further, as a fourth solving means, the insulating base material is composed of a circuit board.
【００１４】[0014]
【発明の実施の形態】本発明の接続構造について説明す
ると、図１は本発明の接続構造を示す要部の拡大断面図
で、ガラス入り基板等の回路基板からなる絶縁基材１
は、平板状をなし、この表面には、複数の金属層２から
なる半田付け用のランド部Ｒ１が設けられている。BEST MODE FOR CARRYING OUT THE INVENTION The connection structure of the present invention will be described. FIG. 1 is an enlarged cross-sectional view of a main part showing the connection structure of the present invention. An insulating base material 1 made of a circuit board such as a glass-filled board.
Has a flat plate shape, and a soldering land portion R1 including a plurality of metal layers 2 is provided on the surface thereof.
【００１５】そして、この金属層２は、絶縁基材１上に
形成され、表面が粗面となったＣｕ層の第１下地金属層
３、及びこの第１下地金属層３上に形成され、表面が粗
面となったＮｉ層の第２下地金属層４と、この第２下地
金属層４上に形成され、表面が粗面となったＡｕ層から
なる表面金属層５とで構成されている。The metal layer 2 is formed on the insulating base material 1 and is formed on the first base metal layer 3 of a Cu layer having a rough surface and on the first base metal layer 3. The second base metal layer 4 is a Ni layer having a rough surface, and the surface metal layer 5 formed on the second base metal layer 4 is an Au layer having a rough surface. There is.
【００１６】また、表面金属層５の表面粗さは、２ミク
ロン以上のもので形成されている。なお、ここでは二層
の下地金属層のもので説明したが、一層の下地金属層で
も良く、また、下地金属層はＣｕやＮｉ以外のもの、更
に、表面金属層はＡｕ以外のものを使用しても良い。The surface roughness of the surface metal layer 5 is formed to be 2 microns or more. In addition, although the description has been given here to the case of the two-layered base metal layer, a single base metal layer may be used, and the base metal layer other than Cu and Ni, and the surface metal layer other than Au may be used. You may.
【００１７】また、表面金属層５の上面には、絶縁材か
らなるレジスト層６が形成されて、このレジスト層６に
よって、ランド部Ｒ１の領域が形成されている。そし
て、Ｃｕ層からなる第１下地金属層３は、ここでは図示
しないが、配線パターンとして絶縁基体１上に形成され
たものとなっている。A resist layer 6 made of an insulating material is formed on the upper surface of the surface metal layer 5, and the resist layer 6 forms a land portion R1. Although not shown here, the first underlying metal layer 3 made of a Cu layer is formed on the insulating base 1 as a wiring pattern.
【００１８】ＩＣ部品やチップ抵抗等の電気部品、或い
は回路基板等からなる被接続部材７が絶縁基材１上に載
置され、半田８によってランド部Ｒ１に接続されて、接
続構造が構成されている。A connected member 7 composed of an IC component, an electric component such as a chip resistor, or a circuit board is placed on the insulating base material 1 and connected to the land portion R1 by the solder 8 to form a connection structure. ing.
【００１９】次に、このような構成を有する絶縁基材１
の製造方法を説明すると、先ず、Ｃｕ層からなる第１下
地金属層３によって所望の配線パターンが施された絶縁
基材１を用意する。Next, the insulating base material 1 having such a structure
First, the insulating base material 1 in which a desired wiring pattern is formed by the first base metal layer 3 made of a Cu layer is prepared.
【００２０】次に、半田付け用のランド部Ｒ１となる部
分の第１下地金属層３上に、ケミカルエッチングを行っ
て、ランド部Ｒ１となる部分の第１下地金属層３の表面
を粗面状態にする。Next, chemical etching is performed on the portion of the first base metal layer 3 that becomes the land portion R1 for soldering to roughen the surface of the first base metal layer 3 that becomes the land portion R1. Put in a state.
【００２１】次に、半田付け用のランド部Ｒ１となる部
分の第１下地金属層３の粗面となった表面上に、メッキ
によってＮｉ層からなる第２下地金属層４を形成する。
すると、第１下地金属層３の粗面となった表面上に形成
された第２下地金属層４の表面は、粗面となった状態で
形成される。Then, a second underlayer metal layer 4 made of a Ni layer is formed by plating on the roughened surface of the first underlayer metal layer 3 in the portion to be the land portion R1 for soldering.
Then, the surface of the second underlying metal layer 4 formed on the roughened surface of the first underlying metal layer 3 is formed in a roughened state.
【００２２】次に、第２下地金属層４の粗面となった表
面上に、メッキによってＡｕ層からなる表面金属層５を
形成する。すると、第２下地金属層４の粗面となった表
面上に形成された表面金属層５の表面は、粗面となった
状態で形成される。このようにして絶縁基材５１の製造
が行われる。Next, a surface metal layer 5 made of an Au layer is formed on the roughened surface of the second underlying metal layer 4 by plating. Then, the surface of the surface metal layer 5 formed on the roughened surface of the second underlying metal layer 4 is formed in a roughened state. In this way, the insulating base material 51 is manufactured.
【００２３】なお、この実施例では、第１下地金属層３
の表面をケミカルエッチングによって粗面としたもので
説明したが、第２下地金属層４の表面をケミカルエッチ
ングによって粗面とし、この第２下地金属層４上に表面
金属層５をメッキにより形成して、表面金属層５の表面
を粗面としても良い。In this embodiment, the first base metal layer 3
The surface of the second base metal layer 4 was roughened by chemical etching, but the surface of the second base metal layer 4 was roughened by chemical etching, and the surface metal layer 5 was formed on the second base metal layer 4 by plating. The surface of the surface metal layer 5 may be roughened.
【００２４】なお、この実施例では、絶縁基材が回路基
板で形成されたもので説明したが、ＩＣ部品やチップ抵
抗等の電気部品に適用しても良い。In this embodiment, the insulating base material is formed of the circuit board, but it may be applied to electric parts such as IC parts and chip resistors.
【００２５】[0025]
【発明の効果】本発明の接続構造は、平板状の絶縁基材
と、この絶縁基材上に形成された複数の金属層によって
構成された半田付け用ランド部とを備え、金属層は、絶
縁基材上に形成された下地金属層と、この下地金属層上
に形成された表面金属層で構成され、下地金属層の表面
を粗面となした上に、表面金属層を形成して、表面金属
層の表面を粗面となしたため、この表面金属層への半田
の付着強度が強くなって、振動や衝撃等によって半田の
剥がれ等の無いものが得られる。また、下地金属層と表
面金属層間は、粗面同士で付着した状態となって、両者
間の付着強度の強いものが得られる。The connection structure of the present invention comprises a flat insulating base material and a soldering land portion composed of a plurality of metal layers formed on the insulating base material. It is composed of a base metal layer formed on an insulating base material and a surface metal layer formed on the base metal layer. The surface of the base metal layer is made rough, and then the surface metal layer is formed. Since the surface of the surface metal layer is made rough, the adhesion strength of the solder to the surface metal layer is increased, and the solder is not peeled off due to vibration or shock. Further, between the underlying metal layer and the surface metal layer, the rough surfaces are adhered to each other, so that the adhesive strength between them is strong.
【００２６】また、下地金属層は、絶縁基材上に形成さ
れたＣｕ層からなる第１下地金属層と、この第１下地金
属層上に形成されたＮｉ層からなる第２下地金属層とで
構成されると共に、表面金属層がＡｕ層で構成され、第
１下地金属層の表面を粗面となした上に、第２下地金属
層と表面金属層を順次形成して、表面金属層の表面を粗
面となしたため、Ｃｕ層に対して、半田付けの良いＡｕ
層の形成が良好となるばかりが、Ｃｕ層、Ｎｉ層、及び
Ａｕ層間の３層の付着強度の強いものが得られる。The underlying metal layer includes a first underlying metal layer made of a Cu layer formed on the insulating base material and a second underlying metal layer made of a Ni layer formed on the first underlying metal layer. And the surface metal layer is composed of an Au layer, and the second base metal layer and the surface metal layer are sequentially formed on the surface of the first base metal layer as a rough surface. Since the surface of the copper is rough, it can be easily soldered to the Cu layer.
Not only is the layer formed well, but the three layers of the Cu layer, the Ni layer, and the Au layer having high adhesion strength are obtained.
【００２７】また、絶縁基材上に形成された下地金属層
の表面がケミカルエッチングによって粗面に形成された
ため、その作業が簡単で、生産性が良く、安価なものが
得られる。Further, since the surface of the underlying metal layer formed on the insulating base material is roughened by chemical etching, the work is simple, the productivity is good, and the cost is low.
【００２８】また、絶縁基材が回路基板で構成されたた
め、特に、電子回路ユニット等の多数の電気部品を使用
するものに適用すると、電気部品の半田付け不良の無い
ものが得られて好適となる。Further, since the insulating base material is composed of the circuit board, when it is applied particularly to a device using a large number of electric parts such as an electronic circuit unit, it is possible to obtain the one without soldering failure of the electric parts. Become.
【図１】本発明の接続構造を示す要部の拡大断面図。FIG. 1 is an enlarged cross-sectional view of a main part showing a connection structure of the present invention.
【図２】従来の接続構造を示す要部の拡大断面図。FIG. 2 is an enlarged cross-sectional view of a main part showing a conventional connection structure.
１ 絶縁基材 ２ 金属層 ３ 第１下地金属層 ４ 第２下地金属層 ５ 表面金属層 ６ レジスト層 ７ 被接続部材 ８ 半田 Ｒ１ ランド部 1 Insulating base material 2 metal layers 3 First underlying metal layer 4 Second underlying metal layer 5 Surface metal layer 6 Resist layer 7 Connected member 8 solder R1 land section
Claims (4)
形成された複数の金属層によって構成された半田付け用
ランド部とを備え、前記金属層は、前記絶縁基材上に形
成された下地金属層と、この下地金属層上に形成された
表面金属層で構成され、前記下地金属層の表面を粗面と
なした上に、前記表面金属層を形成して、前記表面金属
層の表面を粗面となしたことを特徴とする接続構造。1. A flat insulating base material and a soldering land portion composed of a plurality of metal layers formed on the insulating base material, wherein the metal layer is formed on the insulating base material. The underlying metal layer formed and a surface metal layer formed on the underlying metal layer, and the surface metal layer is formed on the surface of the underlying metal layer as a rough surface. A connection structure characterized in that the surface of the metal layer is roughened.
成されたＣｕ層からなる第１下地金属層と、この第１下
地金属層上に形成されたＮｉ層からなる第２下地金属層
とで構成されると共に、前記表面金属層がＡｕ層で構成
され、前記第１下地金属層の表面を粗面となした上に、
前記第２下地金属層と前記表面金属層を順次形成して、
前記表面金属層の表面を粗面となしたことを特徴とする
請求項１記載の接続構造。2. The base metal layer is a first base metal layer made of a Cu layer formed on the insulating base material, and a second base metal layer made of a Ni layer formed on the first base metal layer. And the surface metal layer is composed of an Au layer, and the surface of the first base metal layer is roughened.
The second base metal layer and the surface metal layer are sequentially formed,
The connection structure according to claim 1, wherein the surface of the surface metal layer is roughened.
属層の表面がケミカルエッチングによって粗面に形成さ
れたことを特徴とする請求項１、又は２記載の接続構
造。3. The connection structure according to claim 1, wherein the surface of the base metal layer formed on the insulating base material is roughened by chemical etching.
とを特徴とする請求項１から３の何れかに記載の接続構
造。4. The connection structure according to claim 1, wherein the insulating base material is a circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002069287A JP2003273484A (en) | 2002-03-13 | 2002-03-13 | Connection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002069287A JP2003273484A (en) | 2002-03-13 | 2002-03-13 | Connection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003273484A true JP2003273484A (en) | 2003-09-26 |
Family
ID=29200188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002069287A Withdrawn JP2003273484A (en) | 2002-03-13 | 2002-03-13 | Connection structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003273484A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008078655A1 (en) * | 2006-12-25 | 2008-07-03 | Rohm Co., Ltd. | Semiconductor device |
| WO2011052211A1 (en) * | 2009-10-30 | 2011-05-05 | パナソニック電工株式会社 | Circuit board, and semiconductor device having component mounted on circuit board |
| US8240036B2 (en) | 2008-04-30 | 2012-08-14 | Panasonic Corporation | Method of producing a circuit board |
| US8272126B2 (en) | 2008-04-30 | 2012-09-25 | Panasonic Corporation | Method of producing circuit board |
| US8698003B2 (en) | 2008-12-02 | 2014-04-15 | Panasonic Corporation | Method of producing circuit board, and circuit board obtained using the manufacturing method |
| US9082438B2 (en) | 2008-12-02 | 2015-07-14 | Panasonic Corporation | Three-dimensional structure for wiring formation |
| US9332642B2 (en) | 2009-10-30 | 2016-05-03 | Panasonic Corporation | Circuit board |
| CN106028638A (en) * | 2010-09-27 | 2016-10-12 | 吉坤日矿日石金属株式会社 | Copper foil for printed wiring board, method for producing said copper foil, resin substrate for printed wiring board and printed wiring board |
-
2002
- 2002-03-13 JP JP2002069287A patent/JP2003273484A/en not_active Withdrawn
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8446008B2 (en) | 2006-12-25 | 2013-05-21 | Rohm Co., Ltd. | Semiconductor device bonding with stress relief connection pads |
| CN101542704B (en) * | 2006-12-25 | 2011-04-20 | 罗姆股份有限公司 | Semiconductor device |
| US9018762B2 (en) | 2006-12-25 | 2015-04-28 | Rohm Co., Ltd. | Semiconductor device bonding with stress relief connection pads |
| WO2008078655A1 (en) * | 2006-12-25 | 2008-07-03 | Rohm Co., Ltd. | Semiconductor device |
| JP5570727B2 (en) * | 2006-12-25 | 2014-08-13 | ローム株式会社 | Semiconductor device |
| US8240036B2 (en) | 2008-04-30 | 2012-08-14 | Panasonic Corporation | Method of producing a circuit board |
| US8272126B2 (en) | 2008-04-30 | 2012-09-25 | Panasonic Corporation | Method of producing circuit board |
| US9332650B2 (en) | 2008-04-30 | 2016-05-03 | Panasonic Corporation | Method of producing multilayer circuit board |
| US8698003B2 (en) | 2008-12-02 | 2014-04-15 | Panasonic Corporation | Method of producing circuit board, and circuit board obtained using the manufacturing method |
| US9082438B2 (en) | 2008-12-02 | 2015-07-14 | Panasonic Corporation | Three-dimensional structure for wiring formation |
| US8929092B2 (en) | 2009-10-30 | 2015-01-06 | Panasonic Corporation | Circuit board, and semiconductor device having component mounted on circuit board |
| WO2011052211A1 (en) * | 2009-10-30 | 2011-05-05 | パナソニック電工株式会社 | Circuit board, and semiconductor device having component mounted on circuit board |
| US9332642B2 (en) | 2009-10-30 | 2016-05-03 | Panasonic Corporation | Circuit board |
| US9351402B2 (en) | 2009-10-30 | 2016-05-24 | Panasonic Corporation | Circuit board, and semiconductor device having component mounted on circuit board |
| CN106028638A (en) * | 2010-09-27 | 2016-10-12 | 吉坤日矿日石金属株式会社 | Copper foil for printed wiring board, method for producing said copper foil, resin substrate for printed wiring board and printed wiring board |
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