JP2003250987A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine which reports a time till contents stored in a volatile memory is erased or a timing for instructing the erasure of the storage contents of the volatile memory by an erasure instruction means. <P>SOLUTION: Back-up power source is fed from the back-up power source from a power source board to each RAM of sound boards being a main board and a sub-board, a pattern display board, a put-out control board, and an electric decorative board 46. When an erasure switch is depressed (S20: YES), the time of RAM clear completion is reported (S22), and the storage contents of the RAM in each board are erased (S24). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine such as a pachinko machine, and more specifically, to a memory content of a volatile memory arranged on a control board for controlling the gaming machine or a gaming machine control. The present invention relates to a gaming machine which notifies a time until the stored contents of volatile memories respectively arranged on a main substrate and a sub-substrate to be erased or a timing to instruct the erased contents of the volatile memory to be erased by the erase instruction means.

[0002]

2. Description of the Related Art Conventionally, in a game machine such as a pachinko machine, a main board for controlling the game machine is provided, and by this main board, a control of a pattern display device of the game machine, a control of a lighting mode of an electric decoration, a voice The control of the generation and the control of the payout of the game balls were performed. However, in recent years, the control of the gaming machine has become complicated, and the load on the main board increases when controlled only by the main board. Therefore, in addition to the main board that controls the gaming machine, a symbol display board for controlling the symbol display device, a game A game in which sub-boards such as a payout control board that controls the payout of balls, a lighting board that controls the light emission mode of the electric lighting of the gaming machine, and a sound board that controls the sound generation of the gaming machine are provided separately from the main board. There is an opportunity. In a gaming machine provided with such a sub-board, complicated control is possible without imposing an excessive load on the main board.

In a conventional game machine in which such a main board and other sub boards are separately provided, when power supply to some or all of the boards is cut off for some reason, the power is turned off. If there is already a big hit state before the supply of power is cut off or there is a prize ball payout, the jackpot state will be canceled when the power is turned on again, and the prize ball cannot be paid out, which is a disadvantage to the player. There are cases where inconveniences occur such as being in a different state. In order to prevent such a state, a backup means, which is a power source for holding the stored contents of the volatile memories of the main board and the sub-board, is provided and the volatile memory of the volatile memory is cut off when the power supply current to the board is cut off. A game machine that saves stored contents has been devised.

If a backup means is provided so that the contents stored in the volatile memory are always retained when the power supply to each board is cut off, the main power supply is cut off in the state of a big hit or in the probability fluctuation state. When the main power is turned on next time, the game is started from the big hit state or the probability varying state. This is an unfair condition for the player. In order to prevent this, a storage content erasing means for erasing the storage content of the volatile memory to restore the initial state, and an erase instruction button for instructing the storage content erasing means to erase the storage content of the volatile memory It is also conceivable that the contents stored in the volatile memory are erased by the storage contents erasing means by providing the above and operating the erasing instruction button.

[0005]

However, in the above gaming machine, it takes time to erase the stored content of the volatile memory by the stored content erasing means. Therefore, until the stored content of the volatile memory is erased. However, there is a problem that it is necessary to keep pressing the deletion instruction button, and it is difficult to know how long the deletion instruction button should be pressed.

The present invention has been made to solve the above problems, and it is the time until the stored contents of the volatile memory are erased or the timing at which the erase instruction means instructs the erase of the stored contents of the volatile memory. It is an object of the present invention to provide a gaming machine that can notify.

[0007]

In order to achieve the above object, a gaming machine according to the invention of claim 1 is a control board for controlling the gaming machine, and a power board for supplying power to the control board. Backup means for supplying stored power to a volatile memory provided on the control board to prevent the stored content of the volatile memory from being erased when power supply from the power supply board to the control board is stopped And a storage content erasing means for erasing the storage content of the volatile memory supplied with power for retaining the storage content by the backup means, and an instruction to erase the storage content of the volatile memory by the storage content erasing means. An erasing instruction means and an erasing time informing means for informing a time until the erasing of the stored content of the volatile memory by the stored content erasing means is provided.

In the gaming machine having this structure, the control board controls the gaming machine, the power supply board supplies power to the control board, and when the power supply from the power supply board to the control board is stopped, the backup means controls the control board. A power supply for holding the stored contents is supplied to the volatile memory provided in the storage unit to hold the stored contents of the volatile memory so as not to be erased. When the erasing instruction means instructs the erasing content of the volatile memory by the erasing content erasing means, the erasing content erasing means erases the memorized content of the volatile memory supplied with the power for holding the stored content by the backup means Then, the erasing time notifying means notifies the time until the erasing of the stored content of the volatile memory by the stored content erasing means is completed.

Further, the gaming machine of the invention according to claim 2 is characterized in that, in addition to the configuration of the invention according to claim 1, a liquid crystal display device is used as the erasing time informing means.

In the gaming machine of this construction, in addition to the operation of the invention described in claim 1, a liquid crystal display device is used as the erasing time notifying means until the erasing of the contents stored in the volatile memory is completed. Notify the time.

According to a third aspect of the present invention, there is provided a gaming machine according to the first aspect.
In addition to the configuration of the invention described in (1), a 7-segment LED is used as the erasing time informing means.

In the gaming machine of this structure, in addition to the operation of the invention described in claim 1, the erasing time informing means is
The LED of the segment is used to notify the time until the erasing of the stored contents of the volatile memory is completed.

Further, in the gaming machine of the invention according to claim 4,
In addition to the configuration of the invention according to claim 1, a plurality of LEDs are provided as the erasing time notification means, and the plurality of LEDs are provided.
Is sequentially turned on or off to notify the time until the erasing of the stored contents of the volatile memory is completed.

In addition to the operation of the invention described in claim 1, in the gaming machine of this structure, a plurality of LEDs are provided as the erasing time informing means, and the plurality of LEDs are sequentially turned on or off to volatilize. Of the time until the erasing of the stored contents of the static memory is completed.

Further, in the gaming machine of the invention according to claim 5,
In addition to the configuration of the invention according to any one of claims 1 to 4, the erasing time notifying means is a sounding means, and a sound is emitted from the sounding means until the erasing of the contents stored in the volatile memory is completed. It is characterized by notifying the time of.

In the gaming machine of this structure, in addition to the operation of the invention according to any one of claims 1 to 4, the erasing time notification means is a sounding means, and the sounding means emits a sound to emit the volatile matter. The time until completion of erasing the stored contents of the memory is notified.

Further, in the gaming machine of the invention according to claim 6,
A control board that controls the game machine, a power supply board that supplies power to the control board, and a memory content stored in a volatile memory provided on the control board when power supply from the power supply board to the control board is stopped Means for supplying stored power to the volatile memory so that the stored content of the volatile memory is not erased, and stored content for erasing the stored content of the volatile memory supplied with power for holding the stored content by the backup means Erase means, erase instruction means for instructing the erase of the stored content of the volatile memory by the erased content, and erase timing for notifying the timing of instructing the erase of the stored content of the volatile memory by the erase instructing means And notification means.

In the gaming machine having this structure, the control board controls the gaming machine, the power supply board supplies power to the control board, and when the power supply from the power supply board to the control board is stopped, the backup means controls the control board. A power supply for holding the stored contents is supplied to the volatile memory provided in the storage unit to hold the stored contents of the volatile memory so as not to be erased. When the erasing instruction means instructs the erasing content of the volatile memory by the erasing content erasing means, the erasing content erasing means erases the memorized content of the volatile memory supplied with the power for holding the stored content by the backup means Then, the erasing timing notifying means notifies the timing at which the erasing instruction means instructs the erasing of the contents stored in the volatile memory.

Further, the gaming machine of the invention according to claim 7 is characterized in that, in addition to the constitution of the invention according to claim 6, a liquid crystal display device is used as the erasing timing notifying means.

In the gaming machine of this structure, in addition to the operation of the invention described in claim 6, the liquid crystal display device as the erasing timing informing means informs the timing of erasing the stored contents of the volatile memory.

Further, the gaming machine of the invention according to claim 8 is characterized in that, in addition to the structure of the invention according to claim 6, a 7-segment LED is used as the erasing timing notifying means.

In the gaming machine of this structure, in addition to the operation of the invention described in claim 6, the 7-segment LED as the erasing timing informing means is used to set the timing for instructing the erasing of the contents stored in the volatile memory. Notify me.

Further, in the gaming machine of the invention according to claim 9,
In addition to the configuration of the invention described in claim 6, a plurality of LEDs are provided as the erasing timing notifying means, and the plurality of LEDs are sequentially turned on or off to instruct to erase the stored contents of the volatile memory. It is characterized by notifying the timing.

In addition to the operation of the invention described in claim 6, the gaming machine of this structure is provided with a plurality of LEDs as an erasing time informing means, and the plurality of LEDs are sequentially turned on or off to turn off the volatile memory. The timing for instructing deletion of the stored contents of is notified.

Further, in the gaming machine of the invention according to claim 10, in addition to the configuration of the invention according to any one of claims 6 to 9, the erasing timing notifying means is a sounding means,
It is characterized in that a sound is emitted from the sounding means to notify the timing of instructing the erasing of the contents stored in the volatile memory.

In the gaming machine of this structure, in addition to the operation of the invention according to any one of claims 6 to 9, a sound is emitted from the sounding means as an erasing timing notifying means to instruct to erase the contents stored in the volatile memory. Notify when to do.

Further, in the gaming machine of the invention according to claim 11, in addition to the configuration of the invention according to any one of claims 1 to 10, the erase instruction means is a push button.

According to the gaming machine having this structure, the first to the tenth aspects are provided.
In addition to the operation of the invention related to any one of the above, the push button is operated as an erasing instruction means to instruct to erase the stored contents of the volatile memory.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. A pachinko machine 1 according to a first embodiment, which is an embodiment of the present invention, will be described with reference to the drawings. First, the mechanical configuration of the pachinko machine 1 will be described. FIG. 1 is a front view of a pachinko machine 1. Figure 1
As shown in, the upper half of the front of the pachinko machine 1 is provided with a substantially square game board 2, and the game board 2 is provided with a substantially circular game area 4 surrounded by guide rails 3. ing. At the lower part of the game board 2 of the pachinko machine 1, there is provided an upper plate 5 for supplying a game ball to a launcher (not shown) and for receiving a prize ball. A lower plate 6 for receiving the overflowing prize balls is provided, and a firing handle 7 is provided on the right side of the lower plate 6.

Next, the mechanical structure of the game board 2 is shown in FIG.
Will be described with reference to. FIG. 2 is a front view of the game board 2 of the pachinko machine 1. The game board 2 is provided with a substantially circular game area 4 surrounded by the guide rails 3, and a special symbol display device 8 having a liquid crystal screen is provided substantially in the center of the game area 4. Further, an electric decoration windmill 9 is provided on the upper right side of the special symbol display device 8, and an electric decoration windmill 10 is also provided on the upper left side. Further, a normal symbol starting gate 11 is provided on the right side of the special symbol display device 8, and a normal symbol starting gate 12 is also provided on the left side.

Also, directly below the special symbol display device 8, a special symbol starting electric accessory 15 is provided, and below the special symbol starting electric accessory 15, a special winning opening 16 is provided. A normal winning opening 30 and a normal winning opening 31 are provided on the left and right of the big winning opening 16.

Further, below the normal symbol starting gate 11, a normal winning opening 19 is provided, and the normal symbol starting gate 1
A normal winning opening 20 is provided below 2. Further, at the bottom of the special symbol display device 8, a stage 21 on which a game ball can be temporarily placed is horizontally provided. The game ball passage port 22 is provided on the right shoulder of the special symbol display device 8, and the game ball passage port 23 is also provided on the left shoulder of the special symbol display device 8. The game balls that have passed through these game ball passage openings 22 and 23 are exposed to the stage 21 through the inside (warp zone) of the special symbol display device 8. Stage 2
The game ball appearing in 1 is designed to drop toward the special symbol starting electric accessory 15 provided immediately below the stage 21.

Further, a normal symbol display device 24 is provided above the special symbol display device 8 so that a symbol such as a single digit number or a single letter alphabet can be displayed. Further, a special symbol start holding section 25 consisting of two LEDs each is provided on the left and right of the normal symbol display device 24, and the number of so-called holding balls that have won the special symbol starting electric accessory 15 is displayed. You can Further, between the special symbol display device 8 and the normal symbol display device 24, 4
A normal symbol start-up holding section 26 consisting of individual LEDs is provided, and the normal symbol start-up holding section 26 can display the so-called holding ball number of the game balls that have passed through the normal symbol start gates 11 and 12. In addition to the above, the game board 2 is provided with an outlet, various electric lamps, a windmill, a large number of obstacle nails, etc. at predetermined positions.

Next, the structure and display screen of the special symbol display device 8 will be described with reference to FIG. FIG. 3 is a front view of the special symbol display device 8. As shown in FIG. 3, on the liquid crystal screen of the special symbol display device 8, three special symbols, that is, a first stop symbol L1, a second stop symbol L2, and a third stop symbol L3 can be displayed side by side in a row. ing. The special symbol display device 8, the first stop symbol L1, the second stop symbol L described above.
In addition to the display of the second and third stop symbols L3, a moving image, a message, etc. can be displayed. The special symbols may be displayed not only in the horizontal direction but also in the vertical direction or the diagonal direction. The special symbol display device 8 uses not only a liquid crystal display device but also a CR
Various display devices such as T, LED, and plasma displays can be used. In addition, the special symbol display device 8,
A pattern control board 44 (see FIG. 4) is provided on the back surface.

First stop symbol L1 and second stop symbol L described above
2, as an example of the symbols respectively displayed in the third stop symbol L3, "Imman", "Nimman", "Manman", which imitates Mahjong tiles,
"Four-man", "Five-man", "Six-man", "Seven-man", "Eight-man",
"Kuman", "white plain (hereinafter referred to as" white ")",
There are twelve types of "發" and "middle", and the game ball wins the special symbol starting electric auditors product 15, three symbols of the first stop symbol L1, the second stop symbol L2, and the third stop symbol L3. If you have the same numbers, letters, or designs (for example, if you have three "Nanman" shown in Fig. 3), or if you have a combination of particular numbers, letters, or designs, It is a big hit.

Further, among the 12 patterns, "Sanman", "Goman", "Nanman", "White", "Kaku", "Mid" are stochastic fluctuation patterns (specific jackpot patterns), and these If any of the symbols in the first stop symbol L1, the second stop symbol L2, and the third stop symbol L3 are aligned with the same symbol, it is considered as a probability variation rush and the probability of drawing the next jackpot is increased. change. The jackpot probability, as an example, in the normal state,
It is 1 / 317.6, which is 68.1 in the stochastic state.
It is one-third, but not limited to this value. In addition, "one man", "two man", "four man", "six man",
"Hachiman" and "Kyuman" are non-probability fluctuation designs (non-specific jackpot designs or normal designs).

Next, the electrical circuit configuration of the pachinko machine 1 of the present embodiment will be described with reference to FIG. Figure 4
It is a block diagram showing an electric circuit configuration of the pachinko machine 1. The control unit of the pachinko machine 1 includes a main board 41 and a power board 4.
2, sound board 43, symbol display board 44, payout control board 4
5, a lighting board 46, and a launch board 47. The main board 41 includes a power board 42, a sound board 43, and a pattern display board 4.
4, a payout control board 45, an illumination board 46, and a launch board 47 are connected to each other.

FIG. 5 shows the main board 4 of the pachinko machine 1.
1, supply of power supply current between the power supply board 42, the sound board 43, the symbol display board 44, the payout control board 45, and the decorative board 46,
It is a figure explaining the flow of a signal. As shown in FIG. 5, the main board 41 includes a CPU 41a, a ROM 41b, and a RAM 41.
c, I / O interface 41d, reset circuit 17
Are connected to each other by a bus line 41e, and the power supply board 42 is provided with an erase switch 42s. The sound board 43 includes a CPU 43a, a ROM 43b,
A RAM 43c, an I / O interface 43d, etc. are connected to each other by a bus line 43e and arranged. Similarly, the symbol display board 44 has a CPU 44a and a ROM 44.
b, a RAM 44c, an I / O interface 44d, etc. are arranged by being connected to each other by a bus line 44e, and the payout control board 45 has a CPU 45a, a ROM 45b, and an RA.
The M45c, the I / O interface 45d, etc. are connected to each other by the bus line 45e, and are arranged.
6, CPU 46a, ROM 46b, RAM 46c, I
The / O interface 46d and the like are arranged so as to be mutually connected by a bus line 46e. In addition, the power supply board 4
The connection line connected to 2 is provided with a power switch 80 capable of supplying or cutting off the AC24V power supply current supplied from a power supply source (not shown).

From the power supply board 42, the power supply line 82a is connected to the main board 41, the power supply line 82b is connected to the sound board 43, and the power supply line 82 is connected to the symbol display board 44.
c is connected, the power supply line 82d is connected to the payout control board 45, the power supply line 82e is connected to the decorative board 46, and the power supply current is connected to each board. The power supply line 8
As for 2a to 82e, as shown in FIG. 4, DC + 12 including a backup power source for retaining stored contents
Although power supply lines for supplying a power supply of a voltage corresponding to each application such as V and DC + 5V to each substrate are separately provided, details are omitted in FIG. 5 for simplification of description.

As shown in FIG. 5, the erasing switch 42s provided on the power supply board 42 is connected to the I / O interface 41d of the main board 41 by a signal line 79a and the I / O of the sound board 43 by a signal line 79b. O interface 4
3d, and the symbol display board 44 by the signal line 79c
Signal line 7 connected to the I / O interface 44d of
It is connected to the I / O interface 45d of the payout control board 45 by 9d, and is connected to the I / O interface 46d of the electric decoration board 46 by a signal line 79e.

The erase switch 42s is, for example, a push button switch, and is configured to close the circuit only when the switch is pressed. When the erase switch 42s is pressed, a signal of a predetermined voltage is sent to the main board 41, the sound board 43, the pattern display board 44, the payout control board 45, and the decoration board 46 by the power supply current supplied from the power supply board 42. Composed. The main board 41, the sound board 43, and the pattern display board 4
4, the power supply current may be supplied from all or part of the payout control board 45 and the illumination board 46 to open and close the circuit by the erasing switch 42s. The wiring may be star-shaped or loop-shaped.

When the erasing switch 42s is opened and closed in this way, for example, the signal sent by the erasing switch 42s by the signal line 79a connected to the main board 41 is transmitted from the I / O interface 41d via the bus line 41e to the CP line.
CPU 41a of the main board 41 received by U41a
Knows that the erase switch 42s is ON. Similarly, the signal transmitted by the erasing switch 42s is transmitted by the signal line 79b connected to the sound substrate 43 to the I / O.
It is received by the CPU 43a from the interface 43d via the bus line 43e, and the CPU 43 of the sound board 43 is received.
"a" recognizes that the erasing switch 42s is turned on, and the signal sent by the erasing switch 42s by the signal line 79c connected to the symbol display board 44 is transmitted from the I / O interface 44d through the bus line 44e. C
Received by the PU44a, the CPU of the symbol display board 44
44a recognizes that the erasing switch 42s is ON, and the signal line 79d connected to the payout control board 45.
Causes the signal sent by the erase switch 42s to
C of the payout control board 45, which is received by the CPU 45a from the O interface 45d via the bus line 45e.
The PU 45a recognizes that the erasing switch 42s is turned on, and the signal line 79e connected to the decorative board 46.
Causes the signal sent by the erase switch 42s to
It is received by the CPU 46a from the O interface 46d via the bus line 46e, and the CPU of the decorative board 46 is received.
46a recognizes that the erase switch 42s is ON.

Now, returning to FIG. 4 and continuing the description, on the main board 41, the winning opening switches 32 respectively provided in the normal winning openings 19, 20, 30, 31 (see FIG. 2),
Special symbol start Starting port switch 33 for detecting the winning of the game ball to the electric accessory 15, and normal symbol start gates 11 and 12
(See FIG. 2) A gate switch 34 for detecting passage of a game ball to the special winning opening, a count switch 35 for detecting the number of winning balls of the game ball to the special winning opening 16, and a V zone provided in the special winning opening 16 V switch 36 for detecting the winning of the game ball to (not shown), and special symbol starting electric accessory 15 (see FIG. 2)
Special symbol start electric accessory solenoid 37 that opens and closes the opening and closing member, a special winning opening solenoid 38 that opens and closes the special winning opening 16 (see FIG. 2), an induction device solenoid 39, and a jackpot of the game machine to an external device. External connection terminal 2 substrate 40 for outputting information, and 7-segment LED (light emitting diode)
A normal pattern substrate 60 which is composed of a display device and displays a normal pattern is connected.

The external connection terminal 2 substrate 40 is provided with a jackpot 1 information terminal, a jackpot 2 information terminal, and a symbol confirmation information terminal, and the jackpot information and the special symbol display device 8 are determined by an external device. Information on the displayed symbols can be output. The special symbol display device 8 is connected to the symbol display substrate 44, and the speaker 6 is attached to the sound substrate 43.
1 is connected, the illumination board 46 is connected to the illumination lamp-related board 62, and the illumination lamp-related board 62 is connected to each illumination lamp provided on the surface of the game board 2. .

Further, on the main board 41, a lower plate full detection switch 6 for detecting that the lower plate 6 is full of game balls.
3, a prize ball passage out-of-ball detection switch 64 for detecting a ball out of a prize ball passage (not shown), and a prize ball payout confirmation switch 65 for confirming the number of prize balls paid out from a prize ball device (not shown) are connected. Has been done. The prize ball payout confirmation switch 65 is also connected to the payout control board 45.

Further, on the payout control board 45, a ball lending passage out-of-ball detection switch 66 for detecting the ball out of the ball lending passage.
A ball lending / discharging confirmation switch 67 for confirming the number of balls to be dispensed from a ball lending device (not shown), a prize ball dispensing solenoid 68 for driving a prize ball device (not shown), and a ball lending device (not shown). A ball lending / discharging solenoid 69 to be driven and a prize ball tank for storing a prize ball provided on the upper rear surface of the pachinko machine 1 are provided on a tank rail (not shown) for guiding the game ball to the ball lending device. The tank rail vibrating motor 70 that vibrates the tank rail to prevent the game balls from clogging the tank rail, and the prepaid card unit 71 that reads out the lending data from the prepaid card.
The external connection terminal 1 is connected to the substrate 72. The external connection terminal 1 substrate 72 is provided with a prize ball payout number information terminal and a ball lending payout number information terminal, and can output the prize ball payout number information and the ball lending payout number information to an external device.

Further, the launch board 47 has a launch ball flying strength adjustment volume 73 built in the launch handle 7.
, Launcher stop switch 74 and touch sensor 75
And the firing motor 76 are connected.

Next, the power supply board 42 will be described. 24 V AC is input to the power supply board 42 via the power switch 80, and 5 V DC, 12 V DC, 24 V DC, 3 V DC are supplied by the internal rectifying circuit and smoothing stabilizing circuit.
2V and can be output. The power supply board 42 can also output a reset signal, a backup power supply, a power failure detection signal, and an alternating current of 24V. Furthermore, in the power supply board 42, the output of DC 12 V is DC + 1.
3 circuits of 2VA, DC + 12VB and DC + 12VC are prepared. DC + 12VA is connected to the main board 41, and DC + 12VB is the main board 41 and the payout control board 45.
, And DC + 12VC are connected to the special symbol display device 8, the sound board 43, and the decorative board 46. Further, 24 V AC is input from the power supply board 42 to the payout control board 45, and the backup power supplies are the main board 41, the sound board 43, the pattern display board 44, the payout control board 45, and the decorative board. Connected to 46.

The output of DC24V is DC + 24V
Two circuits of A and DC + 24VB are prepared, DC + 24V
A is connected to the main board 41, and DC + 24VB is connected to the payout control board 45. Further, the output of DC 32V is prepared as one circuit of DC + 32V and is connected to the launch board 47. The output of DC 5V is prepared as one circuit of DC + 5V and is connected to the main board 41, the special symbol display device 8, the sound board 43, the payout control board 45, the illumination board 46, and the launch board 47. It is to be noted that a launching device stop signal is inputted from the payout control substrate 45 to the launching substrate 47 through a signal line 77.

An erase switch 42s is arranged on the power supply board 42. This is because the power source for the erase switch 42s to transmit a signal is the power supply board 42s in the first embodiment.
Since the power is supplied from the power supply board 42, the erase switch 42s is not necessarily provided on the power supply board 42. For example, a push button may be provided at a position separated from the power supply board 42, or a key operation may be performed. In short, the position and form are not limited as long as a signal can be transmitted.

Next, referring to FIG. 5, the main board 41, the power supply board 42, and the sound board 4 of the pachinko machine 1 of the first embodiment.
3, symbol display board 44, payout control board 45, decorative board 4
6 and the supply of power supply current and the flow of signals between them will be described in detail. First, the main board 41 has CPUs 41a, R
An OM 41b, a RAM 41c, a reset circuit 17, and the like are provided, and a ROM 41b stores a main control program for controlling the entire pachinko machine 1 executed by the CPU 41a, initial value data, and the like. Further, a program for erasing the stored contents of the RAM 41c to which the power for holding the stored contents is supplied (backed up) according to the present embodiment is also stored here.
The RAM 41c is a volatile memory that stores various data and the like. For example, the RAM 41c is configured by a power-saving C-MOS static RAM, and a backup power source of the power source substrate 42 is used to connect the main substrate 41 to the power source substrate 42. Even when the power supply to the device is cut off, the stored contents are retained for a long time.

The sound board 43 includes a CPU 43a and a ROM 4
3b, RAM 43c, etc. are provided mutually connected to the bus line 43e, and ROM 43b stores audio data and the like, and various programs executed by the CPU 43a and initial value data and the like. Also,
Backed up RAM 43c in the present embodiment
A program for erasing the stored contents of is also stored here. The RAM 43c is a volatile memory that stores various data and the like, and is stored even when the normal power supply from the power supply board 42 to the sound board 43 is cut off by the backup power supply of the power supply board 42. Power is supplied (backed up) to retain the contents
It is like this.

The symbol display board 44 has CPUs 44a, R
An OM 44b, a RAM 44c, etc. are provided so as to be mutually connected to the bus line 44e, and various display data displayed on the special symbol display device 8 and a CPU are provided in the ROM 44b.
Various programs executed by 44a, data of initial values, and the like are stored. Further, a program for erasing the stored contents of the RAM 44c to which the power for holding the stored contents in the present embodiment is supplied (backed up) is also stored here. In addition, RAM44c,
It is a volatile memory for storing various data and the like, and by the backup power source of the power source board 42, the symbol display board 44
The stored contents are retained even when the normal power supply from the power supply board 42 to the power source is cut off.
The symbol display board 44 can be configured to include a plurality of CPUs in accordance with the recent high definition and high speed of images.

The payout control board 45 includes CPUs 45a, R
An OM 45b, a RAM 45c and the like are provided so as to be mutually connected to the bus line 45e, and the ROM 45b has a CP.
Various programs executed by U45a, data of initial values, and the like are stored. Further, a program for erasing the stored content of the RAM 45c to which the power for holding the stored content in the present embodiment is supplied (backed up) is also stored here. In addition, RAM45c
Is a volatile memory that stores various data, for example, the number of winning prize balls and the number of prize balls to be paid out.
The stored contents are retained even when the normal power supply from the power supply board 42 to 5 is cut off.

The illumination board 46 includes a CPU 46a and a ROM.
46b, a RAM 46c and the like are provided so as to be mutually connected to the bus line 46e, and the ROM 46b includes a CPU 4
6a stores programs such as various lighting patterns executed by 6a, data of initial values, and the like. Further, a program for erasing the stored contents of the RAM 46c to which the power for holding the stored contents in the present embodiment is supplied (backed up) is also stored here. Also,
The RAM 46c is a volatile memory that temporarily stores various data, for example, an illumination pattern to be controlled at the time of a big hit.
Even if the normal power supply from the power supply board 42 to the decorative board 46 is cut off, the stored contents are retained.

The backup power supply for the power supply board 42 is N
It is composed of a secondary battery such as an iCd battery, an electrolytic capacitor, etc., and when a current of 24 V AC, which is a normal power supply current, is input, it is rectified by a rectifier circuit (not shown) and is a backup power supply NiCd. Secondary batteries such as batteries, electrolytic capacitors, etc. are charged.
When the power supply to the power supply board 42 is stopped, the current charged in the secondary battery such as a NiCd battery or the electrolytic capacitor is supplied to the RAM 41c of the main board 41, the RAM 43c of the sound board 43, and the symbol display board 44. RAM4
4c, RAM 45c of payout control board 45, illumination board 46
It can be supplied to the RAM 46c as a power source for holding the stored contents. Further, a power switch 80 is provided on the input side of the power supply board 42 for the AC 24V, and it is possible to supply or stop the supply of the AC 24V to the power supply board 42.

In the main substrate 41 of this embodiment, C
The PU 41a, the ROM 41b, and the RAM 41c are formed as a 64-pin microcomputer that is modularized in one chip, and this microcomputer has a VBB terminal (not shown) that is a power supply terminal for backup. This VBB
The current from the backup power source of DC + 5V is input to the terminal. This microcomputer is configured so that the main power source of the microcomputer does not turn on unless there is an input to the VBB terminal. Therefore, if there is no means for erasing the contents stored in the RAM 41c as in the case of the present embodiment, a switch for pulling out the cord connected to the VBB terminal or disconnecting the cord is used to erase the RAM 41c. It is necessary to physically disconnect the backup power supply of the power supply board 42 to the VBB terminal by separately providing and disconnecting. However, in this case, there arises a disadvantage that the power source of the main board 41 is turned off.
Also, the sound board 43, the symbol display board 44, the payout control board 4
5. The decorative board 46 also has the same configuration as the main board 41, and therefore these RAMs 43c, 44c, 45c,
In order to erase the stored contents of 46c, the connection from the backup power supply of the power supply board 42 to the VBB terminal must be physically disconnected. In the pachinko machine 1 of the first embodiment, the main board 41, the sound board 43, the symbol display board 44, and the payout control board 4 can be operated without such complicated work.
5, RAM 41c, 43c, 44c, 4 of the decorative substrate 46
The stored contents of 5c and 46c can be easily erased.

Incidentally, as shown in FIG.
RAM45 backed up by a backup power supply
An erasing time notification unit 41f is provided to notify the time until the erasing of the stored contents of c is completed.

Next, a specific example of the notification means 41f will be described with reference to FIGS. 7 segment LED
It is a perspective view of 41f1. FIG. 8 shows a liquid crystal display device 41f.
2 is a front view of FIG. FIG. 9 is a front view of a display device 41f3 provided with a plurality of LEDs 41f31. In order to use the 7-segment LED 41f1 shown in FIG. 7, the time until the erasing of the contents stored in the RAM 45c is completed is counted down by a numeral. When using the liquid crystal display device 41f2 shown in FIG. 8, a bar 41f is provided on the liquid crystal display device 41f2.
21 is displayed, and the color of the bar is changed according to the time until the deletion of the stored contents of the RAM 45c is completed. When all the colors of the bar 41f21 on the liquid crystal display device 41f2 have changed, the erasing of the stored contents of the RAM 45c is completed. When the display device 41f3 shown in FIG. 9 is used, the LED 41f31 provided on the display device 41f3 is used.
When all the LEDs 41f31 are turned on by sequentially turning on, the erasing of the stored contents of the RAM 45c is completed.
Incidentally, when the LEDs 41f31 provided on the display device 41f3 are all turned on first and all the LEDs 41f31 are turned off, the erasing of the stored contents of the RAM 45c may be completed. The time until the completion of erasing, which is notified by the notification means 41f, is known in advance from the characteristics of the RAM, so it is set according to the time.

Next, the operation of the pachinko machine 1 of the first embodiment will be described with reference to the flow charts shown in FIGS. 10 and 11 by taking the main routine (main control) of control in the main board 41 as an example. FIG. 10 is a flowchart showing a main routine (main control) of the pachinko machine 1. Figure 1
1 is the power-on process (S
It is a flow chart which shows the procedure of 1) in detail.

The main routine of the flow chart shown in FIG. 10 has a fixed interval time (for example, 2 milliseconds, hereinafter referred to as "2 ms"), and the reset circuit 17 shown in FIG.
CPU of the main board 41 according to the reset signal generated by
41a performs processing sequentially from the start, and processing from the start to the end is performed within 2 ms.
Therefore, every time a reset signal is input at 2 ms intervals, the process is repeated from the start. This FIG.
A program for performing the processing of the flowchart shown in is a ROM
It is stored in 41b.

First, the main routine of the pachinko machine 1 will be described with reference to FIG. First, when the power is turned on,
Power-on processing (S1) is executed.

Here, the procedure of the power-on process (S1) of the flowchart shown in FIG. 10 will be described in detail with reference to FIG. When power is supplied from the power supply board 42 to the main board 41 (power ON), that is, when the power switch 80 of the power supply board 42 is turned ON or the power failure state is restored, the CPU 41a of the main board 41 starts up, ROM4
The following procedure is performed according to the control program read from 1a. First, the activated CPU 41a determines whether or not the erase switch 42s arranged on the power supply board 42 is turned on via the I / O interface 41d and the signal line 79a shown in FIG. 5 (S20). If the signal from 42s is equal to or higher than the voltage of the predetermined HI level, it is determined to be ON (S20: YES), and if it is less than the voltage of the predetermined level, it is determined to be OFF (S20: N).
O).

In the pachinko machine 1, when the power switch 80 is closed, the RAM 41c is the D of the power board 42.
The memory contents are retained by being supplied with a power source current of C + 5V, but even when the power switch 80 is cut off, the main substrate 41 is supplied from the backup power source battery provided on the power substrate 42 via the power supply line 82a. Since the power supply current is input to the RAM 41c from the VBB terminal of the one-chip microcomputer provided in, the contents stored in the RAM 41c are retained as they are.

Here, in S20, the erase switch 42
When it is determined that s is not turned on (S20: N
O), that is, when the erasing switch 42s is not pressed, the power recovery process (S26) is performed. Power recovery process (S2
6) The CPU 41a reads out the contents stored in the RAM 41c that is backed up by the power supply for holding the stored contents, and based on the contents stored in the RAM 41c, the power source is an attendant of the game hall. In the case where the pachinko machine 1 is disconnected by the intention or against the intention, the state of the pachinko machine 1 is restored to the state before the power is cut off. For example, even if there is a power outage due to an accident during a player's game, if the player is in the jackpot state before the power outage, the jackpot flag stored in the RAM 41c after the power is restored is turned on. The game can be continued again in the big hit state.

When the pachinko machine 1 has already performed the normal processing, in the power recovery processing (S26),
The restoration process is not performed, and the process based on the storage content of the RAM 41c is continued. When the power recovery process (S26) ends, the power-on process (S1) of FIG. 10 ends, and the process proceeds to the next stack pointer set process (FIG. 10: S2).

On the other hand, if the erasing switch 42s is pressed when the power is turned on, that is, if the erasing switch 42s is turned on (S20: YES), the stored contents of the RAM 41c backed up are cleared (erased) by software. )
The RAM clear completion time is notified to notify the time until the completion (S22).

This RAM clear completion time notification (S22)
Is the RAM 41c that has been backed up.
The time required to clear the stored contents in the form of software is notified using the notification means shown in FIGS. 7 to 9. For example, if it takes 3 seconds to clear the stored contents of the RAM 41c by software, in the case of the 7-segment LED 41f1 shown in FIG. 7, "3",
"2", "1", "0" and numbers that count down every second are displayed.

When the liquid crystal display device 41f2 shown in FIG. 8 is used, for example, if it takes 3 seconds to clear the stored contents of the RAM 41c by software, the bar 41f21 can be moved from the end in 3 seconds. Try to change colors in order. When the display device 41f3 shown in FIG. 9 is used, for example, if the time taken to clear the stored contents of the RAM 41c by software is 3 seconds, L
The ED 41f31 is sequentially turned on in 3 seconds from the end.

Further, when the RAM clear completion time is notified by the voicing means, the CPU 41a on the main board 41 is used.
A signal designating a pattern produced by the speaker 61 is sent from the sound substrate 43. On the sound board 43, the voice information according to the pattern is read from the ROM 43b and is uttered from the speaker 61 via the drive circuit. For example, R
If it takes 3 seconds to clear the stored contents of the AM 41c by software, it sounds "Sun", "Nii", "Ichi", "Zero" at 1 second intervals, or "RAM".
Only 3 seconds to clear. "It takes 2 seconds to clear the RAM.""It takes 1 second to clear the RAM.",
The voice is said, "RAM cleared."

The RAM clear completion time notification (S22)
Simultaneously with the start, the CPU 41a executes a backup RAM clear for clearing (erasing) the stored contents of the RAM 41c backed up by software (S24). The clerk at the game arcade keeps pressing the erasing switch 42s until the RAM clear completion time notification (S22) is completed, and releases the erase switch 42s when the RAM clear completion time notification (S22) is completed. Therefore, the staff at the game arcade does not continue to press the erasing switch 42s for more than the required time.

When the backup RAM clear (S24) is completed, the power-on process (S1) of FIG. 10 is completed (FIG. 11: END), and the procedure moves to the next stack pointer set process (FIG. 10: S2). In addition, backup RA
The M clear (S24) ends until the RAM clear completion time notification ends.

In the flowchart shown in FIG. 10, when the power-on process (S1) is completed, the stack pointer setting process for setting the designated address of the stack pointer is next performed (S2). Then, a RAM check is performed to check the stored contents of the RAM 41c (S3).
This RAM check (S3) is for determining whether or not the initial setting process (S4) at power-on is being performed. At this time, it is determined whether or not a predetermined numerical value written in the power-on initialization process (S4) is written in the initialization storage area of the RAM 41c.

When the backup RAM clear process (S24) shown in FIG. 11 is being performed, the RAM 41
Since the predetermined numerical value is not written in the initial setting storage area of c (S3: NO), the power-on initial setting process is performed (S4). Also, if the storage of the RAM 41c becomes abnormal for some reason other than when the power is turned on, the RAM check (S3) determines that the RAM 41c is not normal. In this process, the storage value of each storage area of the RAM 41c is set to a predetermined default value. For example, the value of each loop counter stored in the loop counter storage area (not shown) is set to an initial value (for example, "0"), and a predetermined numerical value is stored in the initial setting storage area. Then, the processing of FIG. 10 is once ended (end).

With the reset signal, the processing is performed from the start. First, in the power-on process (S1), if the erase switch 42s is not pressed (FIG. 11: S20: N
O), power recovery processing (S26) is performed, but already RAM4
Since it is processed based on the memory of 1c, nothing is performed here as described above, and the stack pointer setting process (S
Go to 2). And in the RAM check (S3),
Since the predetermined numerical value is written in the initial setting storage area, the RAM 41c is determined to be normal (S3: YES),
Then, the process proceeds to the next liquid crystal screen command output process (S5). In this liquid crystal screen command output process (S5), the main board 41
A signal for controlling the display of the liquid crystal screen is sent from the pattern display board 44 to the pattern display board 44, and the control signal is once sent to the pattern display board 44 by R
Information stored in the AM 44c is read out based on a table stored in the ROM 44b by a lottery designated or drawn based on this control signal, and information about a predetermined symbol is read out from the drive circuit (not shown) to send image information to the special symbol display device 8. .

Then, the process proceeds to the sound command output process (S6). In this sound command output process (S6), a signal designating a pattern to be uttered by the speaker 61 is sent from the main board 41 to the sound board 43, and the sound board 43 reads out audio information according to the pattern from the ROM 43b and the drive circuit. The speaker 61 is uttered via. Then
A lamp command output process (S7) is performed. In this lamp command output process (S7), a signal designating the blinking pattern of various lamps provided in the pachinko machine 1 is output from the main board 41 to the decorative board 46. Illuminated board 46
Then, the information of the electric control of this pattern is read from the ROM 46b and the drive signal is sent to various lamps. Next, port output processing is performed (S8). In this port output process (S8), jackpot information of the pachinko machine 1, symbol confirmation information and the like are output to a computer for game hall management (not shown) via the external connection terminal 2 substrate 40 and the like.

Then, a switch reading process (S9) is performed. This switch reading process (S9) is the normal symbol starting gates 11 and 12, the special symbol starting electric accessory 1 shown in FIG.
5, big prize hole 16, normal prize hole 19, 20, 30, 31
It is for detecting the winning of the game ball to the game etc.

When the switch reading process (S9) is completed,
Then, a loop counter updating process (S10) is performed. In the loop counter updating process (S10), the RAM 41
The value of the normal symbol selection loop counter, the big hit determination loop counter, the special symbol creation counter, the reach determination counter, and the reach pattern determination counter, which are respectively stored in the loop counter storage area (not shown) of c, are increased by a predetermined amount ( Increment). When the maximum value set in each loop counter is exceeded, the value of each loop counter is cleared to 0 and programmed to return to "0".

Next, it is judged whether or not an error has occurred in the pachinko machine 1 (S11), and if an error has occurred in the pachinko machine 1 (S11: YES), the condition device processing (S12), Special symbol processing (S13), normal symbol processing (S14) is skipped to perform the processing, and the special symbol display device 8
To display an error. When no error has occurred (S11: NO), the process proceeds to the condition device process (S12).

In the condition device processing (S12), the special winning opening 1
Opening and closing of 6 (see FIG. 2), jackpot demonstration display processing and the like on the liquid crystal screen (see FIG. 3) of the special symbol display device 8 are performed. In the first round of processing, special symbol processing (S
Since the big hit determination process in 13) has not been performed yet, nothing is performed in the condition device process (S12) and the process proceeds to the next process. Next, special symbol processing (S13) is performed. In this special symbol process (S13), a big hit determination process is performed.

When the special symbol processing (S13) ends, next, the normal symbol processing (S14) is performed. In this normal symbol processing (S14), due to the passage of the game sphere to the normal symbol starting gates 11 and 12, the count value of the normal symbol selection loop counter (not shown) is a RAM as a normal symbol random number.
It is stored in the normal symbol random number storage area (not shown) of 41c,
The symbol is fixedly displayed on the normal symbol display device 24 based on the normal symbol random number.

When the normal symbol processing (S14) ends, next, payout control (S15) for paying out prize balls is performed.
When paying out the prize balls, the signal line 78 is fed from the main board 41.
A payout request command is transmitted to the payout control board 45 via. The payout control board 45 temporarily stores the payout request command in the RAM 45c, and sequentially pays out the prize balls based on the payout request command. And frame lamp control (S16)
After that, the processing of the main routine ends. Note that the processing of this main routine, including the processing of the subroutine,
Finish within ms. Therefore, the main routine does not always execute all the procedures up to the end, but leaves the result of the processing in a flag or the like, and is executed so as to always end within 2 ms. The CPU 41a receives a reset signal from the reset circuit 17 every 2 ms.
Repeats the processing of the main routine shown in FIG. 10 from the start.

If the special symbol processing (S13) of the processing of the main routine of the first round is determined to be a big hit state, R
"1" is stored in the jackpot flag storage area (not shown) of the AM 41c, the jackpot flag is turned on, and in the second condition device processing (S12), the opening and closing operations of the special winning opening 16 are performed a predetermined number of times. (For example, 15 times or 16 times
Times).

The pachinko machine 1 of the first embodiment has been described in detail above with the main board 41 as an example.
Sub board other than sound board 43, symbol display board 44,
Also in the payout control board 45 and the illumination board 46, the main board 4
As in the case of 1, the signal of the erase switch 42s of the power supply board 42 is transmitted from the signal lines 79b, 79c, 79d, and 79e to the sound board 43, the pattern display board 44, the payout control board 45, respectively.
I / O interfaces 43d and 44 of the illuminated substrate 46
d, 45d, 46d via respective CPUs 43a,
Detected by 44a, 45a, and 46a, the same control as that of the main board 41 is performed. That is, when the power is turned on, FIG.
The same process as the process according to the procedure of the flowchart shown in is performed, and when the erase switch 42s is not pressed (S20: NO), the power recovery process (S26) is performed.

In the flowchart of FIG. 10, S
The processes of 1 to S4 are commonly performed on each substrate, and the processes of S5 to S16 are different for each substrate, and the processes are performed based on a unique flow. For example, in the case of the symbol display board 44, if the command from the main board 41 is stored in the RAM 44c, the process of displaying the symbol on the special symbol display device 8 is performed according to the command. Therefore, for example, if it is displayed on the special symbol display device 8 as "One man", "One man", "One man",
Even after the power is turned on again, the symbols "Imman", "Iman" and "Iman" are displayed again on the special symbol display device 8 based on the memory of the RAM 44c. On the other hand, if the power is turned on again while the erase switch 42s is being pressed (S20: Y
ES), the process of clearing the backup RAM (S24) is performed, and the initial screen is displayed on the special symbol display device 8.

In the case of the payout control board 45, if the erase switch 42s is not pressed (S20: N
O), power recovery processing (S26) is performed, and if the number of prize balls to be paid out is stored in the RAM 45c, the prize balls are paid out based on the memory. On the other hand, the erase switch 42
If the power is turned on again while pressing s (S
20: YES), backup RAM clear (S24)
Is performed, and even if there is a prize ball to be paid out before the power is turned off, it will not be paid out. The same applies to the sound board 43 and the decorative board 46.

Power recovery process (S26) or backup RA
When M clear (S24) is completed, the routine returns to the respective routines of the sound board 43, the pattern display board 44, the payout control board 45, and the illumination board 46, and normal processing whose details are not shown is continued. In the case of normal processing, backup RA
When the M clear (S24) is being executed, the same judgment as the judgment (S3) as to whether the RAM check of FIG. 10 is normal is made, and the RAMs 43c, 44c, 45c and 46c of FIG.
The same initial setting as in the power-on initial setting process (S4) of 0 is performed.

In the pachinko machine 1 of the first embodiment, the case has been described in which the power is turned on while pressing the erase switch 42s when the power is turned on. However, even if the erase switch 42s is pressed after the power is turned on (S20: YES), the backup RAM clear process (S24) is performed. Therefore, if power is supplied to the pachinko machine 1, the RAM 41c and the like can be cleared at any time.

Next, with reference to FIG. 12, the RAM erase instruction timing notification processing will be described. FIG. 12 shows RA
9 is a flowchart of an M erasing instruction timing notification process. In the RAM erasing instruction timing notification process, the clerk at the game arcade is informed of the timing of pressing the erasing switch 42s after the power is turned on. This is because there is a timing at which the signal is not accepted even if the erasing switch 42s is pressed immediately after the power is turned on. Therefore, in order to avoid it, the clerk at the game hall usually presses the erasing switch 42s for a long time. become. In order to avoid this, the RAM erasing instruction timing notification process described below is performed.

In the RAM erase instruction timing notification process, first, when the power is turned on, the RAM erase instruction timing notification is performed (S50). In the RAM erasing instruction timing notification (S50), specifically, the timing to start pressing the erasing switch 42s immediately after the power is turned on in order to instruct to clear the stored content of the RAM 41c that has been backed up by software, Notification is performed using the notification means shown in FIGS. 7 to 9. For example, if the timing to start pressing the erasing switch 42s after turning on the power is 3 seconds, in the case of the 7-segment LED 41f1 shown in FIG. 7, "3", "2", "1", "0" and 1 second. Displays a number that counts down each time.

When the liquid crystal display device 41f2 shown in FIG. 8 is used, for example, the erase switch 4 is turned on after the power is turned on.
If the time to press 2s is 3 seconds later, bar 41
Change the color of f21 in order from the end in 3 seconds.
When using the display device 41f3 shown in FIG. 9,
For example, if the timing at which the erasing switch 42s should be pressed after the power is turned on is 3 seconds later, the LEDs 41f31 are sequentially turned on in 3 seconds from the end.

Further, when the RAM erasing instruction timing is notified by the voicing means, the CPU 4 on the main board 41 is used.
A signal for designating a pattern to be uttered by the speaker 61 is sent from 1a to the sound substrate 43. On the sound board 43, the voice information according to the pattern is read from the ROM 43b and is uttered from the speaker 61 via the drive circuit. For example, if the timing to press the erasing switch 42s after the power is turned on is 3 seconds later, a sound such as "Sun", "Nii", "Ichi", "Zero" is emitted at intervals of 1 second, or "3 more
Seconds. "," 2 seconds left. "" 1 second left. ",
Speak "Please press."

The staff at the game hall does not press the erasing switch 42s until the RAM erasing instruction timing notification (S50) is completed, and the RAM erasing instruction timing notification (S5).
When 0) is completed, the erase switch 42s is pressed (S5
2: YES). Then, the backup RAM clear process is performed (S54). Incidentally, if the erasing switch 42s is not pressed within the predetermined time (S52: NO). Power recovery processing is performed (S56). Therefore, the clerk of the game arcade does not continue to press the erasing switch 42s earlier than necessary.

A second embodiment, which is a modification of the present invention, will be described with reference to FIG. FIG. 6 is a block diagram showing a modified example of the pachinko machine 1, which includes a main board 41, a power supply board 42, a sound board 43, a symbol display board 44, and a payout control board 4.
FIG. 5 is a diagram illustrating the supply of power supply current between the decorative board 46 and the flow of signals. Pachinko machine 1 of the first embodiment
In FIG. 5, as shown in FIG. 5, the erasing switch 42s provided on the power supply board 42 is provided with signal lines 79a, 79b, 79.
I of the main board 41, the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46 by c, 79d, and 79e.
/ O interfaces 41d, 43d, 44d, 45
d and 46d, respectively.

On the other hand, in the pachinko machine which is a modified example of the pachinko machine 1, as shown in FIG. 6, the erasing switch 42s arranged on the power supply board 42 has the I / O interface of the main board 41 by the signal line 83a. 41d. Then, the I / O interface 41 of the main board 41
From d, the signal line 83b is connected to the I / O interface 43d of the sound board 43, the signal line 83c is connected to the I / O interface 44d of the symbol display board 44, and the I / O of the payout control board 45 is connected by the signal line 83d. It is connected to the interface 45d and is connected to the I / O interface 46d of the decorative board 46 by the signal line 83e. This point is different. The configuration of the other parts is the same as that of the pachinko machine 1 shown in FIG.

Also in the pachinko machine of the present embodiment, when the power switch 80 is closed, the RAM 41c receives the power supply current of DC + 5V of the power supply substrate 42 and holds the stored contents. Even when the power is cut off or the power supply is interrupted, the V of the one-chip microcomputer provided on the main board 41 is supplied from the backup power supply battery provided on the power supply board 42 through the power supply line 82a.
Since the power supply current is input to the RAM 41c from the BB terminal, the content stored in the RAM 41c is retained as it is.

The main board 41 of the pachinko machine of the present embodiment configured as shown in FIG. 6 also executes the processing of the main routine of the flowchart shown in FIG. 10 in the same manner as described above. Since this processing is the same as that of the pachinko machine 1 of the above-described embodiment, the description thereof will be omitted and the power-on processing (S in FIG.
Details of 1) will be described with reference to the flowchart shown in FIG. FIG. 13 is a subroutine of the power-on process (S1) of the flowchart shown in FIG.

In the flowchart shown in FIG. 13, when it is determined that the erasing switch 42s is not turned on (S
30: NO), that is, when the erasing switch 42s is not pressed, the power recovery process (S) as in the pachinko machine 1 is performed.
36) is performed. The power recovery process (S36) is performed by the CPU 41.
When the power is turned off based on the contents stored in the RAM 41c by reading the contents stored in the RAM 41c that are backed up by a.
The state of the pachinko machine according to the present embodiment is restored to the state before the power is turned off. For example, even if there is a power failure due to an accident during the player's game, if the player is in a big hit state before the power failure, RAM is restored after the power is restored.
Since the jackpot flag stored in 41c is turned on, the game can be continued in the jackpot state again.

Incidentally, the pachinko machine of the present embodiment has already been
If normal processing is being performed, power recovery processing (S36)
, The recovery process is not performed, and the RAM 41 is used as it is.
The processing based on the stored contents of c is continued. When the power recovery process (S36) ends, the process ends as in the pachinko machine 1.

On the other hand, if the erase switch 42s is pressed when the power is turned on, the fact that the erase switch 42s is ON is detected via the I / O interface 41d and the signal line 83a (S30: YES).

Here, the RAM clear command is transmitted (S3
2) is executed by the CPU 41a of the main board 41. In the pachinko machine of the present embodiment, unlike the pachinko machine 1, from the power supply board 42 to the sound board 4 which is a sub board.
3, symbol display board 44, payout control board 45, decorative board 4
No signal is sent directly to the erase switch 42s from the erase switch 42s. Therefore, the fact that the erasing switch 42s is turned on means that the sound substrate 43, the symbol display substrate 44, which is a sub substrate,
The signal line 8 is transmitted from the I / O interface 41d of the main board 41 for transmission to the payout control board 45 and the illumination board 46.
I / O of the sound substrate 43 by 3b, 83c, 83d, and 83e
O interface 43d, I / O of the pattern display board 44
CPUs 43a, 44a, 45 via the interface 44d, the I / O interface 45d of the payout control board 45, and the I / O interface 46d of the decorative board 46.
A RAM clear command is sent to each of a and 46a. The RAM clear command is sent to the CPUs 43a and 44.
R backed up to a, 45a, 46a
This is a command commanding to erase the stored contents of the AMs 43c, 44c, 45c, 46c.

When the RAM clear command is sent (S32), the CPU 41a of the main board 41 informs the time until the stored contents of the RAM 41c, which is backed up next, is cleared (erased) by software. Notification is given (S34).

This RAM clear completion time notification (S34)
Is the RAM 41c that has been backed up.
The time required to clear the stored contents of the software is notified using the notification means shown in FIGS. 7 to 9. For example, if it takes 3 seconds to clear the stored contents of the RAM 41c by software, in the case of the 7-segment LED 41f1 shown in FIG. 7, "3", "2",
"1", "0" and a number that counts down every second is displayed.

When the liquid crystal display device 41f2 shown in FIG. 8 is used, for example, if it takes 3 seconds to clear the stored contents of the RAM 41c by software, the bar 41f21 can be moved from the end in 3 seconds. Try to change colors in order. When the display device 41f3 shown in FIG. 9 is used, for example, if the time taken to clear the stored contents of the RAM 41c by software is 3 seconds, L
The ED 41f31 is sequentially turned on in 3 seconds from the end.

Further, when the RAM clear completion time is notified by the voicing means, the CPU 41a on the main board 41 is used.
A signal designating a pattern produced by the speaker 61 is sent from the sound substrate 43. On the sound board 43, the voice information according to the pattern is read from the ROM 43b and is uttered from the speaker 61 via the drive circuit. For example, R
If it takes 3 seconds to clear the stored contents of the AM 41c by software, it sounds "Sun", "Nii", "Ichi", "Zero" at 1 second intervals, or "RAM".
Only 3 seconds to clear. "It takes 2 seconds to clear the RAM.""It takes 1 second to clear the RAM.",
The voice is said, "RAM cleared."

The RAM clear completion time notification (S34)
Simultaneously with the start of, the CPU 41a executes a backup RAM clear for clearing (erasing) the stored contents of the RAM 41c backed up by software (S38). It should be noted that the clerk at the game arcade 42 erases the switch 42 until the RAM clear completion time notification (S34) ends.
When the RAM clear completion time notification (S34) is completed by continuing to press s, the erase switch 42s is released. Therefore, the staff at the game arcade does not continue to press the erasing switch 42s for more than the required time.

When the backup RAM clear (S38) is completed, the power-on process (S1) of FIG. 10 is completed, and the process proceeds to the next stack pointer set process (FIG. 10: S2).

Next, the RAM erase instruction timing notification process of the pachinko machine equipped with the circuit shown in FIG. 6 will be described with reference to FIG. FIG. 14 is a flowchart of a modified example of the RAM erase instruction timing notification process. This RA
In the M erasing instruction timing notification process, the clerk at the game hall is informed of the timing of pressing the erasing switch 42s after the power is turned on. This is because there is a timing at which the signal is not accepted even if the erasing switch 42s is pressed immediately after the power is turned on. Therefore, in order to avoid it, the clerk at the amusement arcade usually keeps pressing the erasing switch 42s from early on. become. In order to avoid this, the above RA
M erase instruction timing notification processing is performed.

In the RAM erase instruction timing notification process, first, when the power is turned on, the RAM erase instruction timing notification is performed (S60). In the RAM erasing instruction timing notification (S60), specifically, the timing to start pressing the erasing switch 42s immediately after the power is turned on in order to instruct the software to clear the stored contents of the RAM 41c that has been backed up, Notification is performed using the notification means shown in FIGS. 7 to 9. For example, if the timing to start pressing the erasing switch 42s after turning on the power is 3 seconds, in the case of the 7-segment LED 41f1 shown in FIG. 7, "3", "2", "1", "0" and 1 second. Displays a number that counts down each time.

When the liquid crystal display device 41f2 shown in FIG. 8 is used, for example, the erase switch 4 is turned on after the power is turned on.
If the time to press 2s is 3 seconds later, bar 41
Change the color of f21 in order from the end in 3 seconds.
When using the display device 41f3 shown in FIG. 9,
For example, if the timing at which the erasing switch 42s should be pressed after the power is turned on is 3 seconds later, the LEDs 41f31 are sequentially turned on in 3 seconds from the end.

Further, when the RAM erasing instruction timing is notified by the voicing means, the CPU 4 on the main board 41 is used.
A signal for designating a pattern to be uttered by the speaker 61 is sent from 1a to the sound substrate 43. On the sound board 43, the voice information according to the pattern is read from the ROM 43b and is uttered from the speaker 61 via the drive circuit. For example, if the timing to press the erasing switch 42s after the power is turned on is 3 seconds later, a sound such as "Sun", "Nii", "Ichi", "Zero" is emitted at intervals of 1 second, or "3 more
Seconds. "," 2 seconds left. "" 1 second left. ",
Speak "Please press."

It is to be noted that the clerk at the game hall does not press the erase switch 42s until the RAM erase instruction timing notification (S60) is completed, and the RAM erase instruction timing notification (S6).
When 0) is completed, the erase switch 42s is pressed (S6
1: YES). Then, send a RAM clear command (S
62) is executed by the CPU 41a of the main board 41.
In the pachinko machine of the present embodiment, unlike the pachinko machine 1, from the power supply board 42 to the sound board 4 which is a sub board.
3, symbol display board 44, payout control board 45, decorative board 4
No signal is sent directly to the erase switch 42s from the erase switch 42s. Therefore, the fact that the erasing switch 42s is turned on means that the sound substrate 43, the symbol display substrate 44, which is a sub substrate,
The signal line 8 is transmitted from the I / O interface 41d of the main board 41 for transmission to the payout control board 45 and the illumination board 46.
I / O of the sound substrate 43 by 3b, 83c, 83d, and 83e
O interface 43d, I / O of the pattern display board 44
CPUs 43a, 44a, 45 through the interface 44d, the I / O interface 45d of the payout control board 45, and the I / O interface 46d of the decorative board 46.
A RAM clear command is sent to each of a and 46a. The RAM clear command is sent to the CPUs 43a and 44.
R backed up to a, 45a, 46a
This is a command commanding to erase the stored contents of the AMs 43c, 44c, 45c, 46c.

When the RAM clear command transmission (S62) is completed, the RAM 41 which is backed up next
A backup RAM clear is executed to clear (erase) the stored contents of c by software (S64). When the backup RAM clear (S64) is completed, the power-on process (S1) of FIG. 10 is completed, and the process proceeds to the next stack pointer set process (FIG. 10: S2). If the erasing switch 42s is not pressed within the predetermined time (S6
1: NO). Power recovery processing is performed (S66).

Therefore, the clerk at the game arcade does not continue to press the erasing switch 42s earlier than necessary.

Further, although not shown, a backup means which does not include a sub-board and which supplies backup power to the RAM 41c of the main board 41 from the backup power supply provided on the power board 42 to back up only the RAM 41c, A pachinko machine having a delete switch 42s that is operated to delete the stored contents of the RAM 41c, and is configured to delete only the stored contents of the RAM 41c by backing up the RAM 41c and pressing the delete switch 42s. You can also

Although the gaming machine has been described by taking the first-class pachinko machine as an example, not only the first-class pachinko machine but also various types of pachinko machines may be used, such as slot machines, pachi-con machines, pachi-slot machines, and the like. Needless to say, the present invention can be applied to various types of gaming machines controlled by the main board.

Furthermore, the present invention is not limited to the above-mentioned embodiment, and various modifications can be made. For example, the erasing of the memory contents of the RAM is not necessarily limited to erasing by the software control, and the supply of power for holding the memory contents of the RAM may be directly stopped by a switch.

[0118]

As described above, in the gaming machine of the invention according to claim 1, the control board controls the gaming machine, the power supply board supplies power to the control board, and from the power supply board to the control board. When the power supply to the volatile memory is stopped, the backup means can supply power to the volatile memory provided on the control board to hold the stored content so that the stored content of the volatile memory is not erased. When the erasing instruction means instructs the erasing content of the volatile memory by the erasing content erasing means, the erasing content erasing means erases the memorized content of the volatile memory supplied with power for holding the memorized content by the backup means. However, the erasing time notifying means can notify the time until the erasing of the stored content of the volatile memory by the stored content erasing means is completed.

In addition to the effect of the invention according to claim 1, the gaming machine of the invention according to claim 2 erases the contents stored in a volatile memory by using a liquid crystal display device as the erase time notification means. The time until completion can be notified.

The gaming machine of the invention according to claim 3 is the gaming machine according to claim 1.
In addition to the effect of the invention described in (1), it is possible to notify the time until the erasing of the stored contents of the volatile memory is completed by using a 7-segment LED as the erasing time notifying means.

Further, in the gaming machine of the invention according to claim 4,
In addition to the effect of the invention according to claim 1, a plurality of LEDs are provided as the erasing time notification means, and the plurality of LEDs are provided.
Can be turned on or off sequentially to notify the time until the erasing of the stored contents of the volatile memory is completed.

Further, in the gaming machine of the invention according to claim 5,
In addition to the effect of the invention according to any one of claims 1 to 4, the erasing time notification means is a sounding means, and a sound is emitted from the sounding means until the erasing of the stored contents of the volatile memory is completed. The time can be notified.

Further, in the gaming machine of the invention according to claim 6,
The control board controls the game machine, the power supply board supplies power to the control board, and when the power supply from the power supply board to the control board is stopped, the backup means stores the contents stored in the volatile memory provided in the control board. A holding power can be supplied to hold the stored contents of the volatile memory so as not to be erased. When the erasing instruction means instructs the erasing content of the volatile memory by the erasing content erasing means, the erasing content erasing means erases the memorized content of the volatile memory supplied with the power for holding the stored content by the backup means However, the erasing timing notifying means can notify the timing of instructing the erasing of the contents stored in the volatile memory by the erasing instruction means.

Further, in addition to the effect of the invention described in claim 6, the gaming machine of the invention according to claim 7 gives an instruction to erase the contents stored in the volatile memory by a liquid crystal display device as an erase timing notifying means. It is possible to notify the timing to do.

Further, in addition to the effect of the invention described in claim 6, the gaming machine of the invention according to claim 8 uses a 7-segment LED as an erasing timing notifying means to store the contents stored in the volatile memory. The timing for instructing erasure can be notified.

Further, in the gaming machine of the invention according to claim 9,
In addition to the effect of the invention according to claim 6, a plurality of LEDs as an erasing time informing means are provided, and the timing for instructing erasing of the stored content of the volatile memory by sequentially turning on or off the plurality of LEDs is set. Can inform.

Further, in the gaming machine of the invention according to claim 10, in addition to the effect of the invention according to any one of claims 6 to 9, in addition to the effect of the invention according to claim 6, sound is emitted from the sounding means as the erasing timing notifying means, The timing for instructing to erase the stored contents can be notified.

Further, in addition to the effects of the invention according to any one of claims 1 to 10, in the gaming machine of the invention according to claim 11, a push button is operated as an erasing instruction means, and the stored contents of the volatile memory. Can be instructed to be erased.

[Brief description of drawings]

FIG. 1 is a front view of a pachinko machine 1.

FIG. 2 is a front view of a game board 2 of the pachinko machine 1.

FIG. 3 is a front view of a special symbol display device 8.

FIG. 4 is a block diagram showing an electric circuit configuration of the pachinko machine 1.

FIG. 5 is a diagram showing the supply of power supply current and the flow of signals between the main board 41, the power supply board 42, the sound board 43, the pattern display board 44, the payout control board 45, and the decorative board 46 in the pachinko machine 1. It is a figure explaining.

FIG. 6 is a main substrate 4 of a modified pachinko machine.
1, supply of power supply current between the power supply board 42, the sound board 43, the symbol display board 44, the payout control board 45, and the decorative board 46,
It is a figure explaining the flow of a signal.

FIG. 7 is a perspective view of a 7-segment LED 41f1.

FIG. 8 is a front view of a liquid crystal display device 41f2.

FIG. 9 is a front view of a display device 41f3 provided with a plurality of LEDs 41f31.

FIG. 10 is a flowchart showing a main routine of the pachinko machine 1.

11 is a flowchart showing in detail a procedure of power-on processing (S1) of the flowchart shown in FIG.

FIG. 12 is a flowchart showing in detail a procedure of power-on processing of the main board 41 in the pachinko machine of the modified example.

FIG. 13 is a flowchart showing in detail the procedure of power-on processing of the main board 41 in the pachinko machine of the modified example.

FIG. 14 is a flowchart showing in detail the procedure of power-on processing of the main board 41 in the pachinko machine of the modified example.

[Explanation of symbols]

1 Pachinko machine 2 Game board 4 Game area 8 Special symbol display device 24 Normal symbol display device 41 Main board 42 Power supply board 43 Sound board 44 Symbol display board 45 Discharge control board 46 Illumination boards 41a, 43a, 44a, 45a, 46a CPU 41b, 43b, 44b, 45b, 46b ROM 41c, 43c, 44c, 45c, 46c RAM 41d, 43d, 44d, 45d, 46d I / O interface 41f notification means 42s erase switch 61 speaker 77, 78, 79a, 79b, 79c , 79d, 79
e, 83a, 83b, 83c, 83d, 83e Signal line 80 Power switch 82a, 82b, 82c, 82d, 82e Power supply line

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroshi Nogawa             3-12 Nagatoi-cho, Nakamura-ku, Nagoya-shi, Aichi             Chi Toyomaru Sangyo Co., Ltd. F term (reference) 2C088 BC08 BC23 DA23 EA10

Claims (11)

[Claims] 1. A control board for controlling a gaming machine, a power supply board for supplying power to the control board, and when power supply from the power supply board to the control board is stopped,
Backup means for supplying power for holding stored contents to the volatile memory provided on the control board to prevent the stored contents of the volatile memory from being erased; and power for holding stored contents by the backup means Stored content erasing means for erasing the stored content of the volatile memory, erasing instruction means for instructing the stored content erasing means to erase the stored content of the volatile memory, and volatile by the stored content erasing means. A gaming machine comprising: an erasing time informing means for informing a time until the erasing of the stored contents of the memory is completed. 2. The gaming machine according to claim 1, wherein a liquid crystal display device is used as the erase time notification means. 3. The gaming machine according to claim 1, wherein a 7-segment LED is used as the erase time notification means. 4. A plurality of Ls are provided as the erase time notification means.
The gaming machine according to claim 1, wherein an ED is provided and the plurality of LEDs are sequentially turned on or off to notify the time until the erasing of the stored contents of the volatile memory is completed. 5. The erasing time notification means is a sounding means, and sounds a sound from the sounding means to notify the time until the erasing of the contents stored in the volatile memory is completed. The gaming machine according to any one of 1 to 4. 6. A control board for controlling a gaming machine, a power supply board for supplying power to the control board, and a stop of power supply from the power supply board to the control board.
Backup means for supplying power for holding stored contents to the volatile memory provided on the control board to prevent the stored contents of the volatile memory from being erased; and power for holding stored contents by the backup means Stored content erasing means for erasing the stored content of the volatile memory, erasing instruction means for instructing erasing of the stored content of the volatile memory by the stored content erasing means, and the volatile memory by the erasing instruction means And an erasing timing informing means for informing a timing of instructing erasing of the stored contents of the gaming machine. 7. The gaming machine according to claim 6, wherein a liquid crystal display device is used as the erasing timing informing means. 8. The erasing timing informing means includes 7
7. The segment LED is used.
Gaming machine described in. 9. The erasing timing notifying means is provided with a plurality of LEDs, and the plurality of LEDs are sequentially turned on or off to notify a timing of instructing erasing of stored contents of the volatile memory. The gaming machine according to claim 6. 10. The erasing timing notification means is a sounding means, and sounds a sound from the sounding means to notify a timing for instructing deletion of the stored contents of the volatile memory. 9. The gaming machine according to any one of 9. 11. The gaming machine according to claim 1, wherein the erasing instruction means is a push button.