JP2007319608A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce work burdens of a clear switch operator when erasing backed-up stored contents in a storage device of a control means for controlling a game machine by a clear switch. <P>SOLUTION: When a main control board 44 and a lamp control board 37 are activated, by setting a standby time counter or the like by software as delay processing after executing the program of actual initialization or the like, the apparent end time of the program processing of the initialization or the like is delayed for prescribed time. The lamp control board 37 sets delay time shorter than that of the main control board 44, and at the point of time that the delay time elapses, a CPU 70 counts down an displays the timing of pressing a RAM clear switch 60 on a 7-segment LED 75. Thus, even in the game machine wherein it takes long time to activate the main control board 44, the time and labor of pressing the RAM clear switch 60 for a long period of time are eliminated. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a gaming machine such as a pachinko machine, and in particular, it can back up the storage contents of the storage device of the control means for controlling the gaming machine even when the power is cut off, and forcibly stores the storage contents of the backed up storage device. The present invention relates to a gaming machine provided with a memory erasing means for erasing and initializing.

  Conventionally, a gaming machine such as a pachinko machine has a main control board for mainly executing game contents and a plurality of sub-types for auxiliary execution of game contents in accordance with instructions (commands) from the main control board. A control board is provided. In addition to the payout control board for controlling the payout of game balls, the sub-control board controls a display control board for controlling a display device such as a liquid crystal for performing a symbol matching game (slot game), and lighting modes of lamps, LEDs, and the like. There are a lamp control board and a sound control board for generating desired music or voice from a speaker or the like. Note that these control boards are equipped with a microcomputer centering on a CPU, ROM, RAM, and the like.

  By the way, in recent years, when a power supply voltage supplied to a gaming machine is shut off at the time of closing or a power failure, the gaming information is stored in a storage device such as a RAM (hereinafter also simply referred to as RAM). ) Is provided with a backup function for storing and holding. According to this backup function, the game can be resumed from the state immediately before the power supply voltage is cut off based on the game information stored and retained in the RAM after the power is restored. It becomes possible to prevent the disadvantage to the player.

  However, on the other hand, there is a case where the RAM is initialized by deleting the game information stored and held by the backup function. In such a case, for example, if the probability of hitting the game hits the previous day with a high probability state, the store closes, and the next day when the store opens, the game starts in a high probability state, or when the gaming machine is shipped from the factory. Etc. are considered. In the former case, if the game is started with a high probability from the opening of the store, the game store will suffer a disadvantage, and in the latter case, the state of the gaming machine is surely set to the initial state. Because I want to make it.

Therefore, a technology has been proposed in which a gaming machine equipped with such a backup function is provided with a clear switch that forcibly erases and initializes the stored contents of the RAM backed up at the time of opening the store. In this technology, the stored contents of the backed-up RAM are erased by turning on the power switch (hereinafter also referred to as “power-on”) while the clear switch is continuously turned on when the store is opened. Thus, inadvertent initialization of the RAM due to an erroneous operation of the clear switch is also prevented (see, for example, Patent Document 1, hereinafter referred to as the prior art).
JP 2001-346945 A

  However, in recent gaming machines, the performance of sub-control boards such as liquid crystal display devices has been improved in order to improve the appeal of gaming effects, and all of the sub-control boards start up when the power is turned on. Is longer (for example, around 10 seconds). As described above, each sub control board operates in accordance with a command from the main control board. Therefore, after the power is turned on, the main control board ensures that each sub control board can receive the first command from the main control board. Is activated after all the sub-control boards are up.

  In this text, “start up” means the time when the CPU finishes the program processing such as initial setting at the time of power recovery such as when various control boards are turned on or when a power failure is restored and restored. The sub control board is in a state where it can receive commands from the main control board. On the other hand, the “startup” means that the CPU is initialized when power is restored to the various control boards, such as when the power is turned on or power is restored. This is the time when program processing such as setting is started. In this state, the sub-control board cannot receive a command from the main control board.

  However, in the above prior art, when the RAM of the main control board is initialized by the clear switch, the clear switch must be kept on at least from when the power is turned on until the main control board is activated. As described above, in the gaming machine with the high performance of the sub control board, when the RAM of the main control board is initialized, the troublesome work of continuing to turn on the clear switch for a long time is required. In particular, at the time of opening a store in which a considerable number of gaming machine RAMs must be initialized, there are many other preparations, and the burden on the store clerk is increased.

  The present invention has been made to solve such a problem, and the object of the present invention is to erase the storage contents of the storage device of the control means for controlling the backed up gaming machine with a clear switch. An object of the present invention is to provide a gaming machine that can reduce the work burden on a person who operates a clear switch.

  In order to solve such a problem, the gaming machine according to the present invention includes a main control means for controlling a game and various gaming devices based on a command signal from the main control means as described in claim 1. Sub-control means for controlling the power supply, power supply means for generating and supplying predetermined operating power to the main control means and the sub-control means, and at the start of power supply from the power supply means, the main control means is connected to the sub-control means. A delay means for starting up later than the control means; a storage means for storing game information relating to game control of the main control means; and when the power supply from the power supply means is cut off, Backup power supply means for supplying power, a clear switch for outputting a clear signal to the main control means by turning on, and the clear signal is input when the main control means is activated And a memory erasure unit for erasing the game information stored in the storage unit, information relating to timing for turning on the clear switch is transmitted to a predetermined notification device. Informing control means comprising a microcomputer or the like for informing, the informing control means for the start time of the program processing executed after the end of the initial setting at the start of power supply until a predetermined time before the main control means starts up A notification control delay processing unit configured to delay by executing a predetermined program process, wherein the notification control unit is configured to switch the clear switch to the notification device when a predetermined program process executed by the notification control delay processing unit ends; It is characterized in that information relating to the timing of turning on is notified.

  The gaming machine according to claim 2 is the gaming machine according to claim 1, characterized in that the clear switch is a push button type which is turned on only while being pressed.

  The gaming machine according to claim 3 is the gaming machine according to claim 1 or 2, wherein each of the main control means and the sub-control means includes a microcomputer, and the delay means supplies power. Main control delay processing means for delaying the start timing of the program processing executed after completion of the initial setting in the main control means at the start by executing the predetermined program processing until a predetermined time elapses after the sub control means is started up The notification control means notifies the information related to the timing for turning on the clear switch when the predetermined program processing executed by the notification control delay processing means is completed. And

  According to a fourth aspect of the present invention, there is provided a gaming machine according to the third aspect, further comprising a game medium payout device for paying out a game medium to a player, wherein the sub-control means includes the game medium payout device. A payout control means for controlling the payout control means, the payout control means comprising a payout storage means for storing information relating to payout control, and the backup power supply means when the power supply from the power supply means is interrupted, Backup power is also supplied to the payout storage means, and the predetermined program processing executed by the main control delay processing means is a process for checking the number of game media paid out from the game medium payout device. It is characterized by that.

A gaming machine according to claim 5 is characterized in that, in the gaming machine according to claim 3 or 4, the notification control means is the sub-control means.
The gaming machine according to claim 6 is the gaming machine according to any one of claims 1 to 5, wherein the notification device is a display device and / or a sound device, and the notification control means includes: The display device and / or the audio device is notified in a predetermined notification mode of the timing for turning on the clear switch.

  The gaming machine according to claim 7 is the gaming machine according to claim 6, wherein a plurality of the notification modes are provided in advance, and a selection unit that can select a desired notification mode from the plurality of notification modes is provided. It is characterized by that.

  Further, the gaming machine according to claim 8 is the gaming machine according to any one of claims 1 to 7, wherein the gaming information stored in the storage means is erased by the memory erasing means. The main control means outputs a clear completion signal to the notification control means. When the notification control means inputs the clear success signal, the game information stored in the storage means is erased. The notification device is notified of the fact.

  In the first aspect of the invention, the main control means controls the game, and the sub-control means controls various game devices based on a command signal (for example, a strobe signal or a command signal) from the main control means. For example, when the gaming machine is a pachinko machine, examples of the various gaming devices include a display device, a ball payout device, a ball hitting device, an electric accessory, a light emitting device, a sound device, and the like.

  When supply of predetermined operating power from the power supply means to the main control means and the sub control means is started (for example, when the power switch is turned on or when the power failure is restored), the main control means is connected to the sub control means by the delay means. The sub-control unit can reliably receive the command signal from the main control unit. That is, when the supply of power is started, the sub control means can reliably receive the first command signal from the main control means, and therefore the sub control means misses the command signal from the main control means. There is nothing.

  When there are a plurality of sub-control means, the timing for starting the main control means is the time until the command signal from the main control means can be received, that is, the time from when the supply of power is started until it starts. It is set for the slowest sub-control means. For example, in a recent pachinko machine, the slowest time to start up is the sub-control means that controls the display device. In this case, the time for the main control means to start up after the supply of power is started is Some models are set to 10 seconds or more.

  Here, the main control means stores game information related to game control in the storage means, and this storage means is used when the power supply from the power supply means is interrupted (for example, the power switch is turned off). When a power failure occurs or when a power failure occurs, backup power is supplied by backup power supply means. That is, the storage means of the main control means is backed up and the stored contents are held when the power supply is cut off.

  Also, when it is desired to erase the game information stored in the storage means, the clear signal is output to the main control means by turning on the clear switch. The game information stored in the storage means is erased based on the fact that the clear signal is input when the player stands up. That is, if the clear switch is turned on when the supply of power is started and the main control unit starts up, the stored contents of the storage unit are erased.

  In such a configuration, the gaming machine according to the present invention includes notification control means including a microcomputer centered on a CPU, ROM, RAM, and the like, and the notification control means turns on the clear switch. The information concerning is notified to a predetermined notification device.

  Here, the notification control means includes notification control delay processing means, and the notification control delay processing means sets the start timing of the program processing to be executed after completion of the initial setting at the start of power supply, for a predetermined time before the main control means starts up. Until a predetermined program process is executed. In other words, the notification control delay processing means delays the start time of the program processing that is originally executed after the end of the initial setting by executing a predetermined program process after the end of the initial setting at the start of power supply. The delay processing performed by the notification control delay processing means, that is, the predetermined program processing is executed until a predetermined time before the main control means starts up.

  In other words, apparently the end time of the initial setting is delayed, that is, the notification control means starts up when the delay processing performed by the notification control delay processing means ends. The time when the notification control means starts up is a predetermined time before the main control means starts up. Various predetermined program processing as delay processing performed by the notification control delay processing means is conceivable, for example, processing for setting a value corresponding to the delay time in a general-purpose register and decrementing the value of the register by −1 (decrement) And the like are repeated until the value of the register becomes zero.

  Then, when the predetermined program process as the delay process executed by the notification control delay processing unit is completed, the notification control unit notifies the notification device of information related to the timing for turning on the clear switch. That is, the notification device relates to the timing of turning on the clear switch a predetermined time before the main control means starts up so that the clear switch is turned on when the power supply is started and the main control means starts up. Broadcast information.

  According to the invention of claim 1 having the above-described configuration, when the stored contents of the storage means being backed up are erased by turning on the clear switch, the operator of the clear switch is cleared by notification from the notification device. The timing for turning on the switch can be known, and as a result, the clear switch can be appropriately operated. As a result, the stored contents of the storage means being backed up can be surely erased.

  In addition, since the execution time of the predetermined program processing as the delay processing by software can be easily changed, that is, the notification timing of the information related to the timing of turning on the clear switch from the notification device is a simple program. Since it can be easily executed by modification, it is extremely convenient.

  In addition, since the delay processing is executed by software program processing, hardware resources (for example, a delay circuit) for performing the delay processing become unnecessary, making it easy for the developer to design the circuit and reducing the cost. Is peeled off. Further, since hardware resources are not required, the space that can be used for gaming machines increases accordingly, and as a result, the limited space of gaming machines can be used effectively.

  The gaming machine according to claim 2 is the gaming machine according to claim 1, wherein the clear switch is a push button type (return type) that is turned on only while being pressed. Clearing the stored contents of the storage means that the state of the gaming machine will return to the initial state at that time. Therefore, if the clear switch is turned on / off, the state that maintains that state (momentary type) is used. This increases the probability that the stored contents of the storage means will be inadvertently deleted.

  On the other hand, if the clear switch is a return type, inadvertent misoperation is reduced, but on the other hand, the clear signal is not sent unless the clear switch is kept pressed, and therefore the stored contents of the storage means are cleared. Work becomes complicated. In particular, if the time from when the power supply is started until the main control means starts up is long, conventionally the return type clear switch does not know when the main control means starts up. It must be kept pressed for a long time from the start of supply until the main control means is confirmed to rise.

  However, according to the present invention, the notification of the notification device allows the operator of the clear switch to know the timing for turning on the clear switch. Therefore, even if the time from the start of power supply to the start of the main control means is long, it is possible to save the trouble of having to keep pressing the clear switch for a long time. Even if it is a return type, the operation time is shortened and workability is improved. That is, according to the present invention, when the stored contents of the storage means are cleared, there is an extremely remarkable effect that workability is improved while preventing inadvertent misoperation.

  Further, the gaming machine according to claim 3 is the gaming machine according to claim 1 or 2, wherein the main control means and the secondary control means are each a microcomputer centering on a CPU, ROM, RAM, etc. I have. When the power supply from the power supply means is started, the delay means that starts up the main control means later than the sub-control means is used as the main control delay processing means. The start timing of the program processing to be executed after completion of the setting is started by delaying the main control means by a predetermined time from the sub control means by executing the predetermined program processing until a predetermined time elapses after the sub control means starts up. .

  That is, the main control means, like the notification control means, sets the start timing of the program processing to be executed after completion of the initial setting at the start of power supply after the sub-control means has started up by executing the predetermined program processing. Delayed until time has passed. In other words, the initial setting end time is apparently delayed, that is, the main control means is delayed by a predetermined time from the sub control means when the delay processing performed by the main control delay processing means is completed. Will stand up. The predetermined program processing as the delay processing performed by the main control delay processing means is the same as the predetermined program processing as the delay processing performed by the notification control delay processing means. When the predetermined program processing executed by the notification control delay processing unit is completed, the notification control unit notifies the information related to the timing at which the notification device turns on the clear switch.

  According to the invention of claim 3 having such a configuration, the notification control means is notified based on software program processing as delay processing executed by the notification control delay processing means having the same configuration as the main control delay processing means. Since the information related to the timing of turning on the clear switch is notified to the device, that is, the notification control means determines the delay time by the delay processing means having the same configuration as the main control means. The clear switch ON operation timing to be notified can be executed with high accuracy and almost no error.

  According to a fourth aspect of the present invention, there is provided a gaming machine according to the third aspect, further comprising a game medium payout device for paying out game media to the player. The game media is paid out. For example, when the gaming machine is a pachinko machine, the gaming medium is a pachinko ball, and the pachinko ball is paid out from the payout device as a reward for the game or based on the insertion of money.

  Here, the payout control means for controlling the game medium payout device is one of the sub-control means that operates based on the command signal from the main control means, that is, the payout control means is based on the command signal from the main control means. To control the game medium payout device. The payout control means includes payout storage means for storing information relating to payout control. This payout storage means is similar to the storage means of the main control means when the power supply from the power supply means is interrupted. (For example, when a power switch is turned off or when a power failure occurs), backup power is supplied by backup power supply means. That is, in the gaming machine of the present invention, the storage means of the main control means and the payout storage means of the payout control means are both backed up and the stored contents are retained when the power supply is cut off. Yes.

  In such a configuration, in the gaming machine of the present invention, the predetermined program processing as delay processing executed by the main control delay processing means is processing for checking the number of game media paid out from the game media payout device. Yes. That is, the main control means repeatedly executes the process of checking the number of game media paid out from the game medium payout device for the start timing of the program processing executed after the end of the initial setting at the start of power supply. By creating this, a delay is made until a predetermined time elapses after the sub-control means starts up.

  According to the invention of claim 4 having such a configuration, before the main control means starts up, the payout control means as the sub control means starts up, and is based on the unpaid total payout ball number stored in the payout storage means. Even if the game medium payout device has paid out the game medium, the main control means can grasp the exact number of unpaid balls, so that the main control means It is possible to execute appropriately without causing any disadvantage to both players. That is, both the storage means of the main control means and the payout storage means of the payout control means are backed up together and the stored contents are maintained, and the number of unpaid payout balls is properly managed, for example, power failure, etc. Even when the power is shut off at the time, when the supply of power is resumed, the gaming state can be returned to a state closer to the state before the power is shut off. As a result, both the game arcade and the player It can be prevented from suffering disadvantages.

  The gaming machine according to claim 5 is the gaming machine according to any one of claims 1 to 4, wherein the notification control means is sub-control means. The sub-control means is an essential configuration originally provided in the gaming machine. That is, in the present invention, the existing sub-control means is used to notify information related to the timing of turning on the clear switch. It has become. Therefore, according to the invention of claim 5 having such a configuration, it is not necessary to add new notification control means to the gaming machine, thereby simplifying the configuration of the gaming machine and reducing the cost, and limiting the gaming machine. This makes it possible to effectively use the space.

  The gaming machine according to claim 6 is the gaming machine according to any one of claims 1 to 5, wherein the notification control means sets a clear switch on the display device and / or the sound device as the notification device. The timing to turn on is notified in a predetermined notification mode. Here, the predetermined notification mode includes, for example, a countdown or countup display, a voice, and the like, and the operator of the clear switch may turn on the clear switch according to the display device and / or the voice device. That's fine.

  For example, if the time from the start of power supply to the start of the main control means is 10 seconds, information on the timing for turning on the clear switch starts 5 seconds after the start of power supply, and then countdown, countup, etc. The notification may be performed until the time when the main control means rises. This further facilitates the operation of the clear switch. In other words, the operator of the clear switch can execute without fail at the timing when the clear switch is turned on. As the display device and / or the audio device, an existing device may be used, or a new device may be provided.

  The gaming machine according to claim 7 is the gaming machine according to claim 6, wherein a plurality of notification modes are provided in advance, and a selection unit selects a desired notification mode from the plurality of notification modes provided. To do. For example, the notification mode can be changed according to preference, such as a change from countdown notification to countup. If a plurality of types of devices (for example, a display device and an audio device) are provided as notification devices, it is possible to select whether to notify all notification devices or to notify a specific notification device. Good.

  Further, in the gaming machine according to claim 8, in the gaming machine according to any one of claims 1 to 7, the main control means stores the memory means by the memory erasing means based on the ON operation of the clear switch. When the game information that has been erased is erased, a clear completion signal is output to the notification control means. When the clearing signal is input, the notification control means notifies the notification device that the game information stored in the storage means has been deleted.

  Accordingly, the operator of the clear switch may turn off the clear switch when the notification device notifies that the game information stored in the storage means has been deleted. That is, according to the present invention, when the operator of the clear switch performs the operation of erasing the stored contents of the storage means being backed up by operating the clear switch, the clear switch is turned on and the clear switch is turned off. Both the operation timings can be known, thereby significantly reducing the operation time of the clear switch and reducing the work burden on the clear switch operator.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is an overall front view of the gaming machine 1. As shown in FIG. 1, the gaming machine 1 according to the present embodiment includes an outer frame 22 fixed to a game island (not shown) and an inner frame 23 attached to the outer frame 22 so as to be opened and closed. The inner frame 23 includes a game board 21 that provides a player with a pachinko game, a hitting operation handle 2 that operates a hitting ball launching device 43 that is described later when operated by the player, and a game launched by the hitting ball launching device 43. A ball guide rail 3 for guiding a ball, a game region forming rail 4 provided so that the launched game ball flies within a certain range, and a game region surrounded by the ball guide rail 3 and the game region forming rail 4 5 and a return ball which is attached to the tip of the game area forming rail 4 and prevents the game ball launched into the game area 5 from returning to the firing path between the hit ball guiding rail 3 and the game area forming rail 4. A liquid crystal display that performs a stop valve 24, a windmill 20 that changes the game ball launched into the game area 5 in an unexpected direction, and a pseudo display (hereinafter also referred to as scroll display) showing a special symbol rotating. A special symbol display device 6 composed of a display (LCD) or the like, a start winning opening (electric tulip) 11 that causes the special symbol display device 6 to start scroll display of the special symbol when the game ball wins, and a special symbol display When the device 6 wins the start winning slot 11 while the device 6 is scrolling the special symbol, the player is informed of how many times the scroll display is to be changed (usually up to four times). Four hold LEDs 25 for sequentially displaying the hold memory for lighting, and the left symbol for individually displaying three special symbols in the image display unit of the special symbol display device 6 Large winning opening that is advantageously opened to the player when the display results in the display unit 8, the middle symbol display unit 9, the right symbol display unit 10 and the special symbol display device 6 are in a predetermined mode (big hit). (Attacker) 7, a hitting ball supply tray 12 for supplying game balls to the hitting ball launcher 43, and a ball that does not fit in the hitting ball supply tray 12 can be stored, and a game ball is stored in a storage ball box (not shown) A surplus ball tray 13 that can be moved, a normal winning slot 14 where a prize ball is paid out by winning a prize, a payout of a prize ball for a prize, a ball clogging, an abnormality, etc. are notified, or a gaming state is predetermined. A game effect lamp 15 that flashes when a state (for example, a big hit) is achieved to enhance a production effect, an out port 16 that collects game balls provided at the bottom of the game area 5, and an inner frame 23 that can be opened and closed freely Provided in When the glass door frame 17 and a single-digit ordinary symbol are displayed and the ordinary symbol is a predetermined ordinary symbol (winning), a 7-segment LED or the like that opens the blade of the electric tulip as the start winning opening 11 The normal symbol display device 18 configured, the normal symbol operation gate 19 that causes the normal symbol display device 18 to start the normal symbol variation display when the game ball passes, and the normal symbol display device 18 is displaying the normal symbol variation display. When the game ball passes through the normal symbol operation gate 19, the display of the hold memory for informing the player of how many times to display the change (usually up to 4 times) after the change display ends. It is comprised by four hold | maintenance LED26 etc. which are performed sequentially.

  In the gaming machine 1 configured as described above, first, a game ball is launched from the hit ball launching device 43 by the operation of the hitting operation handle 2 of the player, and passes between the hit ball guiding rail 3 and the game area forming rail 4. A game ball is launched into the game area 5 on the game board 21. Then, the game ball falls in the game area 5 by its own weight, and in the process of falling, the game ball 21 is changed in the direction of dropping by a game nail or a windmill 20 (not shown) implanted in the game board 21, In the case where the normal winning opening 14 is won, the normal symbol operating gate 19 is passed, or all the winning holes are not won, the prize is collected at the out opening 16.

  When a game ball wins the start winning opening 11, a predetermined prize ball is given to the player, and the game ball is detected by a start winning detection sensor 116 described later, and each symbol display unit 8 of the special symbol display device 6 is detected. , 9, 10 are displayed in a scrolled manner, and after a predetermined time, a slot game is performed in which a special symbol is stopped in the order of the left symbol display unit 8, the right symbol display unit 10, and the middle symbol display unit 9, and a lottery is performed. When the special symbol of the part 8 and the special symbol of the right symbol display part 10 are stopped, a combination of special symbols constituting a big hit (for example, the special symbol of the left symbol display part 8 and the special symbol of the right symbol display part 10 are The special symbol display device 6 displays a predetermined reach action, and after that, the special symbol on the middle symbol display unit 9 is stopped. If the displayed special symbol is a combination of predetermined special symbols, it will be a big hit, and the attacker as the big prize opening 7 will be opened in a predetermined manner. In some cases, it will be off. Note that the special symbol combinations that are jackpots include those that are in a high probability state (so-called probability variation state) in which the probability of jackpot increases until the next jackpot occurs.

  Further, when the game ball wins the normal winning opening 14, a predetermined prize ball is given to the player. When the game ball passes through the normal symbol operation gate 19, a game ball is detected by an operation gate detection sensor 121, which will be described later, and the normal symbol is displayed on the normal symbol display device 18 in a variable manner. When the normal symbol is a normal symbol determined in advance, the winning symbol is a win and the blades of the start winning opening (electric tulip) 11 are opened for a predetermined time.

  Next, each board | substrate arrange | positioned at the back surface of the gaming machine 1 will be described. FIG. 2 is a schematic diagram showing the entire back surface of the gaming machine 1. Reference numeral 50 denotes a mechanism plate, which is attached to the inner frame 23 by a hinge or the like (not shown) so as to be freely opened and closed. An opening 53 is provided at a substantially upper center portion so that the back surface of the game board 21 faces. A ball storage tank 51 for storing game balls supplied from the game island is provided on the upper part of the mechanism plate 50, and the game balls supplied to the ball storage tank 51 pass through the tank rail 52 to the prize ball payout device 41. Thus, as described above, based on the winning of the game ball to the start winning port 11, the normal winning port 14, etc., the prize ball paying device 41 is driven and a predetermined prize ball is paid out to the player. The prize ball payout device 41 is also driven by inserting a player's money, operating a ball lending switch after inserting a prepaid card, etc., and lending (renting) a predetermined number of game balls.

  A special symbol display device 6 attached to the gaming machine 1 faces the opening 53, and a display control board 39 is integrally attached to the special symbol display device 6 on the back side of the special symbol display device 6. ing. Further, a main control board 44, a payout control board 40, a launch control board 42, a power supply board 36, a lamp control board 37, and a sound control board 38 are respectively attached to substantially the lower part of the mechanism board 50. A terminal board 45 is attached to the upper right corner of the.

  FIG. 3 is a block diagram illustrating a main circuit configuration of the gaming machine 1. First, the main control board 44, which plays a central role in executing a game, has an 8-bit CPU 102 for executing a game progress control program, a ROM 103 for storing a control program executed by the CPU 102, and data processed by the CPU 102. A RAM 104 for temporary storage is provided. Further, the main control board 44 includes an input circuit 101, an output circuit 110, and a bus 115 (data bus, address bus, control bus, etc.) for connecting them, and each sensor and switch acquired via the input circuit 101. The CPU 102 executes a predetermined control program for controlling a later-described sub-control board connected to the output circuit 110, other various circuits, devices, and the like based on the signal from.

  The input circuit 101 includes a start winning detection sensor 116 that sends a special symbol variation start signal when a winning of a game ball provided in the start winning opening 11 is detected, and a count switch 123 that detects a game ball won in the starting winning opening 11. When the passing of the game ball provided in the normal symbol operation gate 19 is detected, the operation gate detection sensor 121 that sends a normal symbol variation start signal, and the game that has won a prize in the big prize opening 7 by opening the big prize opening 7 A count switch 117 for detecting a ball, a hitting operation handle switch 119 that is turned on when the hitting operation handle 2 is turned and a game ball is launched, and a pressing operation that is provided at a predetermined position of the hitting operation handle 2 The ball-hitting operation stop switch 120 that turns off the operation of the ball-hitting device 43 and stops the game ball from being fired, and the game that has won a prize A safe ball detection sensor 122 that outputs a safe signal necessary for counting a ball as a safe ball and paying out a game ball as a prize, and a game ball as a prize ball or a rental ball paid out from the prize ball payout device 41 A payout ball detection sensor 124 for counting is connected.

  The output circuit 110 includes a lamp control board 37 that controls lighting / flashing of LEDs (for example, the hold LED 25 and the hold LED 26) and various display lamps (for example, the game effect lamp 15) provided on the game board surface, and a grand prize. A solenoid 106 for opening the attacker as the mouth 7, a solenoid 107 for opening the electric tulip as the start winning opening 11, and a voice for performing voice control for amplifying various sound effects from the speaker 113. An external information terminal 109 is connected to the control board 38 and a hall management computer (not shown) and the like, and outputs various information from the main control board 44 (for example, information related to jackpots, winning balls, rental balls, etc.) to the outside of the gaming machine 1. Is connected to a terminal board 45 provided with In addition, the output circuit 110 is connected to a firing control board 42 for controlling the operation stop and operation stop release of the hitting ball launching device 43 for firing a pachinko ball toward the game area 5.

  Further, the output control board 40 and the display control board 39 are connected to the output circuit 110. The payout control board 40 drives and controls the prize ball payout device 41 to perform payout control of prize balls and balls. The display control board 39 controls an image displayed on the special symbol display device 6 as an LCD, a number displayed on the normal symbol display device 18 as a 7-segment LED, and the like.

  The lamp control board 37, the sound control board 38, the display control board 39, the payout control board 40, and the launch control board 42 function as sub control boards that play an auxiliary role in executing the game. Although not shown, the boards 37, 38, 39, 40, and 42 include a microcomputer mainly including a CPU, ROM, RAM, etc., as with the main control board 44, and commands in one direction from the main control board 44. It operates based on (command signal etc.). The CPU of the display control board 39 is a 32-bit CPU, and the other sub-control boards 37, 38, 40, and 42 are 8-bit CPUs.

  For example, the payout control board 40 stores and holds the payout control CPU, the work area of the payout control CPU, the number of prize balls (rental balls) corresponding to each prize ball (rental) command from the main control board 44, and the like. A RAM having a storage area for storing data, a ROM storing control data, a control program for paying out a prize ball (rented ball), and the like. That is, the payout control board 40 receives a control signal such as a one-way strobe signal or a payout control command signal from the CPU 102 of the main control board 44 via an input circuit (not shown). The CPU recognizes the payout control command and controls the prize ball payout device 41 to perform payout control of the prize ball (rented ball).

  Further, for example, the display control board 39 constitutes a CPU that reads an OS or the like for high-speed processing of enormous data and executes a display control program, a ROM that stores a display control program executed by the CPU, and a work area of the CPU. VDP for controlling images displayed on the special symbol display device 6 such as RAM and LCD, display control data (variation patterns, etc.) corresponding to each command read by the VDP, and image data for storing characters, symbols, backgrounds, etc. It includes a VRAM having a storage area for temporarily storing and holding image data and the like processed by the CGROM and VDP.

  That is, the display control board 39 receives a control signal such as a one-way strobe signal or a display control command signal from the CPU 102 of the main control board 44 via an input circuit (not shown), and when the strobe signal is input, the display control board 39 The CPU recognizes the display control command. Then, the VDP reads display control data and characters, symbols, backgrounds, and the like from the data area corresponding to the display control command from the CGROM, and stores the image data in the VRAM that temporarily stores the image data. The VDP reads the stored image data from the VRAM when the display order is reached, and displays the image data on the LCD (special symbol display device 6) in a predetermined manner in response to a command from the CPU 102.

  In this way, the control signal (strobe signal, command signal, etc.) is unidirectionally communicated from the main control board 44 to the sub control boards 37, 38, 39, 40, 42, that is, the sub control boards 37, 38, 39. , 40, and 42 to eliminate the input to the main control board 44 by reducing the input to the main control board 44 that controls the main control of the entire gaming machine 1, It is possible to eliminate as much as possible, and the game arcade can provide appropriate games to the player, and the circuit configuration and program relating to the communication between the two can be simplified, which facilitates development and production of the gaming machine 1 and leads to cost reduction.

  In the case where the main control board 44, the payout control board 40, etc. are stored in the board BOX, it is desirable to adopt a so-called caulking structure that is sealed by a predetermined means so that a trace of opening the board BOX remains. As a result, fraud to the main control board 44, the payout control board 40, etc. can be eliminated. Further, the normal symbol display device 18 connected to the display control board 39 may be directly connected to the output circuit 110 of the main control board 44, and the hitting operation handle switch 119 connected to the input circuit 101 and the hitting operation stop. The switch 120 may be directly connected to the launch control board 42. Further, the payout ball detection sensor 124 connected to the input circuit 101 of the main control board 44 may also input to the payout control board 40. These may be appropriately designed according to the functions and arrangement of various devices, the processing speed of each CPU, the capacity of a storage device such as a ROM and a RAM, and the like.

  Next, the main circuit configuration of the present invention will be described with reference to FIG. In the block diagram of FIG. 3, the circuit configuration of the main control board 44 and the sub control boards 37, 38, 39, 40, and 42 is mainly shown. However, the block diagram of FIG. 4 shows the main control board 44 and the lamp control. The main circuit configurations of the substrate 37 and the power supply substrate 36 are shown.

  First, the power supply board 36 receives a main power supply (AC24V) provided on a game island (not shown) via a power switch 55, and the power supply circuit 56 is based on this main power supply. In addition, the operation power supply (for example, full wave 24V, DC30V, DC12V, DC5V) is generated and supplied to each control device and drive device of the gaming machine 1 such as the sub control boards 37, 38, 39, 40, and 42. The power switch 55 is for manually turning on / off the supply of the main power supply AC24V, and a type (momentary type) is used that maintains the state when the power is turned on / off.

  In addition, a power supply monitoring circuit 57 is connected to the power supply circuit 56, and the power supply monitoring circuit 57 is configured such that when the voltage (24V) of the main power supply of the power supply circuit 56 drops below a predetermined voltage V1 (for example, 12V), the main control board. A power failure signal is sent to the NMI terminal (non-maskable interrupt terminal) of the CPU 102 of 44 (falling from the high level to the low level). That is, the power monitoring circuit 57 sends a power failure signal to the main control board 44 when the power to the gaming machine 1 is cut off due to an unexpected power failure or when the power switch 55 is turned off.

  Further, the power supply board 36 is provided with a backup power supply circuit 59 composed of a capacitor or the like, and the power failure signal described above is sent to the backup power supply circuit 59 from the power supply monitoring circuit 57 at the same time. Yes. The backup power supply circuit 59 is connected to the RAM 104 of the main control board 44, and supplies backup power to the RAM 104 when receiving a power failure signal from the power supply monitoring circuit 57. That is, the backup power supply circuit 59 backs up the RAM 104 of the main control board 44 when the power to the gaming machine 1 is cut off due to an unexpected power failure or when the power switch 55 is turned off.

  In the figure, 58 is a reset circuit, and this reset circuit 58 is connected to a power supply monitoring circuit 57. The main circuit of the power supply circuit 56 is restored when a power failure is restored or when the power switch 55 is turned on (when the power is turned on). In a state where the power supply voltage is still below the predetermined voltage V1, a reset signal is sent to the reset terminal of the CPU of the main control board 44 and the sub control boards 37, 38, 39, 40, and 42 (low level signal is output). On the other hand, when the main power supply voltage rises above the predetermined voltage V1, the sending of the reset signal is stopped (rises from a low level to a high level). The main control board 44 and the sub control boards 37, 38, 39, 40, 42 are activated when the reset signal transmission is stopped.

  Further, as described above, when the power to the gaming machine 1 is cut off due to an unexpected power failure or when the power switch 55 is turned off, the main control board 44 and the sub control boards 37, 38, 39, 40, 42 A reset signal is sent to the reset terminal of the CPU (falling from high level to low level). In this case, the reset signal to the main control board 44 is input with a delay of, for example, about 70 ms from the above power failure signal. Since the CPU 102 of the main control board 44 still operates normally during this 70 ms, a power failure process shown in FIG. 6 described later is executed during this period. The main control board 44 and the sub control boards 37, 38, 39, 40, and 42 stop operating when receiving the reset signal.

  Here, the main control board 44 will be described in detail later when the reset signal transmission is stopped and started. However, after executing a program such as actual initial setting, the main control board 44 is set by setting a waiting time counter or the like by software. The end time of the program processing such as the above initial setting is delayed for a predetermined time. In other words, in other words, this is synonymous with delaying the sending of the reset signal to the main control board 44 for a predetermined time via, for example, a delay circuit as hardware.

  In other words, when the reset signal is stopped when the power failure is restored or when the power switch 55 is turned on, the CPUs of the main control board 44 and the sub control boards 37, 38, 39, 40, and 42 are stored in the ROM. A program such as an initial setting is executed based on the stored control program. As described above, the sub-control boards 37, 38, 39, 40, and 42 are based on a command signal from the main control board 44 and the like. Game control is executed.

  Therefore, the sub-control boards 37, 38, 39, 40, and 42 reliably receive the command data related to the game transmitted from the main control board 44 at the time of recovery from power failure or when the power switch 55 is turned on. Needs to complete the execution of the program such as the initial setting prior to the main control board 44. Therefore, a delay time TA is set in order to end the execution of a program such as initial setting of the main control board 44 later than the sub control boards 37, 38, 39, 40 and 42, and program processing such as apparent initial setting is performed. Is terminated by the time TA.

  This delay time TA is about 8 seconds in this embodiment, and this is the most initial setting because it has a 32-bit CPU and VDP in the sub-control board, and reads an OS or the like for high-speed processing of enormous data. The display control board 39 is set in consideration of the time required to execute the program. In other words, this delay time TA is used for all sub-controls of command data related to the game to be transmitted first after the main control board 44 is started up after all of the sub-control boards 37, 38, 39, 40, 42 are surely started up. The timing is set so that the substrates 37, 38, 39, 40, and 42 can be reliably received.

  Further, the power supply board 36 is provided with a RAM clear switch 60 for erasing (clearing) various control information related to games stored and held in the RAM 104 of the main control board 44. A RAM clear switch circuit 61 for continuously sending a RAM clear signal to the CPU 102 of the main control board 44 when the RAM clear switch 60 is turned on is connected.

  The RAM clear switch 60 is a push button type (return type) that is in an ON state only while being pressed, and program processing such as apparent initial setting of the main control board 44 is completed. If the RAM clear switch 60 is turned on (pressed down) at this time (if a RAM clear signal is sent from the RAM clear switch circuit 61), the stored contents stored in the RAM 104 of the main control board 44 are stored. Is cleared (initialized). That is, when the RAM 104 of the main control board 44 is cleared, the main control board 44 finishes the program processing such as the apparent initial setting after about 8 seconds after the power switch 55 is turned on (or after recovery from power failure recovery). The condition is that the RAM clear switch 60 is turned on at the time.

  Next, the lamp control board 37 includes a well-known microcomputer mainly including a CPU 70, a ROM 71 that stores a control program executed by the CPU 70, a RAM 72 that temporarily stores data processed by the CPU 70, and the like. The lamp control board 37 includes a lamp / LED drive circuit 78, and the CPU 70 drives the lamp / LED drive circuit 78 to control lighting / flashing of the hold LED 25, the hold LED 26, the game effect lamp 15, and the like. To do.

  Here, as with the main control board 44, when the lamp control board 37 is started after the reset signal is stopped, the lamp control board 37 executes a program such as an actual initial setting and then sets a waiting time counter or the like by software. The end time of program processing such as apparent initial setting is delayed by time TB. The delay time TB is about 3 seconds in this embodiment, which is about 5 seconds shorter than the delay time TA.

  That is, the delay time TB is set to a time shorter than the delay time TA of the main control board 44, and is set regardless of the other sub-control boards 38, 39, 40, and 42. The lamp control board 37 starts up about 3 seconds after starting, which is about 5 seconds before the main control board 44 starts up. As a result, the lamp control board 37 can reliably receive command data relating to the game to be transmitted first after the main control board 44 stands up.

  Further, a 7-segment LED 75 and an LED 76 are connected to an output circuit (not shown) of the CPU 70 of the lamp control board 37 via an LED driver circuit. The 7 segment LED 75 counts down the timing when the RAM clear switch 60 is turned on. On the other hand, the LED 76 is used for main control when the RAM 104 of the main control board 44 is cleared by turning on the RAM clear switch 60. The LED is turned on in response to a RAM clear signal from the substrate 44 (when the RAM 104 is not cleared, the LED 76 remains off). This will be described with reference to FIG.

  FIG. 5 is a timing chart showing the operating states of the main control board 44, the lamp control board 37, and the RAM clear switch 60 when the power is turned on. When the power switch 55 is turned on and the gaming machine 1 is powered on, the reset signal transmission is stopped (rises from the low level to the high level), and the main control board 44 and the lamp control board 37 are activated. That is, the main control board 44 and the lamp control board 37 are activated simultaneously.

  When activated, the main control board 44 and the lamp control board 37 execute a program such as an actual initial setting, and then set a waiting time counter or the like by software to end the program processing such as an apparent initial setting. The main control board 44 is set after the delay time TA (8 seconds), and the lamp control board 37 is set after the delay time TB (3 seconds).

  The main control board 44 and the lamp control board 37 have substantially the same time from when the power is turned on until the program such as the actual initial setting is completed, and the time is also a very short time of about several tens of ms. It is.

  When the delay time TB (3 seconds) elapses, the lamp control board 37 displays “4” on the 7-segment LED 75, and “3” “2” “1” “0” every time 1 second elapses thereafter. Execute countdown display. Therefore, the time when “0” is displayed on the 7-segment LED 75 is about 1 second before the delay time TA (8 seconds) of the main control board 44 elapses. That is, “0” is displayed on the 7-segment LED 75 about 1 second before the program processing such as the apparent initial setting is finished on the main control board 44.

  Accordingly, when a store clerk or the like of the game hall clears the RAM 104 of the main control board 44, the RAM clear switch 60 is pressed at the timing when “0” is displayed on the 7-segment LED 75 in accordance with the count-down display of the 7-segment LED 75. Just operate. When the delay time TA (8 seconds) elapses while the RAM clear switch 60 is pressed (while the RAM clear signal is continuously sent), the stored contents stored in the RAM 104 are stored. Cleared (initialized). That is, in this embodiment, the contents stored in the RAM 104 of the main control board 44 are cleared after about 1 second has elapsed since the RAM clear switch 60 was pressed.

  When the stored contents of the RAM 104 are cleared, the CPU 102 of the main control board 44 sends a RAM clearing signal indicating that the stored contents of the RAM 104 are cleared to an input circuit (not shown) of the CPU 70 of the lamp control board 37. When the CPU 70 of the lamp control board 37 receives the RAM clearing signal, the LED 76 is lit in a predetermined color (for example, red) for a predetermined time (for example, 5 seconds) to notify the outside that the stored contents of the RAM 104 have been cleared. . Therefore, after confirming that the LED 76 is turned on, the pressing operation of the RAM clear switch 60 may be released. In this embodiment, the pressing operation of the RAM clear switch 60 is performed after about 1 second from the lighting of the LED 76. It shows the case of release. That is, in the present embodiment, the stored contents of the RAM 104 of the main control board 44 can be surely cleared only by executing the pressing operation of the RAM clear switch 60 for a short time of about 2 seconds.

  Each process executed by the gaming machine 1 configured as described above will be described with reference to the flowcharts in FIG. FIG. 6 shows a power failure process executed by the main control board 44 when the power to the gaming machine 1 is shut off due to an unexpected power failure or when the power switch 55 is turned off and a power failure signal is input to the NMI terminal of the CPU 102. It is a flowchart to show.

  When a power failure signal is input to the NMI terminal of the CPU 102, the CPU 102 first writes the values of each register, I / O, etc. to the stack area in step S10, and proceeds to step S12 to back up the stack pointer value in the RAM 104. Write to the area and save it. Next, the process proceeds to step S14, where the CPU 102 writes various information (data) related to the game when a power failure occurs to the backup area of the RAM 104, and stores the game state when the power is cut off in the gaming machine 1. To do.

  Then, the process proceeds to step S16, and the CPU 102 turns on the backup flag indicating that the power failure process has been executed, proceeds to step S18, prohibits access to the RAM 104, and then enters an infinite loop. When the reset signal (falling from the high level to the low level) is received, the operation of the CPU 102 is completely stopped, whereby the power failure process is completed.

  FIG. 7 is a flowchart showing a power-on process executed by the main control board 44 when power is turned on to the gaming machine 1 by turning on the power switch 55 or returning from a power failure. This power-on process is started when the CPU 102 is activated when the sending of the reset signal input to the reset terminal of the CPU 102 is stopped (rises from a low level to a high level).

  When the power-on process is started, the CPU 102 first sets the interrupt prohibition in step S20, shifts to step S21, and sets the RAM 104 in an accessible state. Then, the process proceeds to step S22, and initialization processing is executed. In this initialization process, for example, a specified address is set in a stack pointer or I / O, or an initial value is set in a work area (for example, a counter, buffer, or pointer) of the RAM 104. That is, the initialization process in step S22 corresponds to the program process such as the actual initial setting described above.

  After completing the initialization process in step S22, the CPU 102 proceeds to step S24 and executes a delay process. FIG. 8 is a flowchart showing a delay process executed by the main control board 44. When this delay process is started, the CPU 102 first sets a value corresponding to the delay time TA (8 seconds) in a general-purpose register or the like as the counter A in step S25. Then, the process proceeds to step S26, and the CPU 102 executes a process of decrementing (decrementing by 1) the value of the counter A. The process proceeds to step S27, where it is determined whether or not the value of the counter A has become 0. To do.

  If the value of counter A is not 0 (NO in step S27), CPU 102 executes the processing of steps S26 and S27 again, and this is repeated until the value of counter A becomes 0. If YES in step S27, that is, if the value of the counter A becomes 0, the CPU 102 determines that the delay time TA has elapsed and ends this delay processing.

  That is, in this delay process, the value (positive integer) set in the counter A in step S25 is substantially equal to the value obtained by dividing the delay time TA by the execution time of steps S26 and S27, and therefore FIG. The delay time TA is created by software through the processing of step S26 and step S27 shown in FIG. By this delay process executed after the initialization process in step S22, the end time of the program process such as the apparent initial setting can be delayed by the time TA.

  Returning to FIG. 7, when the delay process of step S24 is completed, the CPU 102 proceeds to step S29 and determines whether or not the RAM clear signal is input, that is, the RAM clear switch 60 provided on the power supply board 36 is turned on. It is determined whether or not it is turned on. If the RAM clear signal has not been input and the determination in step S29 is NO, the CPU 102 proceeds to step S30 to check whether the backup flag indicating that the power failure process has been executed is on. Determine whether or not. If YES in step S30, that is, if it is determined that the backup flag is on, the CPU 102 proceeds to step S60 and executes a power recovery process. This power recovery process will be described later.

  On the other hand, if the RAM clear signal is input and it is determined YES in step S29, the CPU 102 skips step S30, that is, whether or not the backup flag is on, the CPU 102 proceeds to step S32. The RAM clear process for erasing the stored contents of the RAM 104 is executed. That is, if the RAM clear switch 60 is turned on when the delay processing in step S24 is completed, the CPU 102 erases the stored contents of the RAM 104.

  Then, the process proceeds to step S33, and the CPU 102 sets a timer interrupt (in this embodiment, it is set so as to be repeatedly generated every 4 ms), and the process proceeds to step S34 and the interrupt prohibition executed in step S20 is performed. Cancel processing and allow interrupt. Thereafter, the CPU 102 repeatedly executes the game control process of step S36 every time there is a timer interrupt, that is, every 4 ms.

  FIG. 9 is a flowchart showing game control processing executed by the main control board 44. The CPU 102 executes each program stored in the ROM 103 every timer interrupt (4 msec), that is, each process of S40 to S50 described below. When this game control process is started, the CPU 102 first executes a random number update process in step S40. In this random number update processing, for example, a big hit random number counter for lottery whether or not to generate a big hit, a special symbol displayed on the left symbol display unit 8, the middle symbol display unit 9 and the right symbol display unit 10 of the special symbol display device 6 A special symbol determination random number counter for determining the fluctuation pattern, a fluctuation pattern determination counter for determining the fluctuation pattern of the special symbol, a random number counter for lottery whether or not to generate a hit, and a normal symbol to be fixedly displayed on the normal symbol display device 18 The random number used for the normal symbol determination random number counter or the like is updated. These random numbers are updated by means of incrementing (adding 1) each interrupt, for example, and resetting when a predetermined value is reached.

  When the random number update process of step S40 is completed, the CPU 102 proceeds to step S42 to execute the normal symbol game process, and then proceeds to step S44 to execute the hit process. In the normal symbol game process and the winning process, based on the fact that the game ball has passed through the normal symbol operation gate 19, the normal symbol display device 18 receives a number as a normal symbol by the normal symbol variation start signal from the operation gate detection sensor 121 ( For example, when 1 to 9) is displayed in a variable manner and a predetermined number (for example, 7) is confirmed and displayed, it is a hit, and a process of opening the blades of the electric tulip as the start winning opening 11 for a predetermined time is executed. Note that the game balls that have passed through the normal symbol operation gate 19 while the normal symbol is being displayed are retained balls, and up to four retained balls are stored, and the four retained LEDs 26 are sequentially turned on or off to inform the player. After the normal symbol variation display is completed, the player is notified of how many times the lottery will be performed.

  Then, the CPU 102 proceeds to step S46 to execute a special symbol game process, and then proceeds to step S48 to execute a jackpot process. In the special symbol game process and the jackpot process, the CPU 102 determines a predetermined variation pattern on the special symbol display device 6 by a special symbol variation start signal from the start winning detection sensor 116 based on the winning of the game ball to the start winning port 11. When three special symbols are scroll-displayed and a predetermined special symbol is confirmed and displayed on the left symbol display unit 8, the middle symbol display unit 9, and the right symbol display unit 10 after a predetermined time has elapsed, a big win is obtained. (Attacker) Execute a jackpot game that opens 7 in a predetermined manner (for example, the winning opening 7 is opened for 30 seconds or until 10 gaming balls are won, and the gaming ball is placed in a specific area within the winning opening 7. If it passes, the opening is repeated up to 16 times). Note that the game balls won in the start winning slot 11 while the special symbol is being scrolled are held balls, and up to four of these held balls are stored, and the four held LEDs 25 are sequentially turned on or off to give the player After the special symbol scroll display is finished, the player is informed of how many times the big winning lottery will be performed.

  Here, the special symbol combination that is a big win includes a specific big win symbol that has a high probability state (so-called probability fluctuation state) with a dramatic increase in the probability of a big hit until the next big hit occurs. . For example, when the special symbol is a number symbol of “1-14” in the gaming machine 1, “1, 1, 1” to “14, 14, 14” are set as a combination of special symbols that are big hits, Among them, the odd numbered numbers (“1, 1, 1” “3, 3, 3” “5, 5, 5” “7, 7, 7” “9, 9, 9” “11, 11, 11 ”“ 13, 13, 13 ”) is a specific big symbol, and other numbers are the same numbers (“ 2, 2, 2 ”,“ 4, 4, 4 ”,“ 6, 6, 6 ”,“ 8, 8, 8 ”,“ 10, 10, 10 ”,“ 12, 12, 12 ”,“ 14, 14, 14 ”) are normally set as big win symbols.

  When the special big win symbol is confirmed and displayed on the special symbol display device 6, after the big hit game is finished, the big hit and the hit probability are increased by a random number changing process, etc., and the special symbol scroll display time and the normal symbol change display The time is shortened, and the opening time of the electric tulip as the start winning opening 11 is extended, that is, a gaming state (probability variation state) that is extremely advantageous for the player occurs, and this gaming state causes the next big hit. Until it is continued. On the other hand, when the normal big winning symbol is confirmed and displayed, after the big hit game is finished, the normal game state is restored. In the case where the regular big symbol symbol is displayed in a fixed manner, the special big symbol symbol is displayed and confirmed until the special symbol scroll display is executed a predetermined number of times (for example, 100 times). You may make it provide privilege other than a raise of jackpot probability (so-called short-time state).

  When the big hit process in step S48 is completed, the CPU 102 proceeds to step S50 and executes other processes. In the other processes of step S50, various processes are executed in addition to the processes of steps S40 to S48. For example, a process of paying out a predetermined number of prize balls by winning a game ball or a game state is matched. A signal indicating that the game effect lamp 15 or the like is controlled to be turned on in a predetermined manner or that a sound effect is output from the speaker 113 or that a big hit process is being performed from the external information terminal 109 or that the game state is in a high probability state. And the like are output to a hall management computer (not shown) outside the gaming machine 1.

  Returning to FIG. 7, the power recovery process that is executed when it is determined YES in step S <b> 30 will be described. That is, if it is determined as YES in step S30, the power recovery process of step S60 is executed to return each state of the main control board 44 to the state immediately before the power is shut off. FIG. 10 is a flowchart showing the power recovery process executed by the main control board 44. When the power recovery process is started, the CPU 102 first clears the backup flag stored in the RAM 104 in step S16 of the power failure process in step S62, and then proceeds to step S64 to start from the backup area of the RAM 104. Read the value of the stack pointer and write it to the stack pointer.

  Then, the process proceeds to step S66, and the CPU 102 reads the values of each register and I / O saved in the stack area, writes these values to the original register and I / O, etc., and proceeds to step S68. Return to the state before interrupting the power supply (before power failure) (set the return address of the interrupt processing), and play a game when a power failure occurs that is stored in the backup area of the RAM 104 Based on the various information (data), the game control process in step S36 is resumed from the state immediately before the power is turned off. Therefore, by this power recovery process, for example, if a power outage occurs in the middle of a big hit gaming state or a high probability state (probability variation state), the game state can be resumed from the subsequent gaming state after power recovery. One can avoid unexpected disadvantages.

  Next, the RAM clear notification process executed by the lamp control board 37 will be described. FIG. 11 is a flowchart showing a RAM clear notification process executed by the CPU 70 of the lamp control board 37. This RAM clear notification process is started when the CPU 70 is activated when the sending of the reset signal input to the reset terminal of the CPU 70 is stopped (rises from a low level to a high level).

  When the RAM clear notification process is performed, the CPU 70 first executes an initialization process in step S80. Since this initialization process is the same as the initialization process in step S22 in the power-on process described above, description thereof is omitted here. The initialization process in step S80 corresponds to the program process such as the actual initial setting described above.

  After completing the initialization process in step S80, the CPU 70 proceeds to step S81 and executes the delay process similar to that of the main control board 44. FIG. 12 is a flowchart showing a delay process executed by the lamp control board 37. When this delay process is started, the CPU 70 first sets a value corresponding to the delay time TB (3 seconds) in a general-purpose register or the like as the counter B in step S82. Then, the process proceeds to step S83, and the CPU 70 executes a process of decrementing (decrementing by 1) the value of the counter B. The process proceeds to step S84, where it is determined whether or not the value of the counter B has become zero. To do.

  If the value of counter B is not 0 (NO in step S84), CPU 70 executes the processes of steps S83 and S84 again, and this is repeated until the value of counter B becomes 0. If YES in step S84, that is, if the value of the counter B becomes 0, the CPU 70 ends the delay process, assuming that the delay time TB has elapsed.

  In other words, in this delay processing, the value (positive integer) set in the counter B in step S82 is substantially equal to the value obtained by dividing the delay time TB by the execution time of steps S83 and S84, and therefore FIG. The delay time TB is created by software through the processing of step S83 and step S84 shown in FIG. By this delay processing executed after the initialization processing in step S80, the end time of program processing such as apparent initial setting can be delayed by time TB.

  Returning to FIG. 11, when the delay process of step S81 is completed, the CPU 70 proceeds to step S85 to control the LED driver circuit to notify the 7-segment LED 75 of the timing for turning on the RAM clear switch 60. Execute countdown display. In this countdown display, “4” is displayed almost simultaneously with the delay processing in step S81, and thereafter, “3”, “2”, “1”, and “0” are displayed every 1 second by the internal timer of the CPU.

  Therefore, when a store clerk or the like of the game hall clears the RAM 104 of the main control board 44, if the RAM clear switch 60 is pressed at the timing when “0” is displayed on the 7-segment LED 75, the main control is performed after about 1 second. Since the delay time TA (8 seconds) of the board 44 elapses (because program processing such as apparent initial setting is completed in the main control board 44), the RAM 104 is cleared. Then, the process proceeds to step S86, and the CPU 70 determines whether or not the RAM clearing signal indicating that the stored contents of the RAM 104 has been cleared from the CPU 102 of the main control board 44 is turned on (input), and in step S86. If NO, that is, if the RAM clear signal is not turned on (input) after waiting for a predetermined time (for example, 2 seconds), the RAM clear notification process is terminated.

  On the other hand, if YES in step S86, that is, if the RAM clearing signal is turned on (input), the CPU 70 proceeds to step S87, lights the LED 76 in a predetermined color for a predetermined time, and clears the stored contents of the RAM 104. Inform the outside that this has been done. Since this RAM clearing signal is immediately input to the CPU 70 when the RAM 104 is cleared, the LED 76 is turned on about 1 second (slightly exceeding 1 second) after “0” is displayed on the 7-segment LED 75. To do.

  Therefore, the store clerk of the game hall only needs to release the pressing operation of the RAM clear switch 60 by visually recognizing that the LED 76 is turned on. That is, the store clerk of the game hall holds the RAM clear switch 60 slightly longer than about 1 second. The RAM 104 can be surely cleared by simply pressing the button for less than 2 seconds. Thereby, for example, when the closing time is reached with the high probability of hitting on the previous day and the power of the gaming machine 1 is shut off in that state, or when the gaming machine 1 is used at the game hall only after it arrives (so-called Even in the case of a new stand), by clearing the RAM 104 before the store is opened, the game arcade 1 can be used with peace of mind without suffering any unexpected disadvantage. When the process of step S87 is completed, the CPU 70 ends the RAM clear notification process.

  It should be noted that if the LED 76 does not turn on even after a predetermined time (for example, 2 seconds) has elapsed since the “0” is displayed on the 7-segment LED 75, it is determined that the RAM 104 has failed to be cleared. The switch 55 is turned off to cut off the power of the gaming machine 1, and then the power switch 55 is turned on to turn on the power to the gaming machine 1 and then the RAM clear switch 60 is pressed again as described above, so that the RAM 104 is Just clear it.

  As is clear from the above description, in the gaming machine 1 of the present embodiment, the performance of the sub-control board such as the display control board 39 is improved, and the time from when the power is turned on until all the sub-control boards start up becomes longer. Even when the RAM 104 of the main control board 44 being backed up is cleared, the timing of pressing the RAM clear switch 60 is appropriately notified by the 7-segment LED 75.

  That is, the main control board 44 and the lamp control board 37 execute a program such as an actual initial setting when activated, and then set a waiting time counter or the like by software, thereby performing a program process such as an apparent initial setting. The end time is delayed by a predetermined time. Then, by setting the delay time TB of the lamp control board 37 shorter than the delay time TA of the main control board 44, the lamp control board 37 is set to a predetermined time (delay time TA-delay time) than the main control board 44. TB) Start up quickly, and using this time (delay time TA-delay time TB), the lamp control board 37 notifies the timing of pressing down the RAM clear switch 60 by the 7-segment LED 75. And the like can know the timing of pressing the RAM clear switch 60.

  In this embodiment configured as described above, the operator can operate the power switch 55 and the RAM clear switch 60 with a time difference, and saves the trouble of having to press the RAM clear switch 60 for a long time. That is, the operation time of the RAM clear switch 60 is shortened and workability is improved.

  Especially in amusement halls, the operation of clearing RAM has to be performed for a large number of gaming machines 1 before opening the store, which is a busy time zone in which other work is concentrated, and is an extremely complicated task. Shortening the work time for clearing RAM reduces the work of the store clerk and has a very remarkable effect. For example, if the power switch 55 of a plurality of gaming machines 1 is sequentially turned on, and then the RAM clear switch 60 of the gaming machine 1 is sequentially depressed according to the notification of the 7-segment LED 75 of the lamp control board 37, a plurality of It is also possible to execute RAM clear of the gaming machines 1 collectively.

  Further, since the delay time TA and the delay time TB of the main control board 44 and the lamp control board 37 are set by software program processing, hardware resources (for example, a delay circuit) for performing the delay processing are thereby set. This eliminates the need for the developer and facilitates the circuit design while reducing the cost. Furthermore, since the hardware resources are not required, the size of the board related to the notification of the timing of pressing the RAM clear switch 60 is minimized (corresponding to the lamp control board 37 in this embodiment), thereby The limited space of the machine 1 can be effectively used. Furthermore, even when changing the setting of the delay time, it can be easily executed with a simple program change, so it is extremely convenient.

  As mentioned above, although embodiment of this invention has been described based on drawing, a concrete structure is not limited to what was shown in embodiment, The change and addition in the range which does not deviate from the summary of this invention And the like are included in the present invention.

  For example, in the present embodiment, the lamp control board 37 first displays “4” on the 7-segment LED 75, and executes countdown display of “3”, “2”, “1”, “0” every time 1 second elapses thereafter. Thus, the RAM clear switch 60 is depressed at the timing when “0” is displayed. That is, the lamp control board 37 is notified about 5 seconds before the timing at which the RAM clear switch 60 is depressed. However, what is necessary is just to set suitably how many seconds ago this is notified. However, if it is too short, the timing will be lost, so it is desirable that it be 3 seconds or longer.

  Further, the display form of the countdown is not limited to this, and any display form may be used as long as it is generally understandable, and conversely, a display form such as counting up may be used. In these cases, a display such as a liquid crystal display may be employed instead of the 7-segment LED 75. For example, a display form in which a plurality of LEDs are simply arranged and sequentially turned off or on to count down (or count up) may be used. Further, a plurality of such display forms may be provided in advance so that a desired display form can be selected with a changeover switch or the like.

  In this embodiment, the 7-segment LED 75 and the LED 76 are provided on the lamp control board 37. However, this may be provided separately from the lamp control board 37, and the role of the lamp control board 37 may be different. The sub-control boards 38, 39, 40, and 42 may be performed.

  In this embodiment, the RAM clear signal is input to the CPU 102 of the main control board 44 by pressing the RAM clear switch 60 and the RAM 104 is cleared. This RAM clear signal is used when the power switch 55 is turned on. The CPU 102 may accept only at the time of operation. That is, the RAM clear switch 60 is invalidated even when operated except when the power switch 55 is turned on. In the first place, when the RAM 104 is cleared, the gaming machine 1 in which the RAM 104 is backed up is continued from the previous day for management purposes, such as when the closing time is reached with the high probability of hitting on the previous day as described above. This is because we want to keep it in a non-existent state.

  However, if a function that can clear the RAM 104 at any time is added, if the RAM 104 is cleared by operating the RAM clear switch 60 by mistake, the state of the gaming machine 1 returns to the initial state at that time, (For example, when a power failure occurs during a big hit game and then the RAM clear switch 60 is erroneously operated when power is restored). Therefore, in order to eliminate such an erroneous operation of the RAM clear switch 60, the RAM clear switch 60 is invalidated even when operated other than when the power switch 55 is turned on.

  This is because the operation of the RAM clear switch 60 is mostly performed at the time before opening the store, and naturally, the power switch 55 is turned on to turn on the gaming machine 1 before opening the store. It is. Specifically, for example, when the power switch 55 is turned on, a RAM clear permission signal is output to the CPU 102 of the main control board 44, and the RAM clear signal from the RAM clear switch 60 is turned on to the CPU 102. Thus, the RAM 104 of the main control board 44 may be cleared when this RAM clear permission signal is input.

  In the present embodiment, when the RAM 104 is cleared, the lamp control board 37 receives the RAM clearing signal from the main control board 44 and turns the LED 76 to a predetermined color (for example, red) for a predetermined time (for example, 5 seconds). When the RAM 104 is not cleared, the LED 76 is turned off so that nothing is changed. This is because the LED 76 color, lighting mode, etc. , Extinguishing, flashing, etc.) can be set by appropriately selecting.

  For example, even when the RAM 104 is not cleared, the LED 76 may be lit in a predetermined color (for example, blue) for a predetermined time (for example, 5 seconds) to notify the operator to that effect. Specifically, the LED 76 may emit two colors, or one LED having a light emission color different from the LED 76 may be added.

  Further, such a function of the LED 76 may be a 7-segment LED 75. For example, when the RAM 104 is cleared, “A” is lit and displayed, and when the RAM 104 is not cleared, “H” is flashed. In this way, predetermined characters, numbers, or the like may be displayed or the lighting mode may be changed. In this case, as a result, the LED 76 need not be provided, and the cost can be reduced.

  In addition, the main control board 44 and the sub control boards 37, 38, 39, 40, and 42 are examples of a microcomputer in which a CPU, a ROM, and a RAM are separately provided, but these are all integrated one-chip. Alternatively, for example, a chip in which only a CPU and a RAM are integrated (a so-called built-in RAM type CPU), such as a predetermined memory and a CPU, is used. Also good.

  In addition, the gaming machine 1 of the present invention described above is equipped with a microcomputer centering on a CPU, ROM, RAM, etc., such as a pachinko gaming machine, a throttle gaming machine, an arrangement gaming machine, a jean ball gaming machine, a pinball gaming machine, etc. It can be applied in various gaming machines.

  Next, another embodiment of the gaming machine 1 will be described. In this embodiment, the functions of the 7-segment LED 75 and the LED 76 are made to the existing game effect lamp 15, the hold LED 25, and the hold LED 26. Therefore, the 7-segment LED 75 and the LED 76 are omitted in FIG. . That is, this embodiment is an example in which the lamp control board 37 performs lighting control of the game effect lamp 15, the hold LED 25, and the hold LED 26 in a predetermined manner and notifies the timing of pressing the RAM clear switch 60. In addition, description here is abbreviate | omitted about the structure similar to the structure mentioned above in this embodiment.

  FIG. 13 is a timing chart showing operation states of the main control board 44, the lamp control board 37, the game effect lamp 15, the hold LED 25, the hold LED 26, and the RAM clear switch 60 when the power is turned on. When the power switch 55 is turned on and the gaming machine 1 is turned on, the main control board 44 and the lamp control board 37 are stopped by software after the reset signal transmission is stopped and started, as described above. By setting a counter or the like, a delay time TA (8 seconds) and a delay time TB (3 seconds) are set.

  When the delay time TB (3 seconds) has elapsed, the lamp control board 37 repeats the operation of turning off the game effect lamp 15, the hold LED 25, and the hold LED 26 for about 0.3 seconds and then turning off for 0.7 seconds three times. That is, this is an operation in which the game effect lamp 15, the hold LED 25, and the hold LED 26 are lit three times in 3 seconds. The lamp control board 37 then repeats the operation of blinking the game effect lamp 15, the hold LED 25, and the hold LED 26 for 0.1 second for 2 seconds. Therefore, the time point when the blinking operation of 0.1 second is started is about 2 seconds before the delay time TA of the main control board 44 elapses. That is, the game effect lamp 15, the hold LED 25, and the hold LED 26 start blinking about two seconds before the program processing such as the apparent initial setting is finished on the main control board 44.

  Therefore, when a game clerk or the like clears the RAM 104 of the main control board 44, the game effect lamp 15, the hold LED 25, and the hold LED 26 blink in accordance with the lighting state of the game effect lamp 15, the hold LED 25, and the hold LED 26. When the operation is started, the RAM clear switch 60 may be pressed. However, since it is difficult to press down the RAM clear switch 60 immediately after the game effect lamp 15, the hold LED 25, and the hold LED 26 start blinking operation, in FIG. 13, 1 second has elapsed from the start of this blinking operation. An example is shown in which the RAM clear switch 60 is pressed at the time of the above. That is, for this reason, the blinking operation time of the game effect lamp 15, the hold LED 25, and the hold LED 26 is set to 2 seconds, so that the blinking operation time has a margin.

  When the RAM clear switch 60 is pressed (while the RAM clear signal is continuously sent), when the delay time TA of the main control board 44 elapses and the main control board 44 starts up, the RAM 104 The stored contents stored and held in are cleared (initialized). That is, in this embodiment, the contents stored in the RAM 104 of the main control board 44 are cleared after about 1 second has elapsed since the RAM clear switch 60 was pressed.

  When the stored contents of the RAM 104 are cleared, the CPU 102 of the main control board 44 sends a RAM clearing signal indicating that the stored contents of the RAM 104 are cleared to an input circuit (not shown) of the CPU 70 of the lamp control board 37. . When the CPU 70 of the lamp control board 37 receives the RAM clearing signal, the game effect lamp 15, the hold LED 25, and the hold LED 26 are turned on for a predetermined time (for example, 5 seconds) to notify the outside that the stored contents of the RAM 104 have been cleared. To do.

  Therefore, after confirming that the game effect lamp 15, the hold LED 25, and the hold LED 26 are lit, the pressing operation of the RAM clear switch 60 may be released. In this embodiment, the game effect lamp 15, the hold LED 25, and the hold LED 26 are released. This shows a case in which the pressing operation of the RAM clear switch 60 is canceled after about 1 second has elapsed since lit up. That is, in the present embodiment, the stored contents of the RAM 104 of the main control board 44 can be surely cleared only by executing the pressing operation of the RAM clear switch 60 for a short time of about 2 seconds.

  As described above, in the present embodiment, the lamp control board 37 controls the lighting state of the existing game effect lamp 15, the hold LED 25, and the hold LED 26 to notify the timing of pressing the RAM clear switch 60. Therefore, it is not necessary to add a new notification device to the gaming machine 1, so that the configuration of the gaming machine 1 is simplified and costs are reduced, and the limited space of the gaming machine 1 can be used more effectively.

  Furthermore, another embodiment of the gaming machine 1 will be described with reference to FIG. FIG. 14 is a block diagram showing main circuit configurations of the main control board 44, the payout control board 40, the lamp control board 37, and the power supply board 36. In this embodiment, the RAM 212 of the payout control board 40 is backed up in addition to the RAM 104 of the main control board 44, and the stored contents of the RAM 212 are also erased by pressing the RAM clear switch 60. In the present embodiment, the description of the same configuration as described above is omitted.

  Referring to FIG. 14, when the voltage of the main power supply of power supply circuit 56 falls below a predetermined voltage V1, power supply monitoring circuit 57 sends a power failure signal to the NMI terminals of both CPU 102 and CPU 210 of main control board 44 and payout control board 40. Send it out. That is, the power supply monitoring circuit 57 sends a power failure signal to the main control board 44 and the payout control board 40 when the power to the gaming machine 1 is cut off due to an unexpected power failure or when the power switch 55 is turned off.

  The backup power supply circuit 59 is connected to both the RAM 104 and RAM 212 of the main control board 44 and the payout control board 40. When a power failure signal is received from the power monitoring circuit 57, backup power is supplied to both the RAM 104 and RAM 212. . That is, the backup power supply circuit 59 backs up the RAM 104 of the main control board 44 and the RAM 212 of the payout control board 40 when the power to the gaming machine 1 is cut off due to an unexpected power failure or when the power switch 55 is turned off. .

  As with the main control board 44 and the lamp control board 37, the payout control board 40 sets up a standby time counter by software after the reset signal transmission is stopped and starts up, thereby making it possible to set an apparent initial setting, etc. Delay processing for delaying the end time of the program processing by a predetermined time is executed (see FIGS. 8 and 12), and the delay time TC set by the payout control board 40 is about 7 seconds. This delay time TC is approximately 1 second shorter than the delay time TA (8 seconds) set by the main control board 44 described above.

  That is, the payout control board 40 stands up about 1 second before the main control board 44 rises and is ready to receive a command from the main control board. Further, when the RAM clear signal is input to the CPU 210 of the payout control board 40 by the RAM clear switch 60 provided on the power supply board 36 and the stored contents stored in the RAM 212 are thereby cleared (initialized), A RAM clearing signal is sent to the CPU 70 of the lamp control board 37.

  Further, a speaker 225 is connected to the CPU 70 of the lamp control board 37 through a voice synthesis IC, an amplifier, etc. (not shown) in addition to the above-described 7-segment LED 75 and LED 76, and the RAM clear switch 60 is connected from the speaker 225. The timing to turn on and the fact that the RAM 104 and RAM 212 of the main control board 44 and the payout control board 40 are cleared are notified to the outside by voice. These relationships will be described with reference to FIG.

  FIG. 15 is a timing chart showing the operating states of the main control board 44, the payout control board 40, the lamp control board 37, and the RAM clear switch 60 when the power is turned on. When the power switch 55 is turned on and the gaming machine 1 is turned on, the main control board 44, the payout control board 40, and the lamp control board 37 are started after the reset signal transmission is stopped as described above. The delay time TA (8 seconds), the delay time TC (7 seconds), and the delay time TB (3 seconds) are set by setting a waiting time counter or the like by software. That is, the payout control board 40 rises about 4 seconds after the lamp control board 37 rises, while the main control board 44 stands about 5 seconds after the lamp control board 37 rises (after the payout control board 40 rises). Stand up after about 1 second).

  The lamp control board 37 displays “3” on the 7-segment LED 75 when the delay time TB (3 seconds) elapses, and executes countdown display of “2”, “1”, “0” every time 1 second elapses thereafter. To do. Further, the lamp control board 37 pronounces “3” from the speaker 225 at the same time that “7” is displayed on the 7-segment LED 75, and “2”, “1”, and “0” each time one second elapses thereafter. . That is, the display content of the 7-segment LED 75 is sounded from the speaker 225 in synchronization with the display of the 7-segment LED 75.

  Accordingly, when a store clerk or the like of the game hall clears the RAM 104 of the main control board 44 and the RAM 212 of the payout control board 40, “0” is displayed on the 7-segment LED 75 in accordance with the countdown display of the 7-segment LED 75 or the sound output from the speaker 225. The RAM clear switch 60 may be pressed down at the timing when "" is displayed or when "0" is sounded from the speaker 225.

  While the RAM clear switch 60 is being pressed (while the RAM clear signal is continuously sent), first, the payout control board 40 has passed the delay time TC (7 seconds). Stored in the RAM 212 is cleared (initialized), and when the main control board 44 starts up after the delay time TA (8 seconds) of the main control board 44 elapses, it is stored in the RAM 104. The stored contents are cleared (initialized). In other words, in this embodiment, the storage content of the RAM 212 of the payout control board 40 is cleared after about 1 second has elapsed since the RAM clear switch 60 was pressed, and after about 1 second has elapsed, the RAM 104 of the main control board 44 has been cleared. The stored contents will be cleared.

  When the stored contents of the RAM 212 are cleared, the CPU 210 of the payout control board 40 sends a RAM clearing signal indicating that the stored contents of the RAM 212 are cleared to the CPU 70 of the lamp control board 37, and the stored contents of the RAM 104 are changed. When cleared, the CPU 102 of the main control board 44 sends a RAM clearing signal indicating that the stored contents of the RAM 104 are cleared to the CPU 70 of the lamp control board 37. That is, the RAM control signal from the payout control board 40 is first input to the lamp control board 37, and the RAM clear signal from the main control board 44 is input after about 1 second.

  When the CPU 70 of the lamp control board 37 receives the RAM clearing signal from the main control board 44, the LED 76 is lit in a predetermined color for a predetermined time to notify the outside that the stored contents of the RAM 104 and RAM 212 have been cleared. Simultaneously with the lighting of the LED 76, a sound such as "RAM has been cleared normally" is generated from the speaker 225. Accordingly, when the lighting of the LED 76 or the sound that the RAM is cleared from the speaker 225 is confirmed, the pressing operation of the RAM clear switch 60 may be released. In this embodiment, about 1 second after the LED 76 is turned on. A case where the pressing operation of the RAM clear switch 60 is canceled after the elapse of time is shown.

  In other words, in the present embodiment, the RAM clear switch 60 is pressed in a short time of about 3 seconds and executed only once, so that the RAM 104 of the main control board 44 and the RAM 212 of the payout control board 40 can be reliably stored. The contents can be cleared at once. In addition, since the timing of pressing the RAM clear switch 60 is guided by both display and voice, the probability that the operator fails to clear the RAM is reduced. Furthermore, since the speaker 225 is provided on the lamp control board 37 provided on the back surface of the gaming machine 1, the operator can hear the sound compared to the case where the speaker 113 provided on the surface of the existing gaming machine 1 is used. Easy (because the existing speaker 113 sounds on the surface of the gaming machine 1 so that the player can easily hear it).

  In the present embodiment, the dispensing control board 40 is activated about 1 second before the main control board 44 is activated, but the set time of 1 second is appropriately set in consideration of the time when the dispensing control board 40 starts up. (Preferably as short as possible). That is, this set time is preferably the shortest time that the payout control board 40 can stand up before the main control board 44 starts up and can receive a command from the main control board. It is preferable to set a time slightly longer than this time.

  In the present embodiment, the storage contents of the RAM 104 of the main control board 44 and the RAM 212 of the payout control board 40 are cleared at a time by using only one RAM clear switch 60. However, this is because the RAM 104 of the main control board 44 is cleared. Alternatively, separate (two) RAM clear switches for clearing the RAM 212 of the payout control board 40 may be provided on the power supply board 36.

  In this embodiment, the RAM 212 of the payout control board 40 is backed up in addition to the RAM 104 of the main control board 44 and the stored contents of the RAM 104 and RAM 212 can be cleared. In addition to or in addition to the RAM 212, the RAM of other sub-control boards (for example, the voice control board 38, the display control board 39, and the launch control board 42) is backed up and the stored contents of the RAM can be cleared. May be.

  In this embodiment, the speaker 225 is provided in addition to the 7-segment LED 75 and the LED 76 so that the timing of pressing the RAM clear switch 60 and the RAM being cleared are notified to the outside. Instead of the 7-segment LED 75 and the LED 76, the notification may be made only by the speaker 225, or the combination of the 7-segment LED 75 and the speaker 225 or the combination of the LED 76 and the speaker 225 may be used. Furthermore, these selections may be made freely selectable by the operator using a changeover switch or the like.

  Next, as described above, another embodiment of the delay process executed by the main control board 44 will be described in connection with an embodiment in which the RAM 212 of the payout control board 40 is backed up in addition to the RAM 104 of the main control board 44. . FIG. 16 is a flowchart showing a delay process of another embodiment executed by the main control board 44.

  When this delay process is started, the CPU 102 first sets a value corresponding to the delay time TA (8 seconds) in a general-purpose register or the like as the counter D in step S90. In step S91, the CPU 102 executes a process of decrementing (decrementing by 1) the value of the counter D. In step S92, the CPU 102 proceeds to step S92 and award balls and rental balls paid out from the prize ball payout device 41. As a result, the payout ball detection sensor 124 that counts the game balls is checked, and the process proceeds to step S93 where, based on the check result of the payout ball detection sensor 124, the number of unpaid total payout balls is actually stored. A payout ball number subtraction process for subtracting the award balls and rental balls that have been paid out is executed.

  Then, the process proceeds to step S94, where the CPU 102 determines whether or not the value of the counter D has become zero. If the value of counter D is not 0 (NO in step S94), CPU 102 executes the processing of steps S91 to S94 again, and this is repeated until the value of counter D becomes 0. If YES in step S94, that is, if the value of the counter D becomes 0, the CPU 102 determines that the delay time TA has elapsed and ends this delay processing. That is, in this delay process, the value (positive integer) set in the counter D in step S90 is substantially equal to the value obtained by dividing the delay time TA by the execution time of steps S91 to S94, and accordingly FIG. The delay time TA is created by software through the processing of steps S91 to S94 shown in FIG.

  Here, this delay process is characterized in that the check process of the payout ball detection sensor 124 in step S92 and the payout ball number subtraction process in step S93 are executed. This is because of the following reason. . In other words, when an unexpected power outage recovers and recovers, it is an important issue to settle unpaid prize balls and rental balls so as not to give a disadvantage to the player. 40, the RAM 212 of the payout control board 40 is also backed up. Based on the payout control board stored in the RAM 212 before the main control board 44 starts up, the payout control board 40 is backed up. There is a possibility that the drive control of the prize ball payout device 41 is performed by 40 and the payout control of the prize balls and the rental balls is performed.

  Therefore, in the delay process before the main control board 44 rises, if the check process of the payout ball detection sensor 124 in step S92 and the payout ball number subtraction process in step S93 are executed, the main control board 44 can be used even in such a case. It is possible to grasp the exact number of unpaid balls, so that the main control board 44 can appropriately execute the subsequent processing without causing any disadvantage to both the game arcade and the player.

  Further, another embodiment of the gaming machine 1 will be described with reference to FIG. FIG. 17 is a block diagram showing main circuit configurations of the main control board 44, the lamp control board 37, and the power supply board 36. In this embodiment, a sub CPU 250 is provided on the main control board 44. The sub CPU 250 receives a reset signal from a reset circuit 58 provided on the power supply board 36, and sets a reset time counter or the like by software. In this example, it is delayed for a predetermined time and sent to the reset terminals of the main control board 44 and the lamp control board 37, and the activation of the main control board 44 and the lamp control board 37 is delayed for a predetermined time. In the present embodiment, the description of the same configuration as described above is omitted.

  Referring to FIG. 17, reset circuit 58 is in a state where the main power supply voltage of power supply circuit 56 is still below predetermined voltage V1 at the time of recovery from power failure or when power switch 55 is turned on (when power is turned on). Then, a reset signal is sent to the reset terminal of the sub CPU 250 and the reset terminal of the CPU of the sub control boards 38, 39, 40, and 42 (a low level signal is output), while the main power supply voltage has risen above the predetermined voltage V1. At this time, the transmission of the reset signal is stopped (rising from a low level to a high level). The sub CPU 250 and the sub control boards 38, 39, 40, and 42 are activated when the reset signal transmission is stopped.

  Further, when a reset signal is sent from the reset circuit 58 (a low level signal is output), the sub CPU 250 allows the sub CPU 250 to pass through it as it is and input it to the reset terminals of the CPU 102 and CPU 70 of the main control board 44 and the lamp control board 37. On the other hand, when the reset signal transmission from the reset circuit 58 is stopped (rises from a low level to a high level), the reset signal is stopped after a predetermined time delay.

  When the sub CPU 250 is started after the reset signal is stopped, the sub CPU 250 executes program processing such as initialization similar to the initialization processing in step S22 in the power-on processing (FIG. 7) described above. When the program processing such as the initial setting is finished, the sub CPU 250 next executes a delay process similar to the delay process executed by the CPU 102 and the CPU 70 of the main control board 44 and the lamp control board 37 described above.

  FIG. 18 is a flowchart showing a delay process executed by the sub CPU 250. When this delay process is started, the sub CPU 250 first executes the processes of steps S100 to S102. The processing from step S100 to step S102 is the same processing as the delay processing (FIG. 12) executed by the CPU 70 of the lamp control board 37 described above. By executing these processing, the delay time TB (3 seconds) is reduced. Will be created by the software. That is, the sub CPU 250 can delay the apparent end time of the program processing such as the initial setting by the time TB by the processing of step S100 to step S102 of the delay processing executed after the program processing such as the initial setting. .

  Then, when the delay time TB is created by the processing of step S100 to step S102, the sub CPU 250 proceeds to step S103 and stops sending the reset signal to the reset terminal of the CPU 70 of the lamp control board 37 (from low level to high level). Stand up to the level). As a result, the lamp control board 37 is started with a delay of approximately the delay time TB after the power is turned on.

  When step S103 is completed, the sub CPU 250 proceeds to step S104, and sets a value corresponding to the delay time TD (5 seconds) in a general-purpose register or the like as the counter D here. The delay time TD is a time obtained by subtracting the delay time TB (3 seconds) from the delay time TA (8 seconds) created in the delay process (FIG. 8) executed by the main control board 44 described above.

  When step S104 is completed, the sub CPU 250 executes the processing of step S105 and step S106 in the same manner as the processing of step S101 and step S102, thereby creating the delay time TD (5 seconds) by software. . That is, the sub CPU 250 adds the time TB and the time TD to the apparent end time of the program processing such as initial setting by the processing of step S100 to step S106 of this delay processing executed after the program processing such as initial setting. Can be delayed by the set time (8 seconds).

  Then, when the delay time TD is created by the processing of step S104 to step S106, the sub CPU 250 proceeds to step S107 and stops sending the reset signal to the reset terminal of the CPU 102 of the main control board 44 (from low level to high level). Stand up to the level). As a result, the main control board 44 is started after being delayed by a time (8 seconds) obtained by adding the delay time TB and the delay time TD after the power is turned on. These relationships will be described with reference to FIG.

  FIG. 19 is a timing chart showing operation states of the main control board 44, the lamp control board 37, the RAM clear switch 60, and the sub CPU 250 when the power is turned on. When the power switch 55 is turned on and the gaming machine 1 is turned on, the sub CPU 250 sets a waiting time counter or the like by software after the reset signal transmission is stopped and started as described above. To set the delay time TB (3 seconds) and the delay time TD (5 seconds). That is, the lamp control board 37 is started about 3 seconds after the power is turned on, while the main control board 44 is about 5 seconds after the lamp control board 37 is started (about 8 seconds after the power is turned on). ) Seconds later.

  When the delay time TB (3 seconds) elapses, the lamp control board 37 displays “4” on the 7-segment LED 75, and “3” “2” “1” “0” every time 1 second elapses thereafter. Execute countdown display. Therefore, the time when “0” is displayed on the 7-segment LED 75 is about 1 second before the delay time TD (5 seconds) elapses. Accordingly, when a store clerk or the like of the game hall clears the RAM 104 of the main control board 44, the RAM clear switch 60 is pressed at the timing when “0” is displayed on the 7-segment LED 75 in accordance with the count-down display of the 7-segment LED 75. Just operate. When the delay time TD (5 seconds) elapses while the RAM clear switch 60 is pressed (while the RAM clear signal is continuously sent), the stored contents stored in the RAM 104 are stored. Cleared (initialized).

  As described above, in this embodiment, the sub CPU 250 is provided on the main control board 44, and when the sub CPU 250 is started upon receiving a reset signal transmission stop, after executing a program such as an actual initial setting, a waiting time counter by software Etc. is set to delay the end of program processing such as apparent initial setting by a predetermined time, thereby delaying the stop of reset signal transmission to the main control board 44 and the lamp control board 37. Yes. That is, only the sub CPU 250 delays the start timing of the main control board 44 and the lamp control board 37 after the power is turned on by a desired time.

  Therefore, according to the present embodiment having such a configuration, it is possible to create a plurality of delay times only by the sub CPU 250, so that it takes less time for development and delays compared to the case where the delay times are individually created. Time accuracy can be increased. In particular, by backing up the RAM of the sub control boards 38, 39, 40, and 42 other than the main control board 44 and the lamp control board 37, when the number of control boards to be cleared of RAM increases, only the sub CPU 250 is changed. It is easy to use. The sub CPU 250 may be provided on the sub control boards 37, 38, 39, 40, and 42 other than the main control board 44, or may be provided independently.

Next, the main correspondence between the configuration of the claims and the embodiment of the present invention will be described.
The main control means corresponds to the main control board 44, and the sub-control means is the sub-control board (lamp control board 37, sound control board 38, display control board 39, payout control board 40, launch control board 42. The power supply means corresponds to the power supply board 36, the delay means is the delay process shown in FIGS. 8 and 16 executed by the main control board 44, and the delay process shown in FIG. The storage means corresponds to the RAM 104, the backup power supply means corresponds to the backup power supply circuit 59, the clear switch corresponds to the RAM clear switch 60, and the storage erase means , Corresponding to the RAM clear switch circuit 61, the gaming machine corresponds to the gaming machine 1, the notification device is a 7 segment LED 75, a gaming effect lamp 5, the hold LED 25, the hold LED 26, and the speaker 225, the notification control means corresponds to the lamp control board 37, and the notification control delay processing means is the delay processing shown in FIG. Corresponds to the delay processing (steps S100 to S102) shown in FIG.

A push button type clear switch corresponds to the RAM clear switch 60.
Claim 3: The main control delay processing means corresponds to the delay processing shown in FIGS. 8 and 16 executed by the main control board 44 and the delay processing shown in FIG. 18 executed by the sub CPU 250 (steps S100 to S106). To do.

  Claim 4: The game medium payout device corresponds to the prize ball payout device 41, the payout control means corresponds to the payout control board 40, the payout storage means corresponds to the RAM 212, and is executed by the main control delay processing means. The predetermined program process corresponds to the delay process shown in FIG.

Claim 5: The fact that the notification control means is the sub-control means corresponds to the fact that the notification control means is the lamp control board 37.
Claim 6: The display device corresponds to the 7-segment LED 75, the game effect lamp 15, the hold LED 25, and the hold LED 26, the sound device corresponds to the speaker 225, and the predetermined notification mode is a countdown, a change from lighting to flashing It corresponds to the notification by.

  Claim 7: The provision of a plurality of notification modes is as follows. “The countdown display form is not limited to this, and any display form can be used as long as it is generally understandable. Alternatively, a display form such as counting up may be used, and in these cases, a display such as a liquid crystal display may be employed instead of the 7-segment LED 75. It is also possible to adopt a display form in which a plurality of LEDs are arranged side by side and are sequentially turned off or turned on to count down (or count up). This corresponds to the description that “the display form can be selected”.

  Claim 8: The notification device corresponds to the LED 76, the speaker 225, the game effect lamp 15, the hold LED 25, and the hold LED 26, and for notifying the notification device that the game information stored in the storage means has been deleted. This corresponds to turning on the LED 76, causing the speaker 225 to generate a sound “RAM has been cleared normally”, and changing the gaming effect lamp 15, the hold LED 25, and the hold LED 26 from blinking to lighting.

It is a front view showing game machine 1 of this embodiment. It is the schematic which shows the whole back surface of the game machine 1 of this embodiment. It is a block diagram which shows the main circuit structures of the game machine 1 of this embodiment. 3 is a block diagram illustrating main circuit configurations of a main control board 44, a lamp control board 37, and a power supply board 36 of the present embodiment. FIG. 6 is a timing chart showing the operating states of the main control board 44, the lamp control board 37, and the RAM clear switch 60 when the power is turned on according to the present embodiment. It is a flowchart which shows the power failure process which the main control board 44 of this embodiment performs. It is a flowchart which shows the power-on process which the main control board 44 of this embodiment performs. It is a flowchart which shows the delay process which the main control board 44 of this embodiment performs. It is a flowchart which shows the game control process which the main control board 44 of this embodiment performs. It is a flowchart which shows the power supply return process which the main control board 44 of this embodiment performs. It is a flowchart which shows the RAM clear alerting | reporting process which the lamp control board 37 of this embodiment performs. It is a flowchart which shows the delay process which the lamp control board 37 of this embodiment performs. 7 is a timing chart showing operation states of a main control board 44, a lamp control board 37, a game effect lamp 15, a hold LED 25, a hold LED 26, and a RAM clear switch 60 when power is turned on in another embodiment of the gaming machine 1; 4 is a block diagram showing main circuit configurations of a main control board 44, a payout control board 40, a lamp control board 37, and a power supply board 36 of another embodiment of the gaming machine 1. FIG. 6 is a timing chart showing operation states of a main control board 44, a payout control board 40, a lamp control board 37, and a RAM clear switch 60 when power is turned on in another embodiment of the gaming machine 1. It is a flowchart which shows the delay process which the main control board 44 of other embodiment of the gaming machine 1 performs. FIG. 6 is a block diagram showing main circuit configurations of a main control board 44, a lamp control board 37, and a power supply board 36 of another embodiment of the gaming machine 1. It is a flowchart which shows the delay process which sub CPU250 of other embodiment of the gaming machine 1 performs. 6 is a timing chart showing operation states of a main control board 44, a lamp control board 37, a RAM clear switch 60, and a sub CPU 250 when power is turned on in another embodiment of the gaming machine 1.

Explanation of symbols

1 ... game machine, 2 ... hit control handle,
3 ... Hitting ball guide rail, 4 ... Game area formation rail,
5 ... gaming area, 6 ... special symbol display (LCD),
7 ... Grand prize opening (Attacker), 8 ... Left symbol display section,
9 ... middle symbol display part, 10 ... right symbol display part,
11 ... Starting prize opening (electric tulip), 12 ... Hit ball supply tray,
13 ... Extra ball tray, 14 ... Ordinary prize opening,
15 ... Game effect lamp, 16 ... Out port,
17 ... Glass door frame, 18 ... Normal symbol display device (7-segment LED),
19 ... Normal symbol operation gate, 20 ... Windmill,
21 ... Game board, 22 ... Outer frame,
23 ... Inner frame, 24 ... Return ball prevention valve,
25 ... Hold LED, 26 ... Hold LED,
30 ... Control dedicated board, 36 ... Power supply board,
37 ... Lamp control board, 38 ... Audio control board,
39 ... Display control board, 40 ... Dispensing control board,
41 ... Prize ball dispensing device, 42 ... Launch control board,
43 ... Hitting ball launcher, 44 ... Main control board,
45 ... Terminal board, 50 ... Mechanism plate,
51 ... Sphere storage tank, 52 ... Tank rail,
53 ... opening, 55 ... power switch,
56 ... power supply circuit, 57 ... power supply monitoring circuit,
58 ... Reset circuit, 59 ... Backup power supply circuit,
60 ... RAM clear switch, 61 ... RAM clear switch circuit,
62 ... Delay circuit B, 63 ... DIP switch circuit,
70 ... CPU, 71 ... ROM,
72 ... RAM, 75 ... 7 segment LED,
76 ... LED, 78 ... Lamp / LED drive circuit,
101 ... Input circuit, 102 ... CPU,
103 ... ROM, 104 ... RAM,
106 ... Solenoid, 107 ... Solenoid,
109 ... External information terminal, 110 ... Output circuit,
113 ... Speaker, 115 ... Bus,
116 ... Starting winning detection sensor, 117 ... Count switch,
119 ... Hitting ball operation handle switch, 120 ... Hitting ball operation stop switch,
121 ... Actuation gate detection sensor, 122 ... Safe ball detection sensor,
123 ... Count switch, 124 ... Dispensing ball detection sensor,
210 ... CPU, 211 ... ROM,
212 ... RAM, 225 ... speaker,
250 ... sub CPU,
TA, TB, TC, TD ... Delay time

Claims (8)

Main control means for controlling the game;
Sub-control means for controlling various gaming devices based on command signals from the main control means;
Power supply means for generating and supplying predetermined operating power to the main control means and the sub-control means;
Delay means for starting up the main control means later than the sub-control means at the start of power supply from the power supply means;
Storage means for storing game information related to game control of the main control means;
Backup power supply means for supplying backup power to the storage means when power supply from the power supply means is interrupted;
A clear switch for outputting a clear signal to the main control means by turning on,
Based on the fact that the clear signal is input when the main control unit starts up, a memory erasing unit for erasing game information stored in the storage unit;
In a gaming machine equipped with
Comprising notification control means comprising a microcomputer or the like for informing a predetermined notification device of information relating to the timing of turning on the clear switch;
The notification control means is a notification control delay process for delaying a start timing of a program process executed after completion of initial setting at the start of power supply by executing a predetermined program process until a predetermined time before the main control means starts up. With means,
The notification control unit is configured to notify the notification device of information related to a timing for turning on the clear switch when a predetermined program process executed by the notification control delay processing unit is completed. Gaming machine.   The gaming machine according to claim 1, wherein the clear switch is a push button type that is turned on only while being pressed. The main control means and the sub control means each include a microcomputer,
The delay means executes a predetermined program process until a predetermined time elapses after the sub-control means is started, the start timing of the program process executed after the end of the initial setting in the main control means at the start of power supply. As the main control delay processing means to delay,
The notification control unit is configured to notify the information related to the timing of turning on the clear switch when the predetermined program processing executed by the notification control delay processing unit is completed. The gaming machine according to claim 1 or claim 2. A game medium payout device for paying out game media to a player;
The sub-control means includes payout control means for controlling the game medium payout device,
The payout control means includes payout storage means for storing information related to payout control,
The backup power supply means supplies power for backup to the payout storage means when power supply from the power supply means is interrupted,
4. The gaming machine according to claim 3, wherein the predetermined program processing executed by the main control delay processing means is processing for checking a payout number of game media paid out from the game media payout device.   The gaming machine according to claim 3 or 4, wherein the notification control means is the sub-control means.   The notification device is a display device and / or a sound device, and the notification control means notifies the display device or / and the sound device of a timing for turning on the clear switch in a predetermined notification mode. A gaming machine according to any one of claims 1 to 5, wherein the gaming machine is characterized in that:   The gaming machine according to claim 6, wherein a plurality of the notification modes are provided in advance, and a selection unit that can select a desired notification mode from the plurality of notification modes provided. When the game information stored in the storage means is erased by the storage erasure means, the main control means outputs a clear completion signal to the notification control means,
The said notification control means makes the said notification apparatus notify that the game information stored in the storage means has been deleted when the clearing signal is inputted. 8. The gaming machine according to any one of 7.

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