JP2003249525A - Manufacturing method for display panel - Google Patents

Manufacturing method for display panel

Info

Publication number
JP2003249525A
JP2003249525A JP2002049235A JP2002049235A JP2003249525A JP 2003249525 A JP2003249525 A JP 2003249525A JP 2002049235 A JP2002049235 A JP 2002049235A JP 2002049235 A JP2002049235 A JP 2002049235A JP 2003249525 A JP2003249525 A JP 2003249525A
Authority
JP
Japan
Prior art keywords
display panel
mounting
flexible wiring
wiring board
semiconductor elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002049235A
Other languages
Japanese (ja)
Inventor
Hikari Fujita
光 藤田
Tatsufumi Ogata
達文 尾形
Takeshi Ishigame
剛 石亀
Hiroyoshi Takezawa
浩義 竹澤
Naohiro Fukuda
尚宏 福田
Tsutomu Aida
勉 会田
Daijuro Takano
大樹郎 高野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002049235A priority Critical patent/JP2003249525A/en
Publication of JP2003249525A publication Critical patent/JP2003249525A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To mount a semiconductor element by preventing conduction failure due to peeled off paste or film thermosetting bonding agent and generation of air bubbles, etc., even if the bonding agent is cured. <P>SOLUTION: Semiconductor elements GD and SD are mounted on one substrate L1 of a display panel L comprising a pair of substrates, via a first anisotropic conductive film 6A in between. Then a flexible wiring substrate F is mounted at a place where the peripheral part of one substrate L1 of the display panel L and neighborhood of the place on which the semiconductor elements GD and SD are mounted, via a second anisotropic conductive film 6B in between. At this time, the flexible wiring substrate F is mounted within 20 hours after mounting the semiconductor elements GD and SD. The glass transition temperature of the second anisotropic conductive film 6B is made lower than that of the first anisotropic conductive film 6A. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、液晶パネル(liqu
id crystal display panel)やPDP(plasma display
panel)等の表示パネルの製造方法に関する。
TECHNICAL FIELD The present invention relates to a liquid crystal panel (liqu
id crystal display panel) and PDP (plasma display)
panel) and other display panel manufacturing methods.

【0002】[0002]

【従来の技術】近年、半導体素子の実装は、高密度化、
高品質化、薄型化が進行していることに伴い、TAB方
式(Tape Automated Bonding方式)からフリップチップ
方式(Flip Chip Bonding方式)に移行している。特に
液晶表示装置では薄型化、軽量化が要求されることか
ら、COG構造(Chip On Glass構造)における液晶駆
動用LSIの実装には高密度化、高品質化、薄型化が可
能なフリップチップ方式(Flip Chip Bonding方式)が
採用されている。フリップチップ方式とは、フェイスダ
ウン方式の一つであり、半導体素子上の接続電極を基板
またはパッケージの配線用電極に直接接続する方式であ
り、COGでは、異方性導電膜(ACF)などのペース
ト状若しくはフィルム状の接着剤を用いて突起電極(バ
ンプ)とガラス基板の配線用電極とを接続する。このC
OG(chip on glass)法は、PDP(plasma display
panel)等の表示パネルの製造方法にも使用されてい
る。ペースト状若しくはフィルム状の接着剤としては、
熱可塑性のものもあるが、近年、熱硬化性のものが多く
使用されている。
2. Description of the Related Art In recent years, mounting of semiconductor elements has been increased in density.
Along with the progress of higher quality and thinner devices, the TAB method (Tape Automated Bonding method) is being changed to the flip chip method (Flip Chip Bonding method). In particular, since liquid crystal display devices are required to be thin and lightweight, a flip chip method capable of achieving high density, high quality, and thinness in mounting a liquid crystal driving LSI in a COG structure (Chip On Glass structure) (Flip Chip Bonding method) is used. The flip chip method is one of face-down methods and is a method of directly connecting a connection electrode on a semiconductor element to a wiring electrode of a substrate or a package. In the COG, an anisotropic conductive film (ACF) or the like is used. The protruding electrodes (bumps) are connected to the wiring electrodes of the glass substrate using a paste or film adhesive. This C
The OG (chip on glass) method is based on PDP (plasma display).
It is also used in the manufacturing method of display panels such as. As a paste or film adhesive,
There are thermoplastics, but in recent years, thermosetting ones have been widely used.

【0003】 図9ないし図11に、COG法による半
導体素子GD,SDの接続を模式的に示す。液晶表示パ
ネルLにおけるCOG法は、一対のガラス基板の一方基
板L1に半導体素子GD,SDをフェイスダウンにて直
接接続する方法であり、接続方法の一つとして、半導体
素子GD,SDの突起電極(バンプ)4a,4bと一方
のガラス基板L1に形成された配線用電極端子11,1
2とを対向させて、異方性導電樹脂膜(Anisotropic C
onductive Film;ACF)6を介して加熱圧着により
接続される方法がある。図11は実装に使用される装置
である。ACF6は、樹脂製の接着剤フィルムに導電性
粒子6cを分散させたものであり、加熱及び加圧によ
り、半導体素子GD,SDの突起電極(バンプ)4a,
4bと一方の基板L1上の電極端子11,12との間
に、導電性粒子6cが挟まれて接触することによって、
電気的導通が得られ、ACF6が硬化することにより半
導体素子GD,SDが一方基板L1に接着される。実装
方法は、図11に示す装置により、一方のガラス基板L
1を固定ステージS2上に固定し、実装領域にACF6
を貼付けし、半導体素子GD,SDやフレキシブル配線
基板Fを位置合わせしてその上方から昇降動する加熱ツ
ールS3により加熱及び加圧して行われる。このよう
に、モジュール化工程においては、半導体素子SD,G
DがACF6を介して実装されるとともに、一方の基板
L1の外周端縁にフレキシブル配線基板FがACF6を
介して配設され、液晶表示装置として製造される。
9 to 11 schematically show the connection of the semiconductor devices GD and SD by the COG method. The COG method in the liquid crystal display panel L is a method in which the semiconductor elements GD and SD are directly connected face down to the one substrate L1 of the pair of glass substrates. One of the connection methods is the protruding electrodes of the semiconductor elements GD and SD. (Bumps) 4a, 4b and wiring electrode terminals 11, 1 formed on one glass substrate L1
2 and the anisotropic conductive resin film (Anisotropic C
There is a method of connecting by thermocompression bonding via an onductive film (ACF) 6. FIG. 11 shows an apparatus used for mounting. The ACF 6 is obtained by dispersing conductive particles 6c in a resin adhesive film, and by heating and pressurizing, the protruding electrodes (bumps) 4a of the semiconductor elements GD, SD,
4b and the electrode terminals 11 and 12 on the one substrate L1 are sandwiched and brought into contact with the conductive particles 6c,
Electrical conduction is obtained, and the ACF 6 is cured to bond the semiconductor elements GD and SD to the one substrate L1. The mounting method is as shown in FIG.
1 is fixed on the fixed stage S2, and the ACF6 is mounted on the mounting area.
Is attached, the semiconductor elements GD, SD and the flexible wiring board F are aligned and heated and pressed by a heating tool S3 which moves up and down from above. Thus, in the modularization process, the semiconductor devices SD, G
The D is mounted via the ACF 6, and the flexible wiring board F is disposed on the outer peripheral edge of the one substrate L1 via the ACF 6 to manufacture a liquid crystal display device.

【0004】[0004]

【発明が解決しようとする課題】ところで、従来、半導
体素子SD,GDを実装した後は、半導体素子SD,G
Dの駆動状態の検査(通電検査)を行い、その後フレキ
シブル配線基板Fの実装工程が行われている。半導体素
子SD,GDの駆動状態の検査としては、検査機器を使
用した検査の前に目視による検査が行われることもあ
る。また、半導体素子SD,GDを実装した後は、例え
ば製造現場(工場)が休日(土曜日、日曜日)を挟むよ
うな場合は、休日空けにフレキシブル配線基板Fの実装
が行われたり、半導体素子SD,GDの通電検査を行っ
てからフレキシブル配線基板Fの実装が行われたりして
おり、半導体素子GD,SDの実装とフレキシブル配線
基板Fの実装との間に2〜3日かかる待機状態におかれ
ることがある。
By the way, conventionally, after the semiconductor elements SD and GD are mounted, the semiconductor elements SD and G are not mounted.
A drive state inspection of D (energization inspection) is performed, and then a mounting process of the flexible wiring board F is performed. As the inspection of the driving states of the semiconductor elements SD and GD, visual inspection may be performed before the inspection using the inspection device. Further, after mounting the semiconductor elements SD and GD, for example, when the manufacturing site (factory) includes holidays (Saturday and Sunday), the flexible wiring board F is mounted on holidays and the semiconductor elements SD are mounted. , The flexible wiring board F is mounted after conducting the energization inspection of GD, and in a standby state in which it takes 2 to 3 days between the mounting of the semiconductor elements GD and SD and the mounting of the flexible wiring board F. There is a chance

【0005】しかしながら、半導体素子GD,SDの実
装後フレキシブル配線基板Fの実装までに長時間経過し
た場合、半導体素子GD,SDのCOG接続部(特に半
導体素子GD,SDの両端部)の導通不具合が生じる問
題を有していた。すなわち、半導体素子GD,SD側の
ACF6が硬化収縮して、半導体素子GD,SDに収縮
応力が加わり(図6(a)中符号f1)、その応力に応
じて一方の基板L1に反りが生じる(凹状に歪みが生じ
る)が、長時間経過後にフレキシブル配線基板Fを実装
すると、ACF6等の硬化状態が完全な安定状態に達し
てしまうことから、図11に示す装置の圧着ヘッドS3
による押圧力がフレキシブル配線基板Fに対する無理な
応力(上記反りを戻そうとする反力であり、この応力は
一方の基板L1を平板状態にする力(符号f2)でもあ
る)として働き(図6(b))、硬化したペースト状若
しくはフィルム状の熱硬化性接着剤が剥がれて隙間が生
じたり気泡が生じたりする事態が生じる(図7
(a))。また、ACF6の導電性粒子6cは、図11
の装置の熱圧着により上記配線電極端子11,12とバ
ンプ4a,4bに圧力による導電性粒子6cの痕跡(以
下「圧痕」という)が生じるが、この圧痕が失われる事
態が生じる。通電検査では、この圧痕の数を数えること
で行われるが、圧痕が失われると導通不具合の原因とな
る。これらにより、半導体素子GD,SDのCOG接続
部(特に半導体素子GD,SDの両端部)の導通不具合
が生じる問題を有していた。
However, when a long time elapses after the mounting of the semiconductor elements GD and SD until the mounting of the flexible wiring board F, the COG connection portions of the semiconductor elements GD and SD (particularly both ends of the semiconductor elements GD and SD) have a conduction defect. Had a problem that occurs. That is, the ACF 6 on the semiconductor element GD, SD side cures and shrinks, and a shrinkage stress is applied to the semiconductor elements GD, SD (reference numeral f1 in FIG. 6A), and one substrate L1 warps according to the stress. However, when the flexible wiring board F is mounted after a long time has passed, the cured state of the ACF 6 or the like reaches a completely stable state. Therefore, the pressure bonding head S3 of the apparatus shown in FIG.
The pressing force due to acts as an unreasonable stress on the flexible wiring board F (a reaction force for returning the warp, and this stress is also a force (symbol f2) for making one board L1 into a flat plate state) (FIG. 6). (B)) The cured paste-like or film-like thermosetting adhesive may be peeled off to form a gap or bubbles (FIG. 7).
(A)). In addition, the conductive particles 6c of the ACF 6 are as shown in FIG.
The thermocompression bonding of the device causes a trace of the conductive particles 6c (hereinafter referred to as "indentation") due to the pressure on the wiring electrode terminals 11 and 12 and the bumps 4a and 4b, but this indentation occurs. The energization inspection is performed by counting the number of indentations, but if the indentations are lost, it causes a conduction failure. As a result, there is a problem in that a COG connection portion of the semiconductor elements GD and SD (particularly both ends of the semiconductor elements GD and SD) causes a conduction failure.

【0006】なお、フレキシブル配線基板Fは、上記応
力等により平板状態が失われていても柔軟に(フレキシ
ブルに)対応するが、フレキシブル配線基板Fの熱圧着
による実装も平板状態で実装されることが表示パネルの
製造に理想的な実装として求められる。
The flexible wiring board F can flexibly (flexibly) even if the flat plate state is lost due to the stress or the like, but the flexible wiring board F can be mounted in the flat plate state by thermocompression bonding. Is required as an ideal mounting for display panel manufacturing.

【0007】そこで本発明の目的は、ペースト状若しく
はフィルム状の熱硬化性接着剤が硬化してもこの接着剤
が剥がれたり気泡が生じたりする等による導通不具合を
生じさせないようにして半導体素子を実装することを可
能とし、実装精度の高い表示パネルを製造する表示パネ
ルの製造方法を提供することにある。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor element by preventing a conductive failure due to peeling of the adhesive or generation of air bubbles even when the paste or film thermosetting adhesive is cured. An object of the present invention is to provide a method of manufacturing a display panel that enables mounting and that manufactures a display panel with high mounting accuracy.

【0008】[0008]

【課題を解決するための手段】上記課題を解決するため
に、本発明の請求項1記載の表示パネルの製造方法は、
一対の基板を有する表示パネルの一方の基板にペースト
状若しくはフィルム状の熱硬化性接着剤を介して半導体
素子を実装した後、表示パネルの一方の基板の周辺部で
あって半導体素子が実装される近傍にペースト状若しく
はフィルム状の熱硬化性接着剤を介してフレキシブル配
線基板を実装する表示パネルの製造方法において、上記
半導体素子を実装した後20時間以内にフレキシブル配
線基板を実装することを特徴とする。
In order to solve the above problems, a method of manufacturing a display panel according to claim 1 of the present invention comprises:
After mounting a semiconductor element on one substrate of a display panel having a pair of substrates via a paste-shaped or film-shaped thermosetting adhesive, the semiconductor element is mounted on the peripheral portion of one substrate of the display panel. In a method of manufacturing a display panel, in which a flexible wiring board is mounted in the vicinity of a substrate through a paste or film thermosetting adhesive, the flexible wiring board is mounted within 20 hours after mounting the semiconductor element. And

【0009】この発明によれば、半導体素子の実装の
際、熱硬化性接着剤が硬化収縮して、半導体素子に収縮
応力が加わり、表示パネルの一方の基板に反りが生じる
が、上記半導体素子を実装した後20時間以内にフレキ
シブル配線基板を実装すると、接着剤の硬化状態が完全
な安定状態に達していないために、フレキシブル配線基
板を熱圧着する際に既に実装された半導体素子の接着剤
が剥がれたり気泡が生じたり圧痕が失われるようなこと
がなく、表示パネルの一方の基板の平板状態を維持しつ
つ信頼性の高い接着効果が得られる。
According to the present invention, when the semiconductor element is mounted, the thermosetting adhesive cures and shrinks, and a shrinkage stress is applied to the semiconductor element, so that one substrate of the display panel warps. When the flexible wiring board is mounted within 20 hours after mounting, the cured state of the adhesive has not reached a completely stable state. Therefore, when the flexible wiring board is thermocompression-bonded, the adhesive of the semiconductor element already mounted is mounted. It is possible to obtain a highly reliable adhesive effect while maintaining the flat plate state of one substrate of the display panel without peeling off, generation of bubbles or loss of indentation.

【0010】本発明の請求項2記載の表示パネルの製造
方法は、請求項1記載の発明を前提に、前記半導体素子
を実装するときの熱硬化性接着剤のガラス転移温度より
もフレキシブル配線基板を実装するときの熱硬化性接着
剤のガラス転移温度の方が低いことを特徴とする。
According to a second aspect of the present invention, the method for manufacturing a display panel is based on the first aspect of the invention, and the flexible wiring board is higher than the glass transition temperature of the thermosetting adhesive when the semiconductor element is mounted. Is characterized in that the glass transition temperature of the thermosetting adhesive when mounting is lower.

【0011】この発明によれば、前記半導体素子を実装
するときの熱硬化性接着剤のガラス転移温度よりもフレ
キシブル配線基板を実装するときの熱硬化性接着剤のガ
ラス転移温度の方が低いことから、フレキシブル配線基
板を熱圧着するときの熱による影響が既に実装された半
導体素子の接着剤に伝達し難くなり(熱的影響を与え難
くなり)、信頼性の高い接着効果が得られる。
According to the present invention, the glass transition temperature of the thermosetting adhesive when mounting the flexible wiring board is lower than the glass transition temperature of the thermosetting adhesive when mounting the semiconductor element. Therefore, the influence of heat when the flexible wiring board is thermocompression-bonded is hard to be transmitted to the adhesive of the semiconductor element already mounted (hard to exert a thermal influence), and a highly reliable adhesive effect is obtained.

【0012】本発明の請求項3記載の表示パネルの製造
方法は、請求項1又は請求項2記載の発明を前提とし
て、前記半導体素子を実装した後フレキシブル配線基板
を実装する間に、半導体素子の通電検査工程を介在させ
ないことを特徴とする。
A method of manufacturing a display panel according to a third aspect of the present invention is based on the invention of the first or second aspect, and after mounting the semiconductor element, while mounting the flexible wiring board, the semiconductor element is mounted. It is characterized in that the energization inspection process of is not involved.

【0013】従来の表示パネルの工程では、半導体素子
を実装した後は、その半導体素子の通電検査を行い、そ
の後フレキシブル配線基板の実装工程が行われていた
が、この発明によれば、半導体素子の通電検査工程を介
在させないために、必然的にフレキシブル配線基板の実
装が早くなり、半導体素子の実装の際のペースト状若し
くはフィルム状の熱硬化性接着剤が剥がれたり気泡が生
じたりする等による導通不具合を生じさせないようにし
てフレキシブル配線基板を熱圧着することが可能にな
る。
In the conventional display panel process, after the semiconductor element is mounted, the semiconductor element is inspected for electricity, and then the flexible wiring board mounting step is carried out. Since it does not involve the energization inspection process, the flexible wiring board will inevitably be mounted quickly, and the paste-like or film-like thermosetting adhesive will be peeled off or bubbles will be generated when mounting the semiconductor element. The flexible wiring board can be thermocompression-bonded without causing a conduction failure.

【0014】[0014]

【発明の実施の形態】以下に、本発明の一実施の形態を
図面に基づいて説明する。
BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

【0015】(第1の実施の形態)本実施の形態は、図
1及び図2に示すように、液晶層を挟持する一対の基板
の一方にドライバ素子(半導体素子)を直接実装するC
OG実装に本発明を適用したもので、液晶表示パネルL
の一方の基板L1に、液晶表示パネルLを駆動させる半
導体素子GD,SDとフレキシブル配線基板Fが実装さ
れている。液晶表示パネルLは、フレキシブル配線基板
Fから半導体素子GD,SDに電源や信号の供給が行わ
れ、液晶表示パネルL内に半導体素子GD,SDから電
源や信号の供給が行われる。半導体素子GD,SDは、
駆動用ドライバ(Driver IC、DriverLSI)と呼ばれ、液
晶表示パネルLに縦横に配される信号線と走査線に各々
連結されているソースドライバSDとゲートドライバG
Dである。
(First Embodiment) In this embodiment, as shown in FIGS. 1 and 2, a driver element (semiconductor element) is directly mounted on one of a pair of substrates sandwiching a liquid crystal layer.
The present invention is applied to OG mounting, and a liquid crystal display panel L
The semiconductor elements GD and SD for driving the liquid crystal display panel L and the flexible wiring substrate F are mounted on the one substrate L1. In the liquid crystal display panel L, power and signals are supplied from the flexible wiring board F to the semiconductor elements GD and SD, and power and signals are supplied from the semiconductor elements GD and SD in the liquid crystal display panel L. The semiconductor elements GD and SD are
A source driver SD and a gate driver G, which are called driver ICs (Driver ICs), are respectively connected to the signal lines and the scanning lines vertically and horizontally arranged on the liquid crystal display panel L.
It is D.

【0016】液晶表示パネルLの上下一対の基板L1,
L2は、各々短冊状のもので、下方の第1の基板(一方
基板、AM基板)L1と上方の第2の基板L2が平行に
配され、この第1の基板L1と第2の基板L2との間に
液晶3を封入して形成されている。符号7A,7Bは、
入射光に対して特定の偏光のみを透過させる機能を有す
る光学部材である偏光板であり、本実施の形態では液晶
表示パネルLの最表面と最裏面に2枚配されている。こ
のような構成の液晶表示装置は、2枚偏光板方式と呼ば
れるが、1枚偏光板方式のものもある。
A pair of upper and lower substrates L1 of the liquid crystal display panel L1,
Each of L2 is a strip shape, and a lower first substrate (one substrate, AM substrate) L1 and an upper second substrate L2 are arranged in parallel, and the first substrate L1 and the second substrate L2 are arranged. And the liquid crystal 3 is sealed between them. Reference numerals 7A and 7B are
It is a polarizing plate which is an optical member having a function of transmitting only specific polarized light with respect to incident light. In this embodiment, two polarizing plates are provided on the outermost surface and the outermost surface of the liquid crystal display panel L. The liquid crystal display device having such a structure is called a two-sheet polarizing plate system, but there is also a one-sheet polarizing plate system.

【0017】第1の基板L1は、第2の基板L2よりも
大きく形成され、このため両基板L1,L2を重ね合わ
せると、AM基板L1の外周縁部に一部張り出した半導
体素子GD,SDの実装領域L6が形成されている。第
1の基板L1の半導体素子側表面(上面)には、アルミ
ニウム(Al)などによる電極11,12が配設されて
いる。電極11(図1中左)は入力電極であり、電極1
2(図1中右)は出力電極である。
The first substrate L1 is formed larger than the second substrate L2. Therefore, when the two substrates L1 and L2 are superposed on each other, the semiconductor elements GD and SD partially projecting to the outer peripheral edge of the AM substrate L1. Mounting region L6 is formed. Electrodes 11 and 12 made of aluminum (Al) or the like are provided on the surface (upper surface) of the first substrate L1 on the semiconductor element side. Electrode 11 (left in FIG. 1) is an input electrode, and electrode 1
Reference numeral 2 (right in FIG. 1) is an output electrode.

【0018】実装領域L6には、半導体実装用の配線パ
ターンP1が形成されるとともに、複数の半導体素子G
D,SDが本発明の実装方法によって搭載されている。
また、液晶表示パネルL側には、配線パターンP2が形
成され、フレキシブル配線基板Fの裏面側には配線パタ
ーンP3が形成されている。
In the mounting region L6, a wiring pattern P1 for semiconductor mounting is formed and a plurality of semiconductor elements G are formed.
D and SD are mounted by the mounting method of the present invention.
A wiring pattern P2 is formed on the liquid crystal display panel L side, and a wiring pattern P3 is formed on the back surface side of the flexible wiring board F.

【0019】配線パターンP1は、半導体素子GD,S
D(駆動ドライバ)への信号の供給や電源供給を行う配
線群(バス配線)であり、AM基板(AM−LCD)L
1では、一方の基板L1に成膜される薄膜トランジスタ
(TFT)等のスイッチング素子の成膜工程で同時にパ
ターン形成が可能なものである。本実施の形態の配線パ
ターンP1は、アルミニウム製材料をスパッタリングで
膜厚0.1〜0.2μmに成膜した後、フォトリソグラ
フィでパターンニングして形成されている。半導体素子
GD,SDには、金(Au)や銀(Ag)などを材質と
する複数の電極突起(バンプ)4a,4bが形成され、
この電極突起4a,4bは、異方性導電膜(ACF)6
Aの導電性粒子6cを介して上記配線パターンP1と電
気的に接続されている。
The wiring pattern P1 is composed of semiconductor elements GD and S.
A wiring group (bus wiring) for supplying signals and power to D (driving driver), and an AM substrate (AM-LCD) L
In No. 1, pattern formation is possible at the same time in a film formation process of a switching element such as a thin film transistor (TFT) formed on one substrate L1. The wiring pattern P1 of the present embodiment is formed by forming a film of aluminum material by sputtering to a film thickness of 0.1 to 0.2 μm and then patterning by photolithography. A plurality of electrode protrusions (bumps) 4a, 4b made of gold (Au), silver (Ag) or the like are formed on the semiconductor elements GD, SD,
The electrode protrusions 4a and 4b are formed by an anisotropic conductive film (ACF) 6
It is electrically connected to the wiring pattern P1 through the conductive particles 6c of A.

【0020】フレキシブル配線基板Fは、実装領域L6
において表示パネルの一方の基板(第1の基板)L1の
周辺部であって半導体素子GD,SDが実装される近傍
位置に配設されている。つまり、四角形状の第1の基板
L1の二辺1a,1bの外周縁部には、フレキシブル配
線基板Fが実装されている。このフレキシブル配線基板
Fは、ポリイミド等の合成樹脂材料で構成され、片側の
実装領域L6側が多数の凹凸形状に形成され、このうち
の凸形状の部分Faが第1の基板L1の外周縁部に沿う
ようにして実装配設されている。具体的には、図2に示
すように、前記片側の実装領域L6側が多数の凹凸形状
に形成されたフレキシブル配線基板Fを、このうちの凸
形状の部分Faを半導体素子GD,SDの位置近傍にお
いて実装させている。半導体素子GD,SDの側面から
フレキシブル配線基板Fの位置までの距離Hは、通常
0.3mmから1mmの範囲に設定されることが多い。
The flexible wiring board F has a mounting area L6.
In the peripheral portion of one substrate (first substrate) L1 of the display panel in the vicinity of where the semiconductor elements GD and SD are mounted. That is, the flexible wiring board F is mounted on the outer peripheral edge portions of the two sides 1a and 1b of the quadrangular first board L1. This flexible wiring board F is made of a synthetic resin material such as polyimide, and one side of the mounting region L6 side is formed into a large number of concave and convex shapes, of which the convex portion Fa is the outer peripheral edge portion of the first substrate L1. It is mounted and arranged along the line. Specifically, as shown in FIG. 2, a flexible wiring board F having a large number of concavo-convex shapes on one side of the mounting region L6 is used, and a convex portion Fa of the flexible wiring board F is located near the positions of the semiconductor elements GD and SD. It is implemented in. The distance H from the side surfaces of the semiconductor elements GD and SD to the position of the flexible wiring board F is usually set in the range of 0.3 mm to 1 mm.

【0021】次に、上記表示パネルの製造方法について
説明する。液晶表示パネルLは、図3に示すように、可
動ステージS1により搬送されて、液晶表示パネルLの
実装領域L6が固定ステージS2上に置かれる。この固
定ステージS2上には、圧着ヘッドS3が昇降動作可能
に配置されている。固定ステージS2や圧着ヘッドS3
には、加熱用のヒーターが内蔵され、半導体素子SD,
GDの熱圧着に使用される。半導体素子GD,SDの吸
着手段は圧着ヘッドS3が兼ねており、圧着ヘッドS3
や固定ステージS2の加熱及び加圧時間、加熱温度、加
圧力は、コントロール制御されている。
Next, a method of manufacturing the above display panel will be described. As shown in FIG. 3, the liquid crystal display panel L is transported by the movable stage S1 and the mounting area L6 of the liquid crystal display panel L is placed on the fixed stage S2. A pressure bonding head S3 is arranged on the fixed stage S2 so that it can be moved up and down. Fixed stage S2 and pressure bonding head S3
Has a built-in heater for heating the semiconductor element SD,
Used for thermocompression bonding of GD. The crimping head S3 also serves as a suction means for the semiconductor elements GD and SD.
The heating and pressurizing time, the heating temperature, and the pressure of the fixed stage S2 are controlled and controlled.

【0022】そして、表示パネルLの一方の基板L1
に、以下のようにして、ペースト状若しくはフィルム状
の熱硬化性接着剤(第1の異方性導電膜(ACF))6
Aを介して半導体素子GD,SDを実装した後の所定時
間以内に、フレキシブル配線基板Fをペースト状若しく
はフィルム状の熱硬化性接着剤(第2の異方性導電膜
(ACF))6Bを介して実装する。ここで、半導体素
子GD,SDを実装するときのペースト状若しくはフィ
ルム状の熱硬化性接着剤(第1の異方性導電膜(AC
F))6Aは、そのガラス転移温度Tgがフレキシブル
配線基板Fを実装するときのペースト状若しくはフィル
ム状の熱硬化性接着剤(第1の異方性導電膜(AC
F))6Bのガラス転移温度Tgよりも高いものを使用
することが好ましい。フレキシブル配線基板Fを熱圧着
するときの熱による影響が既に実装された半導体素子G
D,SDの熱硬化性接着剤6Aに伝達する熱的影響を与
え難くするためである。
Then, one substrate L1 of the display panel L
Then, a paste or film thermosetting adhesive (first anisotropic conductive film (ACF)) 6 was prepared as follows.
Within a predetermined time after mounting the semiconductor elements GD, SD via A, the flexible wiring board F is coated with a paste or film thermosetting adhesive (second anisotropic conductive film (ACF)) 6B. To implement via. Here, when the semiconductor elements GD and SD are mounted, a paste-like or film-like thermosetting adhesive (first anisotropic conductive film (AC
F)) 6A is a paste-like or film-like thermosetting adhesive (first anisotropic conductive film (AC) having a glass transition temperature Tg for mounting the flexible wiring board F).
F)) It is preferable to use one having a glass transition temperature Tg higher than 6B. The effect of heat when the flexible wiring board F is thermocompression bonded is already mounted on the semiconductor element G.
This is because it is difficult to give a thermal influence to the thermosetting adhesive 6A of D and SD.

【0023】ペースト状若しくはフィルム状の熱硬化性
接着剤である異方性導電膜(Anisotropic Conductive F
ilm:ACF)6A,6Bは、絶縁性を有する接着剤中に導
電性粒子6cが分散され厚み方向(接続方向)に導電性
を有し、面方向(横方向)に絶縁性を有するもので、導
電性粒子6cと接着剤から構成される。その接続は基本
的には加熱圧着であり、導電性粒子6cが電気接続の機
能を担当し、接着剤が圧接状態を保持する機能を担当す
る。
Anisotropic Conductive F which is a paste or film thermosetting adhesive.
ilm: ACF) 6A, 6B has conductive particles 6c dispersed in an insulating adhesive, has conductivity in the thickness direction (connection direction), and has insulation in the surface direction (lateral direction). , Conductive particles 6c and an adhesive. The connection is basically thermocompression bonding, the conductive particles 6c are responsible for the function of electrical connection, and the adhesive is responsible for the function of maintaining the pressed state.

【0024】異方性導電膜(例えば、日立化成(株)
製)6A,6Bは、直径3μmから10μm程度の導電
性粒子6cの表面に絶縁性薄膜樹脂をコートするもの
で、接続方向では圧着力で破壊され下層の金属薄膜と電
極が接触して導通し、横方向では破壊されず導電性粒子
6c同士が接触しても絶縁性が保たれるようになってい
る。また、異方性導電膜6A,6Bは、液晶表示パネル
Lに貼り付ける前は両面テープのような構成で供給さ
れ、液晶表示パネルLに接着剤層側を貼り付けた後、セ
パレータを剥がし接着剤層を露出させ、その後、半導体
素子GD,SDを実装(加熱加圧)し、半導体素子G
D,SD部の接着剤を硬化させ、本来の接着力を得る。
セパレータは、異方性導電膜6A,6Bの保護シートと
しての役割をも有する。絶縁性薄膜樹脂としては、ポリ
テトラフルオロエチレンやPET(poly-ethylene tere
phthalate resin)が使用されている。接着剤として
は、熱硬化性樹脂が使用されている。導電性粒子6cに
は、高分子球の表面に金属薄膜をメッキしたものもあ
る。なお、絶縁性薄膜樹脂がない導電粒子をここで使用
することも可能である。また、ペースト状若しくはフィ
ルム状の熱硬化性接着剤6としては、導電性接着剤(導
電性ペースト)であっても良い。接着剤としては、熱可
塑性樹脂のものもあるが、近年、熱硬化性のものが多く
使用されている。
Anisotropic conductive film (for example, Hitachi Chemical Co., Ltd.)
6A, 6B is for coating an insulating thin film resin on the surface of the conductive particles 6c having a diameter of about 3 μm to 10 μm. In the lateral direction, the insulating property is maintained even if the conductive particles 6c come into contact with each other without being broken. The anisotropic conductive films 6A and 6B are supplied in a structure such as a double-sided tape before being attached to the liquid crystal display panel L, and after the adhesive layer side is attached to the liquid crystal display panel L, the separator is peeled off and adhered. The agent layer is exposed, and then the semiconductor elements GD and SD are mounted (heated and pressed) to form the semiconductor element G.
The adhesive in the D and SD parts is cured to obtain the original adhesive force.
The separator also serves as a protective sheet for the anisotropic conductive films 6A and 6B. As the insulating thin film resin, polytetrafluoroethylene or PET (poly-ethylene tere
phthalate resin) is used. A thermosetting resin is used as the adhesive. As the conductive particles 6c, there is one in which a metal thin film is plated on the surface of a polymer sphere. In addition, it is also possible to use conductive particles without the insulating thin film resin here. The paste or film thermosetting adhesive 6 may be a conductive adhesive (conductive paste). Some adhesives include thermoplastic resins, but in recent years, thermosetting adhesives have been widely used.

【0025】まず、半導体素子GD,SDを実装すると
き、固定ステージS2上の第1の基板L1の実装領域L
6に第1の異方性導電膜(ACF)6Aを貼着させ(仮
止め工程)、半導体素子GD,SDの突起電極4a,4
bと配線パターンP1,P2の電極11,12が接触す
るように位置合わせする(アライメント工程)。その
後、所定の温度に加熱した圧着ヘッドS3と固定ステー
ジS2とにより半導体素子GD,SDを熱圧着する(本
圧着工程)。つまり、半導体素子GD,SDを吸着した
圧着ヘッドS3を昇降動作させて熱圧着させる。ゲート
ドライバGDとソースドライバSDの実装位置は異なる
が、可動ステージS1を可動させて固定ステージS2上
に液晶表示パネルLの一辺1aと他の一辺1bを載置さ
せることとなる。なお、半導体素子GD,SDの圧着に
は、液晶表示パネルLの一辺を多数の圧着ヘッドで同時
に圧着する多ヘッド一括圧着や、液晶表示パネルLの一
辺を1個の圧着ヘッドで同時に圧着する一括圧着等があ
る。
First, when mounting the semiconductor elements GD and SD, the mounting area L of the first substrate L1 on the fixed stage S2 is mounted.
The first anisotropic conductive film (ACF) 6A is adhered to 6 (temporary fixing step), and the protruding electrodes 4a, 4 of the semiconductor elements GD, SD are attached.
Positioning is performed so that b and the electrodes 11 and 12 of the wiring patterns P1 and P2 are in contact with each other (alignment step). Then, the semiconductor elements GD and SD are thermocompression bonded by the pressure bonding head S3 and the fixed stage S2 heated to a predetermined temperature (main pressure bonding step). That is, the pressure bonding head S3 that has attracted the semiconductor elements GD and SD is moved up and down to perform thermocompression bonding. Although the mounting positions of the gate driver GD and the source driver SD are different, the movable stage S1 is moved to place one side 1a and the other side 1b of the liquid crystal display panel L on the fixed stage S2. For the pressure bonding of the semiconductor devices GD and SD, a multi-head batch bonding in which one side of the liquid crystal display panel L is simultaneously pressed by a large number of pressure bonding heads, or a batch bonding in which one side of the liquid crystal display panel L is simultaneously pressed by a single pressure bonding head. There is crimping etc.

【0026】上記のように半導体素子GD,SDが熱圧
着された後は、少なくとも20時間以内にフレキシブル
配線基板Fを第1の基板L1の二辺1a,1bの縁部に
第2の異方性導電膜6Bを介して熱圧着する。具体的に
は、固定ステージS2上に第1の基板L1に第2の異方
性導電膜(ACF)6Bを貼着させ(仮止め工程)、フ
レキシブル配線基板Fの配線P3の電極と第1の基板L
1の配線パターンP1の電極が接触するように位置合わ
せし(アライメント工程)、その後、所定の温度に加熱
した圧着ヘッドS3と固定ステージS2とによりフレキ
シブル配線基板Fを熱圧着する(本圧着工程)。この熱
圧着によって、半導体素子GD,SDとフレキシブル配
線基板Fとが第1の異方性導電膜(ACF)6Aと第2
の異方性導電膜6Bを介して電気的に接続されるため
に、この状態で通電検査を行う。つまり、半導体素子を
実装した後に行われていた従来の通電検査は行わないよ
うにする。ただし、上記半導体素子GD,SDを実装し
た後20時間以内にフレキシブル配線基板Fを実装する
ものであれば、半導体素子GD,SDの駆動状態の検査
(通電検査)を行い、その後フレキシブル配線基板Fの
実装工程が行われても良い。
After the semiconductor elements GD and SD have been thermocompression bonded as described above, the flexible wiring board F is secondly anisotropically attached to the edges of the two sides 1a and 1b of the first board L1 within at least 20 hours. Thermocompression bonding is performed via the conductive film 6B. Specifically, the second anisotropic conductive film (ACF) 6B is attached to the first substrate L1 on the fixed stage S2 (temporary fixing step), and the electrodes of the wiring P3 of the flexible wiring substrate F and the first Board L
Positioning is performed so that the electrodes of the first wiring pattern P1 are in contact with each other (alignment step), and then the flexible wiring board F is thermocompression bonded by the pressure bonding head S3 and the fixed stage S2 heated to a predetermined temperature (main pressure bonding step). . By this thermocompression bonding, the semiconductor elements GD and SD and the flexible wiring board F are connected to the first anisotropic conductive film (ACF) 6A and the second anisotropic conductive film (ACF) 6A.
In order to be electrically connected through the anisotropic conductive film 6B, the conduction test is performed in this state. That is, the conventional energization inspection that has been performed after the semiconductor element is mounted is not performed. However, if the flexible wiring board F is mounted within 20 hours after the semiconductor elements GD and SD are mounted, the driving state inspection (energization inspection) of the semiconductor elements GD and SD is performed, and then the flexible wiring board F is mounted. The mounting process may be performed.

【0027】(第2の実施の形態)本実施の形態は、図
4に示すように、携帯電話や携帯情報端末(PDA)等
の小型の液晶表示パネルLに本発明を適用したもので、
液晶表示パネルLの一方の基板L1の一辺1a側に形成
される実装領域L6にゲートドライバGDとソースドラ
イバSDが一つずつ実装される。本実施の形態では、従
来例の第1の基板L1の一辺1aの実装領域L6にのみ
半導体素子とフレキシブル配線基板Fを実装する。その
実装方法は、第1の実施の形態と同様である。なお、図
5に示すように、一方の基板L1の一辺1a側の実装領
域L6にゲートドライバGDとソースドライバSDを兼
用する半導体素子ICが一個のみ実装されるものもあ
る。
(Second Embodiment) In the present embodiment, as shown in FIG. 4, the present invention is applied to a small liquid crystal display panel L such as a mobile phone or a personal digital assistant (PDA).
One gate driver GD and one source driver SD are mounted in a mounting region L6 formed on one side 1a of the substrate L1 of the liquid crystal display panel L. In the present embodiment, the semiconductor element and the flexible wiring board F are mounted only in the mounting area L6 on one side 1a of the first board L1 of the conventional example. The mounting method is similar to that of the first embodiment. Note that, as shown in FIG. 5, there is also one in which only one semiconductor element IC that also serves as the gate driver GD and the source driver SD is mounted in the mounting region L6 on one side 1a side of the one substrate L1.

【0028】ここで、上記第1と第2の実施の形態にお
いて、液晶表示パネルLの一方の基板L1の反り状態に
ついて説明すると、まず、半導体素子GD,SDの実装
の際、その熱硬化性接着剤6Aが硬化収縮して、半導体
素子GD,SDに収縮応力が加わり(図6(a)中の符
号f1)、液晶表示パネルLの一方の基板L1に反りが
生じる(図6(a))。次に、従来では、長時間経過後
にフレキシブル配線基板Fを実装すると、ACF6Aの
硬化状態が完全な安定状態に達してしまうことから、圧
着ヘッドS3による押圧力がフレキシブル配線基板Fに
対する無理な応力(上記反りを戻そうとする反力であ
り、この応力は一方の基板L1を平板状態にする力でも
ある。図6(b)中の符号f2)として働き、硬化した
第1のACF6Aが剥がれる事態が生じ(図7
(a))、これにより、半導体素子GD,SDのCOG
接続部(特に半導体素子GD,SDの両端部)の導通不
具合が生じる問題を有していた。しかし、本実施の形態
では、上記半導体素子GD,SDを実装した後20時間
以内にフレキシブル配線基板Fを実装すると、熱硬化性
接着剤6Aの硬化状態が完全な安定状態に達していない
ために、フレキシブル配線基板Fを熱圧着する際に既に
実装された半導体素子GD,SDの接着剤6Aが剥がれ
ることがなく、上記一方の基板L1の平板状態を維持し
つつ信頼性の高い接着効果が得られる(図7(b))。
また、上記各実施の形態によれば、フレキシブル配線基
板Fの熱圧着による実装も平板状態で実装されることと
なる。
The warped state of one substrate L1 of the liquid crystal display panel L in the first and second embodiments will now be described. First, when the semiconductor elements GD and SD are mounted, their thermosetting properties are set. The adhesive 6A cures and shrinks, and shrinkage stress is applied to the semiconductor elements GD and SD (reference numeral f1 in FIG. 6A), so that one substrate L1 of the liquid crystal display panel L is warped (FIG. 6A). ). Next, conventionally, when the flexible wiring board F is mounted after a long time elapses, the cured state of the ACF 6A reaches a completely stable state. Therefore, the pressing force of the pressure bonding head S3 imposes an excessive stress on the flexible wiring board F ( This is a reaction force to return the warp, and this stress is also a force to bring one substrate L1 into a flat plate state, which acts as a symbol f2) in Fig. 6 (b), and the cured first ACF 6A is peeled off. Occurs (Fig. 7
(A)), whereby the COG of the semiconductor devices GD and SD
There is a problem that a connection part (particularly both ends of the semiconductor elements GD and SD) has a conduction defect. However, in the present embodiment, when the flexible wiring board F is mounted within 20 hours after mounting the semiconductor elements GD and SD, the cured state of the thermosetting adhesive 6A has not reached a completely stable state. The adhesive 6A of the already mounted semiconductor elements GD and SD is not peeled off when the flexible wiring board F is thermocompression-bonded, and a highly reliable adhesive effect is obtained while maintaining the flat state of the one board L1. (FIG. 7B).
Further, according to each of the above-described embodiments, the mounting of the flexible wiring board F by thermocompression bonding is also mounted in a flat plate state.

【0029】[0029]

【実施例】(実施例1)次に、半導体素子GD,SDの
実装とフレキシブル配線基板Fの実装との間の待機時間
(hr)による半導体素子GD,SDの実装状態の不具
合の発生率を調べる実験を行った。この実験では、液晶
表示パネルLの一方の基板L1として、厚みtが0.5
mmのもの(図8中符号A1)と0.7mmのもの(図
8中符号B1)を使用し、待機時間(hr)を変えて実
装した。そして、以下の表1に示す条件で実際に半導体
素子GD,SDとフレキシブル配線基板Fとを実装し
た。実装例は、多数の半導体素子GD,SDを実装する
上記第1の本実施の形態によるが、第1の異方性導電膜
(ACF)6Aと第2の異方性導電膜6Bのガラス転移
温度Tgが同じもので行った。不具合の発生率とは、A
CF6Aが剥がれたり気泡が生じたりする等による導通
不具合を言う。
(Embodiment 1) Next, the occurrence rate of defects in the mounting state of the semiconductor elements GD, SD due to the waiting time (hr) between the mounting of the semiconductor elements GD, SD and the mounting of the flexible wiring board F will be described. An experiment was conducted to investigate. In this experiment, one substrate L1 of the liquid crystal display panel L has a thickness t of 0.5.
8 mm (reference numeral A1 in FIG. 8) and 0.7 mm (reference numeral B1 in FIG. 8) were used and mounted with different waiting times (hr). Then, the semiconductor elements GD and SD and the flexible wiring board F were actually mounted under the conditions shown in Table 1 below. The mounting example is based on the first embodiment in which a large number of semiconductor elements GD and SD are mounted, but the glass transition of the first anisotropic conductive film (ACF) 6A and the second anisotropic conductive film 6B. The same temperature Tg was used. What is the failure rate?
This is a conduction failure due to peeling of CF6A or generation of bubbles.

【0030】[0030]

【表1】 [Table 1]

【0031】表1において、「仮止め」とは、上述した
ように、第1と第2の異方性導電膜(ACF))6A,
6Bを貼着させる工程であり、「本圧着」とは、上述し
たように、所定の温度に加熱した圧着ヘッドS3と固定
ステージS2とにより熱圧着する工程である。なお、
「仮止め」工程の後には、半導体素子GD,SD等の位
置合わせ工程であるアライメント工程がある。液晶表示
パネルLの一方の基板L1の厚みtが0.5mmのもの
(図8中符号A1)と0.7mmのもの(図8中符号B
1)を使用して実装し、半導体素子GD,SDの実装状
態の不具合の発生率と比較したものが表2であり、これ
をグラフ化した図が図8である。半導体素子GD,SD
の側面からフレキシブル配線基板Fの位置までの距離H
は、0.8mmである。
In Table 1, "temporary fixing" means, as mentioned above, the first and second anisotropic conductive films (ACF) 6A,
6B is a step of adhering 6B, and "main pressure bonding" is a step of performing thermocompression bonding by the pressure bonding head S3 and the fixed stage S2 heated to a predetermined temperature as described above. In addition,
After the “temporary fixing” step, there is an alignment step which is a step of aligning the semiconductor elements GD, SD and the like. One of the substrates L1 of the liquid crystal display panel L has a thickness t of 0.5 mm (reference numeral A1 in FIG. 8) and 0.7 mm (reference numeral B in FIG. 8).
Table 2 shows a rate of occurrence of defects in the mounted state of the semiconductor elements GD and SD, which is mounted using the method 1), and FIG. 8 is a graph of this. Semiconductor device GD, SD
H from the side of the board to the position of the flexible wiring board F
Is 0.8 mm.

【0032】[0032]

【表2】 [Table 2]

【0033】表2と図8から明らかなように、液晶表示
パネルLの一方の基板L1の厚みtが0.5mmのもの
(表1中符号A1)と厚みtが0.7mmのもの(表1
中符号B2)のいずれの場合も、半導体素子GD,SD
の実装(COG接続部)からフレキシブル配線基板Fの
実装との間の待機時間(hr)が長くなればなるほど、
半導体素子GD,SDのCOG接続部のACF6Aが剥
がれて隙間が生じたり気泡が生じたりする等による導通
不具合が正比例的に生じることがわかる。すなわち、半
導体素子GD,SDを実装した後20時間以内であれ
ば、不具合の発生率は許容範囲であるので(0.2%以
下は許容範囲)、半導体素子GD,SDを実装した後2
0時間以内にフレキシブル配線基板Fを実装することが
望ましいが、半導体素子GD,SDを実装した後15時
間以内にフレキシブル配線基板を実装すると、不具合の
発生率は「0.1%」であるので、更に好ましい。
As is clear from Table 2 and FIG. 8, one of the substrates L1 of the liquid crystal display panel L has a thickness t of 0.5 mm (reference numeral A1 in Table 1) and a thickness t of 0.7 mm (see Table 1). 1
In either case of the medium code B2), the semiconductor elements GD, SD
The longer the waiting time (hr) from the mounting (COG connection part) to the mounting of the flexible wiring board F becomes,
It can be seen that the ACF 6A at the COG connection portion of the semiconductor elements GD and SD is peeled off to form a gap or a bubble, which causes a conduction defect in direct proportion. That is, since the occurrence rate of defects is within the allowable range within 20 hours after mounting the semiconductor elements GD and SD (0.2% or less is within the allowable range), 2 after mounting the semiconductor elements GD and SD.
It is desirable to mount the flexible wiring board F within 0 hours, but if the flexible wiring board is mounted within 15 hours after mounting the semiconductor elements GD and SD, the failure occurrence rate is "0.1%". , And more preferably.

【0034】(実施例2)次に、半導体素子GD,SD
を実装するときの熱硬化性接着剤6Aのガラス転移温度
Tgよりもフレキシブル配線基板Fを実装するときの熱
硬化性接着剤6Bのガラス転移温度Tgの方が低いもの
使用して実施した。表3は実装条件を示す図である。図
8中符号A2がt=0.5mmの場合であり、符号B2
がt=0.7mmの場合であり、半導体素子GD,SD
の実装状態の不具合の発生率と比較したものが表4であ
る。半導体素子GD,SDの側面からフレキシブル配線
基板Fの位置までの距離Hは、0.8mmである。
(Embodiment 2) Next, semiconductor elements GD and SD
The glass transition temperature Tg of the thermosetting adhesive 6B when mounting the flexible wiring board F is lower than the glass transition temperature Tg of the thermosetting adhesive 6A when mounting. Table 3 is a diagram showing the mounting conditions. In FIG. 8, the code A2 is when t = 0.5 mm, and the code B2
Is t = 0.7 mm, and the semiconductor elements GD, SD
Table 4 shows a comparison with the occurrence rate of defects in the mounting state. The distance H from the side surfaces of the semiconductor elements GD and SD to the position of the flexible wiring board F is 0.8 mm.

【0035】[0035]

【表3】 [Table 3]

【0036】[0036]

【表4】 [Table 4]

【0037】表4と図8から明らかなように、実施例2
でも、半導体素子GD,SDの実装からフレキシブル配
線基板Fの実装との間の待機時間(hr)が長くなれば
なるほど、半導体素子GD,SDのCOG接続部のAC
F6Aが剥がれて隙間が生じたりする等による導通不具
合が正比例的に生じることがわかる。そして、液晶表示
パネルLの一方の基板L1の厚みtが0.5mmのもの
(表1中符号A2)と厚みtが0.7mmのもの(表1
中符号B2)のいずれの場合も、半導体素子GD,SD
を実装した後20時間以内であれば、不具合の発生率は
許容範囲であるので(0.2%以下は許容範囲)、半導
体素子GD,SDを実装した後20時間以内にフレキシ
ブル配線基板Fを実装することが望ましいが、半導体素
子GD,SDを実装した後15時間以内にフレキシブル
配線基板Fを実装すると、不具合の発生率は「0」であ
るので、更に好ましい。なお、表2と表4との比較か
ら、半導体素子GD,SDを実装するときの第1の異方
性導電膜6Aのガラス転移温度よりもフレキシブル配線
基板Fを実装するときの第2の異方性導電膜6Bのガラ
ス転移温度の方を低くすると、不具合の発生率が低いこ
とが分かる。
As is clear from Table 4 and FIG.
However, as the waiting time (hr) between the mounting of the semiconductor elements GD and SD to the mounting of the flexible wiring board F becomes longer, the AC of the COG connection portion of the semiconductor elements GD and SD becomes longer.
It can be seen that the conduction failure occurs in direct proportion due to the peeling of F6A and the formation of a gap. Then, one of the substrates L1 of the liquid crystal display panel L having a thickness t of 0.5 mm (reference numeral A2 in Table 1) and one having a thickness t of 0.7 mm (Table 1
In either case of the medium code B2), the semiconductor elements GD, SD
Since the defect occurrence rate is within the allowable range within 20 hours after mounting the semiconductor device (0.2% or less is within the allowable range), the flexible wiring board F is mounted within 20 hours after mounting the semiconductor elements GD and SD. It is preferable to mount the flexible wiring board F within 15 hours after mounting the semiconductor elements GD and SD, and it is more preferable because the failure occurrence rate is “0”. From the comparison between Table 2 and Table 4, the second difference when mounting the flexible wiring board F is higher than the glass transition temperature of the first anisotropic conductive film 6A when mounting the semiconductor elements GD and SD. It can be seen that when the glass transition temperature of the anisotropic conductive film 6B is lowered, the incidence of defects is low.

【0038】また、液晶表示パネルLの一方の基板L1
の厚みtが厚い方(符号B1,B2のt=0.7mm)
が薄いもの(符号A1,A2のt=0.5mm)よりも
半導体素子GD,SDのACF6Aが剥がれたり気泡が
生じたりする等による導通不具合が少ないことことがわ
かる。これは、半導体素子GD,SDの実装に際して熱
硬化性接着剤6Aが硬化収縮して、半導体素子GD,S
Dに収縮応力が加わり、表示パネルLの一方の基板L1
に反りが生じるが、厚みtが厚いと、上記反りが生じ難
いことによるものと考えられる。
Further, one substrate L1 of the liquid crystal display panel L
Has a larger thickness t (reference numeral B1 and B2 t = 0.7 mm)
It can be seen that there is less conduction failure due to peeling or bubble formation of the ACF 6A of the semiconductor elements GD and SD, compared to the thin one (t = 0.5 mm of reference characters A1 and A2). This is because the thermosetting adhesive 6A cures and shrinks during mounting of the semiconductor elements GD, SD, and the semiconductor elements GD, S
The contraction stress is applied to D, and one substrate L1 of the display panel L
However, it is considered that when the thickness t is large, the above-mentioned warpage is difficult to occur.

【0039】以上、本発明は、前記各実施の形態に示す
ほか、種々の形態に構成することができる。例えば、表
示パネルLを液晶表示装置に用いた場合について説明し
たが、PDP(plasma display panel)用パネル等の他
の表示パネルでも、本発明を用いることで同様の効果が
得られる。
As described above, the present invention can be configured in various forms other than the above-mentioned embodiments. For example, although the case where the display panel L is used in a liquid crystal display device has been described, the same effect can be obtained by using the present invention in another display panel such as a PDP (plasma display panel) panel.

【0040】[0040]

【発明の効果】本発明の表示パネルの製造方法によれ
ば、半導体素子を実装した後20時間以内にフレキシブ
ル配線基板を実装すると、接着剤の硬化状態が完全な安
定状態に達していないために、フレキシブル配線基板を
熱圧着する際に既に実装された半導体素子の接着剤が剥
がれることがなく、表示パネルの一方の基板の平板状態
を維持しつつ信頼性の高い接着効果が得られ、その結
果、表示パネルの一方の基板に対する半導体素子のみな
らず、フレキシブル配線基板の実装精度の高い表示パネ
ルを製造することが可能になる。
According to the method of manufacturing a display panel of the present invention, when the flexible wiring board is mounted within 20 hours after mounting the semiconductor element, the cured state of the adhesive does not reach a completely stable state. , The adhesive of the semiconductor element already mounted is not peeled off when the flexible wiring board is thermocompression bonded, and the highly reliable adhesive effect is obtained while maintaining the flat state of one board of the display panel. Thus, it is possible to manufacture not only a semiconductor element for one substrate of the display panel but also a display panel having a high mounting accuracy of a flexible wiring substrate.

【0041】[0041]

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施の形態における表示パネル
における半導体素子とフレキシブル配線基板の実装状態
を示す断面図
FIG. 1 is a cross-sectional view showing a mounted state of a semiconductor element and a flexible wiring board in a display panel according to a first embodiment of the present invention.

【図2】上記第1の実施の形態における表示パネルにお
ける半導体素子とフレキシブル配線基板の実装状態を示
す斜視図
FIG. 2 is a perspective view showing a mounted state of a semiconductor element and a flexible wiring board in the display panel according to the first embodiment.

【図3】上記第1の実施の形態における半導体素子とフ
レキシブル配線基板の実装に使用する製造装置を示す断
面図
FIG. 3 is a sectional view showing a manufacturing apparatus used for mounting the semiconductor element and the flexible wiring board in the first embodiment.

【図4】本発明の第2の実施の形態における表示パネル
における半導体素子とフレキシブル配線基板の実装状態
を示す断面図
FIG. 4 is a sectional view showing a mounted state of a semiconductor element and a flexible wiring board in a display panel according to a second embodiment of the present invention.

【図5】上記第2の実施の形態における表示パネルにお
ける半導体素子とフレキシブル配線基板の実装状態を示
す斜視図
FIG. 5 is a perspective view showing a mounting state of a semiconductor element and a flexible wiring board in the display panel according to the second embodiment.

【図6】上記各実施の形態における液晶表示パネルの一
方の基板の反りの状態を説明する断面図
FIG. 6 is a cross-sectional view illustrating a warped state of one substrate of the liquid crystal display panel in each of the above embodiments.

【図7】上記各実施の形態における液晶表示パネルの一
方の基板のペースト状若しくはフィルム状の熱硬化性接
着剤の状態と従来の剥離状態を説明する断面図
FIG. 7 is a cross-sectional view for explaining a state of a paste or film thermosetting adhesive and a conventional peeled state of one substrate of the liquid crystal display panel in each of the above embodiments.

【図8】半導体素子の実装状態と不具合の発生率との関
係をグラフ化した図
FIG. 8 is a graph showing the relationship between the mounting state of semiconductor elements and the incidence of defects.

【図9】従来の液晶表示パネルにおける半導体素子とフ
レキシブル配線基板の実装状態を示す断面図
FIG. 9 is a cross-sectional view showing a mounted state of a semiconductor element and a flexible wiring board in a conventional liquid crystal display panel.

【図10】従来の液晶表示パネルにおける半導体素子と
フレキシブル配線基板の実装状態を示す平面図
FIG. 10 is a plan view showing a mounting state of a semiconductor element and a flexible wiring board in a conventional liquid crystal display panel.

【図11】表示パネルの製造方法を示す斜視図FIG. 11 is a perspective view showing a method of manufacturing a display panel.

【符号の説明】[Explanation of symbols]

4a,4b 突起電極(バンプ) 6 ペースト状若しくはフィルム状の熱硬化性接着
剤 6A ペースト状若しくはフィルム状の熱硬化性接着
剤(第1の異方性導電膜;ACF) 6B ペースト状若しくはフィルム状の熱硬化性接着
剤(第2の異方性導電膜;ACF) 6c 導電粒子 11,12 電極 F フレキシブル配線基板 GD,SD 半導体素子 L 液晶表示パネル L1 一方の基板(第1の基板,AM基
板) L2 他方の基板(第2の基板) P1,P2,P3 配線パターン S1 可動ステージ S2 固定ステージ S3 圧着ヘッド
4a, 4b Protruding electrodes (bumps) 6 Paste or film thermosetting adhesive 6A Paste or film thermosetting adhesive (first anisotropic conductive film; ACF) 6B Paste or film Thermosetting adhesive (second anisotropic conductive film; ACF) 6c conductive particles 11, 12 electrode F flexible wiring board GD, SD semiconductor element L liquid crystal display panel L1 one substrate (first substrate, AM substrate) ) L2 other substrate (second substrate) P1, P2, P3 wiring pattern S1 movable stage S2 fixed stage S3 pressure bonding head

───────────────────────────────────────────────────── フロントページの続き (72)発明者 石亀 剛 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 竹澤 浩義 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 福田 尚宏 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 会田 勉 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 高野 大樹郎 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 5F044 NN13 NN19 RR17 RR19    ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tsuyoshi Ishigame             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Hiroyoshi Takezawa             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Naohiro Fukuda             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Tsutomu Aida             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Daijuro Takano             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 5F044 NN13 NN19 RR17 RR19

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 一対の基板を有する表示パネルの一方の
基板にペースト状若しくはフィルム状の熱硬化性接着剤
を介して半導体素子を実装した後、表示パネルの一方の
基板の周辺部であって半導体素子が実装される近傍にペ
ースト状若しくはフィルム状の熱硬化性接着剤を介して
フレキシブル配線基板を実装する表示パネルの製造方法
において、 上記半導体素子を実装した後20時間以内にフレキシブ
ル配線基板を実装することを特徴とする表示パネルの製
造方法。
1. A semiconductor device is mounted on one substrate of a display panel having a pair of substrates via a paste-shaped or film-shaped thermosetting adhesive, and then a peripheral portion of the one substrate of the display panel. In a method for manufacturing a display panel, in which a flexible wiring board is mounted near a semiconductor element mounted via a paste-shaped or film-shaped thermosetting adhesive, a flexible wiring board is mounted within 20 hours after mounting the semiconductor element. A method for manufacturing a display panel, which is characterized by mounting.
【請求項2】 前記半導体素子を実装するときの熱硬化
性接着剤のガラス転移温度よりもフレキシブル配線基板
を実装するときの熱硬化性接着剤のガラス転移温度の方
が低いことを特徴とする請求項1記載の表示パネルの製
造方法。
2. The glass transition temperature of the thermosetting adhesive when mounting the flexible wiring board is lower than the glass transition temperature of the thermosetting adhesive when mounting the semiconductor element. The method for manufacturing a display panel according to claim 1.
【請求項3】 前記半導体素子を実装した後フレキシブ
ル配線基板を実装する間に、半導体素子の通電検査工程
を介在させないことを特徴とする請求項1又は請求項2
記載のいずれかに記載の表示パネルの製造方法。
3. The semiconductor element energization inspection step is not interposed during mounting of the flexible wiring board after mounting of the semiconductor element.
A method for manufacturing a display panel according to any one of the above.
JP2002049235A 2002-02-26 2002-02-26 Manufacturing method for display panel Pending JP2003249525A (en)

Priority Applications (1)

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JP2002049235A JP2003249525A (en) 2002-02-26 2002-02-26 Manufacturing method for display panel

Publications (1)

Publication Number Publication Date
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Application Number Title Priority Date Filing Date
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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278442A (en) * 2005-03-28 2006-10-12 Casio Comput Co Ltd Conductivity path establishment structure of electronic component and its manufacturing equipment
WO2016027762A1 (en) * 2014-08-22 2016-02-25 シャープ株式会社 Manufacturing device for mounting substrate and manufacturing method for mounting substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278442A (en) * 2005-03-28 2006-10-12 Casio Comput Co Ltd Conductivity path establishment structure of electronic component and its manufacturing equipment
JP4650050B2 (en) * 2005-03-28 2011-03-16 カシオ計算機株式会社 Method for electrically installing electronic parts and method for manufacturing liquid crystal display elements
WO2016027762A1 (en) * 2014-08-22 2016-02-25 シャープ株式会社 Manufacturing device for mounting substrate and manufacturing method for mounting substrate
CN106576432A (en) * 2014-08-22 2017-04-19 夏普株式会社 Manufacturing device for mounting substrate and manufacturing method for mounting substrate

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