JP2003209037A - アライメントマーク及び半導体装置の製造方法 - Google Patents

アライメントマーク及び半導体装置の製造方法

Info

Publication number
JP2003209037A
JP2003209037A JP2002004595A JP2002004595A JP2003209037A JP 2003209037 A JP2003209037 A JP 2003209037A JP 2002004595 A JP2002004595 A JP 2002004595A JP 2002004595 A JP2002004595 A JP 2002004595A JP 2003209037 A JP2003209037 A JP 2003209037A
Authority
JP
Japan
Prior art keywords
gas
film
alignment mark
via hole
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002004595A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003209037A5 (enExample
Inventor
Nobuhisa Yamagishi
信久 山岸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2002004595A priority Critical patent/JP2003209037A/ja
Publication of JP2003209037A publication Critical patent/JP2003209037A/ja
Publication of JP2003209037A5 publication Critical patent/JP2003209037A5/ja
Pending legal-status Critical Current

Links

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2002004595A 2002-01-11 2002-01-11 アライメントマーク及び半導体装置の製造方法 Pending JP2003209037A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002004595A JP2003209037A (ja) 2002-01-11 2002-01-11 アライメントマーク及び半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002004595A JP2003209037A (ja) 2002-01-11 2002-01-11 アライメントマーク及び半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2003209037A true JP2003209037A (ja) 2003-07-25
JP2003209037A5 JP2003209037A5 (enExample) 2005-07-21

Family

ID=27643891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002004595A Pending JP2003209037A (ja) 2002-01-11 2002-01-11 アライメントマーク及び半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP2003209037A (enExample)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3536104B2 (ja) 2002-04-26 2004-06-07 沖電気工業株式会社 半導体装置の製造方法
JP2007505492A (ja) * 2003-09-12 2007-03-08 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体デバイスにおける造形部分のパターン形成技術
JP2008004724A (ja) * 2006-06-22 2008-01-10 Fujitsu Ltd 半導体装置及びその製造方法
US7465670B2 (en) 2005-03-28 2008-12-16 Tokyo Electron Limited Plasma etching method, plasma etching apparatus, control program and computer storage medium with enhanced selectivity
JP2009124157A (ja) * 2008-12-19 2009-06-04 Renesas Technology Corp 配線構造の製造方法
JP2009182362A (ja) * 2009-05-21 2009-08-13 Casio Comput Co Ltd 半導体素子の半田層の製造方法、半導体素子のマークの製造方法及び半導体素子のダイシング方法
JP2009238801A (ja) * 2008-03-26 2009-10-15 Consortium For Advanced Semiconductor Materials & Related Technologies 半導体装置の製造方法、及び半導体装置の製造に際して用いられる位置整合用パターン構造
JP2009295920A (ja) * 2008-06-09 2009-12-17 Oki Semiconductor Co Ltd 半導体基板、及びその製造方法
US8497997B2 (en) 2009-06-23 2013-07-30 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
JP2013168472A (ja) * 2012-02-15 2013-08-29 River Eletec Kk アライメントマーク
JP2014033209A (ja) * 2013-09-05 2014-02-20 Lapis Semiconductor Co Ltd 半導体基板
JP2014228708A (ja) * 2013-05-22 2014-12-08 キヤノン株式会社 電子装置およびその製造方法ならびにカメラ
US10811360B2 (en) 2015-09-01 2020-10-20 Toshiba Memory Corporation Semiconductor device, method for manufacturing semiconductor device and alignment mark

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3536104B2 (ja) 2002-04-26 2004-06-07 沖電気工業株式会社 半導体装置の製造方法
JP2007505492A (ja) * 2003-09-12 2007-03-08 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体デバイスにおける造形部分のパターン形成技術
JP4755592B2 (ja) * 2003-09-12 2011-08-24 インターナショナル・ビジネス・マシーンズ・コーポレーション 造形部分をパターン形成する方法
US7465670B2 (en) 2005-03-28 2008-12-16 Tokyo Electron Limited Plasma etching method, plasma etching apparatus, control program and computer storage medium with enhanced selectivity
JP2008004724A (ja) * 2006-06-22 2008-01-10 Fujitsu Ltd 半導体装置及びその製造方法
JP2009238801A (ja) * 2008-03-26 2009-10-15 Consortium For Advanced Semiconductor Materials & Related Technologies 半導体装置の製造方法、及び半導体装置の製造に際して用いられる位置整合用パターン構造
JP2009295920A (ja) * 2008-06-09 2009-12-17 Oki Semiconductor Co Ltd 半導体基板、及びその製造方法
JP2009124157A (ja) * 2008-12-19 2009-06-04 Renesas Technology Corp 配線構造の製造方法
JP2009182362A (ja) * 2009-05-21 2009-08-13 Casio Comput Co Ltd 半導体素子の半田層の製造方法、半導体素子のマークの製造方法及び半導体素子のダイシング方法
US8497997B2 (en) 2009-06-23 2013-07-30 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
JP2013168472A (ja) * 2012-02-15 2013-08-29 River Eletec Kk アライメントマーク
JP2014228708A (ja) * 2013-05-22 2014-12-08 キヤノン株式会社 電子装置およびその製造方法ならびにカメラ
JP2014033209A (ja) * 2013-09-05 2014-02-20 Lapis Semiconductor Co Ltd 半導体基板
US10811360B2 (en) 2015-09-01 2020-10-20 Toshiba Memory Corporation Semiconductor device, method for manufacturing semiconductor device and alignment mark

Similar Documents

Publication Publication Date Title
US6225217B1 (en) Method of manufacturing semiconductor device having multilayer wiring
US6930036B2 (en) Semiconductor device and method of manufacturing the same
KR100563969B1 (ko) 선택적 플라즈마 식각방법
TW441015B (en) Dual-damascene interconnect structures and methods for fabricating same
CN101320706B (zh) 形成多层半导体结构与其双层镶嵌凹陷的方法
US6767826B2 (en) Method of manufacturing semiconductor device
US6696760B2 (en) Semiconductor structure
US6468898B1 (en) Method of manufacturing semiconductor device
KR100641502B1 (ko) 반도체 소자 제조시 듀얼 다마신 공정을 이용한 콘텍형성방법
JP2003209037A (ja) アライメントマーク及び半導体装置の製造方法
JP2002009150A (ja) 半導体装置、その製造方法及び製造装置
JP2002026122A (ja) 半導体装置の製造方法
JP3346475B2 (ja) 半導体集積回路の製造方法、半導体集積回路
JP2001308175A (ja) 半導体装置及びその製造方法
US5942801A (en) Borderless vias with HSQ gap filled metal patterns having high etching resistance
US6867139B2 (en) Method of manufacturing semiconductor device
US20250316496A1 (en) Film deposition for patterning process
US20230136674A1 (en) Self-aligned double patterning (sadp) integration with wide line spacing
US6780778B2 (en) Method for fabricating semiconductor device
JP2004260001A (ja) 半導体装置の製造方法
US6841467B2 (en) Method for producing semiconductor device
KR100602086B1 (ko) 반도체 소자의 배선 형성방법
US6133628A (en) Metal layer interconnects with improved performance characteristics
US11315872B1 (en) Self-aligned top via
JP2000003912A (ja) 半導体装置の製造方法および半導体装置

Legal Events

Date Code Title Description
RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20040319

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20040604

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041129

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20041129

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060616

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060620

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060808

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20061017