JP2003141897A - Memory test device and method, program storage medium, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory test device and method, program recording medium, and a program for shortening the time required for a test even for a memory to be tested of which data bus width is large. SOLUTION: This memory test device is provided with: a memory 3 for test program storing a program for testing a memory 2 to be tested; and a memory 4 for test data pattern group storing a test data pattern group used for a test. A bit column generated by repeating division into two parts of a binary number column consisting of the same bits as the data bus width of the memory 2 to be tested is used for the test data pattern group.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection apparatus for a memory mounted in a microcomputer system or a semiconductor integrated circuit incorporating the memory, an inspection method therefor, an inspection program recording medium and an inspection program.

[0002]

2. Description of the Related Art FIG. 12 shows an inspection data pattern group used in a conventional memory inspection device.

In the conventional inspection of a memory, when inspecting for a short circuit between all bits of a memory data bus, generally, a Walki as shown in FIG. 12 is used.
It has been performed that a simple inspection data pattern group called ng "0" and Walking "1" is written to the entire area of the memory one by one, and then read and collated with the written data pattern.

[0004]

However, in the test data pattern group used in the conventional memory test, the test data patterns of the same number as the number of bits of the data bus width of the memory under test are required. The larger the width of the memory, the larger the number of data patterns required for the inspection, and as a result, there is a drawback in that the inspection requires more time.

The present invention has been made in order to solve the above-mentioned conventional problems, and a memory inspection apparatus, method and program capable of shortening the time required for inspection even in a memory under inspection having a large data bus width. A recording medium and a program are provided.

[0006]

SUMMARY OF THE INVENTION A memory inspection device according to the present invention includes an inspection program memory for storing a program for inspecting a memory to be inspected and an inspection data pattern group for storing an inspection data pattern group used for the inspection. The test data pattern group includes a memory, and a bit string generated by repeatedly dividing a binary number string having the same number of bits as the data bus width of the memory under test into two.

With this configuration, it is possible to inspect the presence or absence of a short circuit that occurs between all bits of the memory data bus with a small number of inspection data patterns, and it is possible to shorten the inspection time.

A memory inspection apparatus of the present invention comprises an inspection program memory for storing a program for inspecting a memory to be inspected, and an inspection data pattern group memory for storing an inspection data pattern group used for the inspection. The test data pattern group includes all the bits of a bit string generated by repeatedly dividing a binary number string having the same number of bits as the data bus width of the memory under test into two, and one bit string arbitrarily selected from the generated bit string. It was decided to use the inverted bit string.

With this configuration, the presence or absence of a short circuit that occurs between all the bits of the memory data bus is checked, and the value of the bit is fixed to "0" or "1". , "1" fixing failure can be inspected with a smaller number of patterns than if inspection is performed separately, and the inspection time can be further shortened.

A memory inspection apparatus of the present invention comprises an inspection program memory for storing a program for inspecting a memory to be inspected, and an inspection data pattern group memory for storing an inspection data pattern group used for the inspection. The test data pattern group includes all the bits of a bit string generated by repeatedly dividing a binary number string having the same number of bits as the data bus width of the memory under test into two, and one bit string arbitrarily selected from the generated bit string. An inverted bit string is used, and one arbitrarily selected bit string is used again.

With this configuration, the presence / absence of a short circuit that occurs between all bits of the memory data bus is checked, the "0" fixing defect and the "1" fixing defect of the bit are detected, and once the power is turned on, "0" is set once. Separates the inspection of the fixed defect after writing "0" and the fixed defect after writing "1", which is a defect in which the bit is fixed at "0" or fixed at "1" when "or" is written to the bit. It is possible to inspect three persons with a smaller number of patterns than that performed in the above, and it is possible to further shorten the inspection time.

A memory inspection result display means for displaying an inspection result after the completion of the inspection is further provided.

With this configuration, the inspection result of the memory can be easily determined, and the inspection time can be shortened and erroneous determination can be prevented.

The data bus width, capacity of the memory under test,
The inspected memory information setting means for setting all or part of the address mapping information is further provided.

With this configuration, even if there are plural kinds of data bus widths, capacities, address mappings, etc. of the memory under test, it can be dealt with only by changing the setting of the memory information under test, and the inspection program need not be changed. be able to.

As the inspection data pattern group memory, an inspection data pattern group capable of inspecting a memory having a specific data bus width is stored in advance and used.

With this configuration, the test data pattern group stored in the test data pattern group memory need only be a pattern that can be tested by a memory having a specific bus width. Therefore, a circuit and a program for generating the test data pattern group can be used. Is unnecessary, and the capacity of the inspection data pattern group memory can be reduced.

The inspection data pattern group memory is adapted to generate and store the inspection data pattern group based on the information of the data bus width of the memory to be inspected set in the inspected memory information setting means.

With this configuration, even if there are a plurality of types of data bus width, capacity, address mapping, etc. of the memory under test, this can be dealt with by simply changing the setting of the memory data under test, and the memory contents for the group of test data patterns and It is possible to inspect a memory having various specifications without requiring a manual change of the inspection program.

In the test data pattern group, the number of bits of the data bus width of the memory under test is smaller than 2 to the n-th power (n is an integer of 2 or more) when the binary sequence is repeatedly divided into two. When it is larger than the (n-1) th power of, the binary number sequence of the original binary number sequence is supplemented with bits so that the number of bits becomes 2 to the nth power, and the last supplemented bit is deleted. It was decided to generate using the remaining bit string.

With this configuration, no matter how many bits the data bus width of the memory to be inspected is, the same method can be used for the inspection, and since the bit correction needs to be performed only once at the beginning, a simple and simple method is possible. Can be generated with.

The test data pattern group is formed by repeatedly dividing the binary number sequence into two, when the number of bits of the data bus width of the memory under test is an odd number, or when the number of bits of the number sequence divided in the process of dividing into two. When the number becomes an odd number, the binary number sequence is divided into two parts by supplementing the original binary number sequence so that the bit number becomes an even number, and the last supplemented bit is deleted and the remaining bit sequence is used. It was decided to be generated.

With this configuration, no matter how many bits the data bus width of the memory to be inspected is, the same method can be used for the inspection, and the number of bits to be additionally corrected can be minimized.

An inspection data pattern group generation means for realizing the generation of the inspection data pattern group by hardware such as an LSI is further provided.

With this configuration, it is possible to speed up the generation time of the inspection data pattern group.

The inspection data pattern group is generated by the program stored in the inspection program memory.

With this configuration, no special hardware is required for generation, and it is possible to easily change the pattern generation method and generation content.

The inspection data pattern group memory inspects a memory of a specific data bus width used when the number of bits of the data bus width of the inspected memory is 2n (n is an integer of 2 or more). A group of possible inspection data patterns is stored in advance, and based on the information on the data bus width of the memory to be inspected set in the inspected memory information setting means, it is selected from the group of inspection data patterns stored in advance. I decided to use it.

With this configuration, the inspection of the memory having the data bus width of 2 raised to the n-th power (n is an integer of 2 or more), which is often used, can be performed without generating the inspection data pattern group. And time can be unnecessary.

The test data pattern group memory can test a memory having a specific data bus width used when the number of bits of the data bus width of the memory under test is 2n (n is an integer of 2 or more). An inspection data pattern group is stored in advance, and is stored in advance when the number of bits of the data bus width of the inspected memory set in the inspected memory information setting means is 2n (n is an integer of 2 or more). N selected when the number of bits of the data bus width is 2 selected from the inspection data pattern group
In the cases other than the power (n is an integer of 2 or more), the inspection data pattern group is generated and used.

With this configuration, a memory having a data bus width of 2 (n is an integer of 2 or more), which is often used, can be inspected without generating an inspection data pattern group. Therefore, the inspection data pattern can be generated and inspected for the memories having other data bus widths, and the inspection can be performed regardless of the data bus width of the inspected memory.

The inspected memory information setting means sets information in each of the plurality of inspected memories.

With this configuration, a plurality of memories to be inspected can be individually or continuously inspected, and the efficiency of inspection can be improved.

A memory inspection method of the present invention stores a program for inspecting a memory to be inspected, stores a predetermined inspection data pattern group used for the inspection, and the inspection data pattern group is stored in the memory to be inspected. It is decided to use the bit string generated by repeatedly dividing the binary number string having the same number of bits as the data bus width into two.

With this method, it is possible to inspect the presence or absence of a short circuit that occurs between all the bits of the memory data bus with a small number of inspection data patterns, and the inspection time can be shortened.

An inspection program storage medium for a memory according to the present invention is an inspection program memory for storing a program for inspecting a memory to be inspected and an inspection data pattern group memory for storing a predetermined inspection data pattern group used for the inspection. The test data pattern group includes a bit string generated by repeatedly dividing a binary number string having the same number of bits as the data bus width of the memory under test into two.

With this configuration, it is possible to inspect the presence or absence of a short circuit that occurs between all the bits of the memory data bus with a small number of inspection data patterns, and it is possible to shorten the inspection time.

The memory inspection program of the present invention has an inspection data pattern group used for inspection of the inspected memory, and the inspection data pattern group is a binary number having the same number of bits as the data bus width of the inspected memory. It is decided to use a bit string generated by repeatedly dividing the string into two parts.

With this inspection program, it is possible to inspect with a small number of inspection data patterns whether or not a short circuit occurs between all bits of the memory data bus, and the inspection time can be shortened.

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a memory inspection device according to the first embodiment of the present invention.

The memory inspection device according to the first embodiment shown in FIG. 1 includes a microprocessor 1, an inspected memory 2, and an inspection program memory 3 for storing a program for the microprocessor 1 to inspect the inspected memory 2. An inspection data pattern group memory 4 for storing an inspection data pattern group used for inspection.

The microprocessor 1 operates according to the inspection program stored in the inspection program memory 3, and the first inspection data pattern is selected from the inspection data pattern group stored in the inspection data pattern memory 4. Is read and written in the area under test of the memory under test 2. Next, the microprocessor 1
The value is read from the area to be inspected, and whether or not it matches the written data pattern is verified. After that, all data patterns are collated by the same operation. In this way, the inspection of the memory is realized.

FIG. 2 shows a flow chart of a method of generating an inspection data pattern group used for inspection of the memory under inspection 2 in the first embodiment. Further, FIG. 3 shows the memory under test 2 used in the memory inspection apparatus according to the first embodiment.
3 shows a group of inspection data patterns when the data bus width of is 16 bits.

Regarding the method of generating the inspection data pattern group to be stored in the inspection data pattern group memory 4, the flow chart shown in FIG. 3 with reference to FIG. 3 will be described taking the case where the data bus width of the memory under inspection 2 is 16 bits as an example. Follow the instructions below.

First, in step S1, a sequence (xxx) consisting of 16 bits, which is the same number as the data bus width of the memory under test 2, is formed.
xxxxxxxxxxxxxx) is generated. Next, in step S2, the sequence is divided into two at the center (xxxxxxxxxx / xx).
xxxxxxx). In step S3, all the bits in the left half are "0" in sequence, and all the bits in the right half are "1".
Of the number (00000000/11111111). In step S4, an array of all sequences (00000
00011111111) as one of the inspection data patterns. Here, this is the pattern No. 1 shown in FIG.
Sequences created by division (00000000 and 1111)
1111) is not 1 bit (here, 8 bits), the result of step S5 is No, and the process proceeds to step S2.

In step S2, the number sequence is divided into two at the center (00
00/0000 and 1111/1111). In step S3, all bits in the left half are set to "0", and all bits in the right half are set to "1" (0000/1111 and 0000/1111). In step S4, an array of all sequences (0000111100001111)
Is one of the inspection data patterns. Here is this
It becomes the pattern No. 2 shown in. The sequence of numbers (00
00, 1111, 0000, and 1111) are not 1 bit, so step S5 is No, and step S2
Transition to.

In step S2, the number sequence is divided into two at the center (00
/ 00, 00/00, 11/11 and 11/11). In step S3, all bits in the left half are
0 ", all bits in the right half are a sequence of" 1 "(00/11,
00/11, 00/11 and 00/11). In step S4, an array of all sequences (00110011
00110011) is one of the inspection data patterns.
Here, this is pattern No. 3 shown in FIG. Sequences created by division (00, 11, 00, 11, 00, 11,
00 and 11) are not 1 bit, so step S5
Is No, and the process proceeds to step S2.

In step S2, the number sequence is divided into two at the center (0 /
0, 0/0, 0/0, 0/0, 1/1, 1/1, 1/1
And 1/1). In step S3, here, all the bits in the left half are "0", and all the bits in the right half are "1" (0/1, 0/1, 0/1, 0/1, 0/1, 0 / 1,
0/1 and 0/1). In step S4, an array of all sequences (0101010101010101) is set as one of the inspection data patterns. Here, this is pattern No. 4 shown in FIG. Sequences (0,
1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
Since 1, 0 and 1) are 1 bit, step S5 becomes Yes and is ended. As described above, the inspection data pattern group can be generated.

With this configuration, all the bits of the memory data bus can be compared with each other with a smaller number of data patterns than the method using the check data pattern groups generally called Walking "0" and Walking "1". Can be inspected for short circuit.

The microprocessor may be an integrated circuit such as DSP. Further, in the above embodiment,
Although the inspection program memory, the inspection data pattern group memory, and the inspected memory are described as different memories, they may be different areas of the same memory. Further, these memories and buses may exist inside the microprocessor or DSP.

FIG. 4 shows a test data pattern group when the data bus width of the memory under test 2 used in the memory testing device according to the second embodiment of the present invention is 16 bits.

The configuration of the memory inspection device according to the second embodiment is the same as that of the first embodiment, and the operation is also the same as that of the first embodiment.

In FIG. 4, the data bus width of the memory under test 2 is 1
9 shows a group of inspection data patterns in the case of 6 bits. In the method of generating the inspection data pattern group shown in FIG. 4, the data bus width of the memory under inspection 2 is 16
The case of a bit will be described as an example. Pattern No.4
The procedure is the same as that of the first embodiment up to the generation of. In the second embodiment, another pattern is continuously generated.

The generation method is as follows. Of the inspection data patterns of pattern No. 1 to pattern No. 4 generated up to this point, a sequence in which any bit is logically inverted in all bits is defined as pattern No. 5. Here, pattern No. 4 (0101
A sequence (1010101010101010) obtained by logically inverting all bits of (0101010101101) becomes pattern No. 5 in FIG.

With this configuration, it is possible to check whether or not there is a short circuit between all bits of the memory data bus.
Both of the inspections can be performed with a smaller number of patterns than the inspections of the defect in which the bit value is fixed to "0" or "1", the "0" fixed defect, and the "1" fixed defect are separately performed.

The configuration of the memory inspection device according to the third embodiment of the present invention is the same as that of the second embodiment, and the operation is also the same as that of the second embodiment.

FIG. 5 shows a test data pattern group in the case where the data bus width of the memory under test 2 used in the memory testing device according to the third embodiment is 16 bits.

The method of generating the inspection data pattern group shown in FIG. 5 will be described by taking the case where the data bus width of the memory under inspection 2 is 16 bits as an example. The procedure up to the generation of pattern No. 5 is the same as that of the second embodiment. In the third embodiment, another pattern is continuously generated.

The generation method is as follows. Pattern No.5
The pattern in which all the bits are logically inverted to generate is used again as pattern No. 6. Here, pattern No. 4
Since the number sequence (1010101010101010) obtained by logically inverting all bits of (0101010101010101) is set as pattern No. 5, pattern No. 4 (0101010).
10101010) is used again as pattern No. 6.

With this structure, it is possible to check whether or not there is a short circuit between all bits of the memory data bus.
Detecting "0" fixing failure or "1" fixing failure of the bit, and after writing "0" or "1" to the bit after turning on the power, the bit becomes "0" fixing or "1" fixing. It is possible to carry out the inspection of three persons with a smaller number of patterns than the case where the inspection of the fixed defect after writing "0" and the fixed defect after writing "1" is separately performed.

FIG. 6 is a block diagram of a memory inspection device according to the fourth embodiment of the present invention.

The memory inspection device according to the fourth embodiment has a configuration in which an inspection result display means 5 is added to the memory inspection device according to the first embodiment shown in FIG.

Next, the operation of the memory inspection device according to the fourth embodiment will be described with reference to FIG.

First, the microprocessor 1 operates according to the inspection program stored in the inspection program memory 3. The microprocessor 1 reads the first test data pattern from the test data pattern group stored in the test data pattern group memory 4 and writes it into the test area of the test memory 2. Next, the microprocessor 1 reads a value from the inspected area of the inspected memory 2 and verifies whether the value matches the written data pattern. After that, all data patterns are collated by the same operation. The microprocessor 1 displays the collation result on the inspection result display means 5.

With such a structure, the inspection result of the memory can be easily determined, so that the inspection time can be shortened.

The inspection result display means may display the result on the monitor screen, or may show the result by sound or voice. Also, an optical display element such as an LED may be used.

FIG. 7 is a block diagram of a memory inspection device according to the fifth embodiment of the present invention.

The memory inspection device according to the fifth embodiment has a configuration in which the inspected memory information setting means 6 is added to the memory inspection device shown in FIG.

Next, the operation of the memory inspection device according to the fifth embodiment will be described with reference to FIG.

First, the microprocessor 1 operates according to the inspection program stored in the inspection program memory 3. The microprocessor 1 sets the inspected memory information setting means 6. For example, data bus width, capacity,
Based on the information of the memory under test such as address mapping,
The first inspection data pattern is read from the inspection data pattern group stored in the inspection data pattern group memory 4. Further, the data is written in the inspected area of the inspected memory 2. Next, the microprocessor 1 reads a value from the inspected area of the inspected memory 2 and verifies whether the value matches the written data pattern. After that, all the used data patterns are collated by the same operation. The microprocessor 1 displays the collation result on the inspection result display means 5.

With this configuration, even if there are a plurality of types of data bus width, capacity, address mapping, etc. of the memory under test, it can be dealt with by simply changing the setting of the memory under test information. No change is required.

The configuration of the memory inspection apparatus according to the sixth embodiment of the present invention is the same as that of the first embodiment, the second embodiment,
This is the same as the third, fourth and fifth embodiments. The operation of the sixth embodiment is similar to that of the first embodiment, the second embodiment, the third embodiment, the fourth embodiment and the fifth embodiment, but the inspection data pattern group memory is used. Only the test data pattern group capable of inspecting the memory having the specific data bus width is stored in advance in the memory 4 before the test is started.

With such a configuration, the inspection data pattern group stored in the inspection data pattern group memory need only be the patterns that can be inspected by the memory having the specific bus width. Therefore, a circuit and a program therefor are unnecessary, and the capacity of the inspection data pattern group memory is small.

The structure of the memory inspection device according to the seventh embodiment of the present invention is the same as that of the fifth embodiment. 7th
The operation of this embodiment is the same as that of the fifth embodiment, but the inspection data pattern group memory 4 is stored in the inspection data pattern group memory 4 based on the information previously set in the inspected memory information setting means 6 before the inspection is started. Create and remember groups.

With this configuration, even if there are a plurality of types of data bus width, capacity, address mapping, etc. of the memory under test, it can be dealt with by simply changing the setting of the memory data under test, and the test data pattern can be obtained. Memory of various specifications can be inspected without the need to manually change the group memory contents or inspection program.

The structure of the memory inspection device according to the eighth embodiment of the present invention is the same as that of the seventh embodiment. 8th
The operation of this embodiment is similar to that of the seventh embodiment, but is stored in the inspection data pattern group memory 4,
The generation of the inspection data pattern group that is performed before the inspection is started will be described here by taking as an example the case where the data bus width of the memory under inspection 2 is 9 bits.

FIG. 8 is a flow chart of a method of generating a test data pattern group when the data bus width of the memory under test is 9 bits in the eighth embodiment.

First, in step S11, the memory under test 2
Sequence consisting of the same number of bits as the data bus width of (xxxx
xxxxxx) is generated. Next, in step S12, it is determined whether the number of bits of the generated sequence is 2 to the n-th power (n is an integer of 2 or more). Here, the number of bits of the generated sequence is 9, which is not the n-th power of 2 (n is an integer of 2 or more). Therefore, step S12 is No, and the process proceeds to step S13.

In step S13, the number of bits is additionally corrected so that the number of bits of the generated sequence becomes 2 to the n-th power (n is an integer of 2 or more). Here, the sequence (xxxxxxxxx
7 bit (zzzzzzz) is additionally corrected to (x), and (xx
xxxxxxxxxxzzzz) and a 16-bit sequence.

Next, in step S14, the number sequence is divided into two at the center (xxxxxxxxx / xzzzzzzzz). In step S15, all the bits in the left half are "0", and all the bits in the right half are "1" (00000000/11).
111111). In step S16, from the array of all sequences (0000000011111111),
Deleted corrected bits (00000001)
Is the first inspection data pattern. Since the sequence of numbers (00000000 and 11111111) formed by division is not 1 bit, step S17 becomes No and the process proceeds to step S14.

In step S14, the number sequence is divided into two at the center (0
000/0000 and 1111/1111). In step S15, all bits in the left half are "0",
All bits in the right half are a sequence of "1" (0000/1111
And 0000/1111). Step S16
Then, an array of all sequences (0000111100001
111) with the corrected bits deleted (000
011110) is the second inspection data pattern. Since the sequence of numbers (0000, 1111, 0000, and 1111) formed by division is not 1 bit, step S17 becomes No and the process proceeds to step S14.

In step S14, the number sequence is divided into two at the center (0
0/00, 00/00, 11/11 and 11/11)
To do. In step S15, all the bits in the left half are "0", and all the bits in the right half are "1" (00/1).
1, 00/11, 00/11 and 00/11). In step S16, a series of all numerical sequences (0011
001100110011) from which the corrected bit is deleted (001100110) is the third inspection data pattern. Sequences created by division (00, 11, 0
0, 11, 00, 11, 00 and 11) are not 1 bit, the step S17 is No and the step S1
Transition to 4.

In step S14, the number sequence is divided into two at the center (0
/ 0, 0/0, 0/0, 0/0, 1/1, 1/1, 1 /
1 and 1/1). In step S15, here, all the bits in the left half are "0", and all the bits in the right half are "1" (0/1, 0/1, 0/1, 0/1, 0/1, 0 /
1, 0/1 and 0/1). In step S16,
An array of all number sequences (01010101010101010)
The corrected bit is deleted from (1) (01010
1010) is the fourth inspection data pattern. The sequence of numbers (0, 1, 0, 1, 0, 1, 0, 1, 0,
Since 1, 0, 1, 0, 1, 0 and 1) are 1 bit, step S17 is Yes, and the process ends.

As described above, the inspection data pattern group here only needs to be corrected once by 7 bits to obtain (00000
0001), (000011110), (001100)
110) and four patterns of (010101010) can be generated.

Further, bit "0" fixation failure, "1"
Detecting improper fixing and once turning on the power, "0" or "
When testing "1" is a defect in which the bit is fixed to "0" or "1" after that, "0" is fixed after writing, and "1" is fixed after fixing,
The fifth and sixth patterns may be generated by the methods described in the second and third embodiments.

With such a configuration, the same method can be used for testing regardless of the number of bits of the data bus of the memory under test, and the bit correction to the number sequence can be performed only once at the beginning. Good, easy, simple.

The structure of the memory inspection device according to the ninth embodiment of the present invention is the same as that of the seventh embodiment. 9th
The operation of this embodiment is similar to that of the seventh embodiment, but is stored in the inspection data pattern group memory 4,
The generation of the inspection data pattern group that is performed before the inspection is started will be described here by taking as an example the case where the data bus width of the memory under inspection 2 is 9 bits.

FIG. 9 shows a flow chart of a method of generating a test data pattern group when the data bus width of the memory under test is 9 bits in the ninth embodiment.

First, in step S21, the memory under test 2
Sequence consisting of the same number of bits as the data bus width of (xxxx
xxxxxx) is generated. Next, in step S22, it is determined whether or not the number of bits in the sequence of two or more bits with the corrected bits deleted is even. Since the bits are not yet corrected in the generated sequence, the number of bits in the generated sequence is counted as it is. Since the number of bits of the generated sequence is 9 and is not an even number, step S22
Is No, and the process proceeds to step S23. Step S
In 23, set 1 so that the number of bits in the generated sequence is even.
Add a bit and correct. Here, the sequence (xxxxxxxxx
1 bit (z) is additionally corrected to (xxxx), and (xxxxxxxxx
xxxz) and a 10-bit sequence.

In step S24, the number sequence is divided into two at the center (x
xxxx / xxxxxx). In step S25, here all bits in the left half are "0" and all bits in the right half are "."
1 ”number sequence (00000/11111). In step S26, all number sequences are arranged (0000001111).
The corrected bit is deleted from (1) (00000
1111) is the first inspection data pattern. Since the sequence of numbers (00000 and 11111) formed by division is not 1 bit, step S27 becomes No and the process proceeds to step S22.

In step S22, it is determined whether or not the number of bits in the sequence of two or more bits with the corrected bits deleted is even. Here, the sequence obtained by deleting the corrected bits from the sequence (00000 and 11111) formed by division becomes (00000 and 1111), and the sequence (0000
0) is 5 bits, which is not an even number, so step S22
Is No, and the process proceeds to step S23. Step S
In 23, one bit is added and corrected so that the number of bits in the sequence is even. Here, 1 bit (z) is additionally corrected to the number sequence (00000) to obtain a number sequence of (00000z) and 6 bits.

In step S24, each number sequence is divided into two at the center (000 / 00z and 11/11). Step S
25, where all bits in the left half are "0" and all bits in the right half are "1" (000/111 and 00 /
11). In step S26, the second inspection data pattern is the one in which the corrected bits are deleted (000110011) from the one in which all sequences are arranged (0001110011). The sequence of numbers (000, 111,
00 and 11) are not 1 bit, so step S
27 is No, and the process proceeds to step S22.

In step S22, it is determined whether or not the number of bits in the sequence of two or more bits from which the corrected bits have been deleted is even. Here, the sequence of numbers (000, 11
The sequence obtained by deleting the corrected bits from (1, 00 and 11) becomes (000, 11, 00 and 11). Since the sequence (000) is 3 bits and is not an even number, step S22 becomes No and the process proceeds to step S23. To do. In step S23, 1 bit is added and corrected so that the number of bits in the sequence is even. Here, 1 bit (z) is additionally corrected to the number sequence (000) to obtain a number sequence of (000z) and 4 bits.

In step S24, each number sequence is divided into two at the center (00 / 0z, 1/1, 0/0 and 1/1). In step S25, all bits in the left half are set to "0",
Set all bits in the right half to a sequence of "1" (00/11, 0 /
1, 0/1 and 0/1). In step S26,
A third inspection data pattern is obtained by arranging all the numerical sequences (0011010101) and deleting the corrected bits (001010101). The sequence of numbers (00, 11, 0, 1, 0, 1, 0, and 1) created by division is not all 1-bit, so step S27 is No,
The process proceeds to step S22.

In step S22, it is determined whether or not the number of bits in the sequence of two or more bits from which the corrected bits have been deleted is even. Here, the sequence of numbers (00, 11,
The sequence obtained by deleting the corrected bits from (0, 1, 0, 1, 0 and 1) becomes (00, 1, 0, 1, 0, 1, 0 and 1), and the sequence (00) of 2 bits or more becomes 2 Since it is an even number of bits, step S22 is Yes and the process proceeds to step S24.

In step S24, a sequence of two or more bits is divided into two at the center (0/0, 1, 0, 1, 0, 1, 0 and 1). In step S25, all the bits in the left half are "0" and all the bits in the right half are "1" (0 /
1, 1, 0, 1, 0, 1, 0 and 1). Since no bit correction has been performed, in step S26, a line in which all sequences are arranged (011010101) is set as the fourth inspection data pattern. A sequence of numbers (0, 1, 1,
Since 0, 1, 0, 1, 0, and 1) are all 1 bit, step S27 is Yes, and the process ends. From the above, the inspection data pattern group here is corrected by a total of 4 bits, and (000011111), (0001
10011), (001010101), (01101)
4 patterns of 0101) can be generated. A bit more
After detecting the 0 "fixing defect and the" 1 "fixing defect and turning on the power,
Once "0" or "1" is written to the bit, the bit is fixed to "0" or "1" after that.
In the case of inspecting the fixed defect after writing 0 "and the fixed defect after writing" 1 ", the fifth and sixth patterns are generated by the method described in the second and third embodiments. Good.

With such a configuration, the same method can be used for testing regardless of the number of bits of the data bus of the memory under test, and the bit correction to the sequence in the generation process can be minimized. I'm done.

FIG. 10 is a block diagram of a memory inspection device according to the tenth embodiment of the present invention.

The memory inspection device according to the tenth embodiment has a configuration in which the inspection data pattern group generation means 7 realized by hardware such as an LSI is added to the memory inspection device shown in FIG.

Next, the operation of the memory inspection device according to the tenth embodiment will be described with reference to FIG.

First, the inspection data pattern group generation means 7 generates an inspection data pattern based on the information of the inspection memory such as the data bus width, capacity and address mapping set in the inspection memory information setting means 6. , In the inspection data pattern group memory 4. Microprocessor 1
Operates according to the inspection program stored in the inspection program memory 3. The microprocessor 1 reads the first inspection data pattern from the inspection data pattern group stored in the inspection data pattern group memory 4.

Further, the data is written in the inspected area of the inspected memory 2. Next, the microprocessor 1 reads a value from the inspected area of the inspected memory 2 and verifies whether the value matches the written data pattern. After that, all the used data patterns are collated by the same operation. The microprocessor 1 displays the collation result on the inspection result display means 5.

With such a configuration, the inspection data pattern group can be generated by hardware such as an LSI, and the generation time can be shortened.

The structure of the memory inspection device according to the eleventh embodiment of the present invention is the same as that of the seventh embodiment. The operation of the eleventh embodiment is similar to that of the seventh embodiment, but the inspection data pattern group to be stored in the inspection data pattern group memory 4 is generated by the inspection program memory 3
It is realized by the program stored in.

With this configuration, the generation of the inspection data pattern group is realized by software,
No special hardware is required for generation. Moreover, it is easy to change the pattern generation method and the generation contents.

The structure of the memory inspection apparatus according to the twelfth embodiment of the present invention is the same as that of the fifth embodiment. The operation of the twelfth embodiment is similar to that of the fifth embodiment, but the inspection data pattern group stored in advance in the inspection data pattern group memory 4 has a data bus width of 2 to the n-th power (n
1 or several types of pattern groups capable of inspecting memories of 2 or more) are selected and used based on the data bus width information of the memory 2 to be inspected set in the memory information setting means 6 to be inspected.

With such a configuration, n of 2
The inspection of a memory having a data bus width, which is a commonly used power (n is an integer of 2 or more), can be inspected without generating an inspection data pattern group, so that means and time for generating inspection data patterns are unnecessary.

The structure of the memory inspection apparatus according to the thirteenth embodiment of the present invention is the same as that of the seventh embodiment. The operation of the thirteenth embodiment is the same as that of the seventh embodiment, but a memory having a data bus width of 2 to the n-th power (n is an integer of 2 or more) can be inspected in advance in the inspection data pattern group memory 4. One or several kinds of inspection data pattern groups are stored, and when the data bus width information of the inspection memory 2 set in the inspection memory information setting means 6 is 2 to the n-th power (n is an integer of 2 or more), this is set. Is selected and used, and for other data bus widths, a pattern is generated and used for inspection.

With such a configuration, n of 2
The inspection of a memory having a data bus width, which is a commonly used power (n is an integer of 2 or more), can be inspected without generating an inspection data pattern group, so that means and time for generating inspection data patterns are unnecessary. In addition, since inspection data patterns can be generated and inspected for memories with other data bus widths,
Inspection is possible regardless of the data bus width of the memory under test.

The structure of the memory inspection device according to the fourteenth embodiment of the present invention is as follows: the fifth embodiment, the sixth embodiment, the seventh embodiment, the eighth embodiment, the ninth embodiment, This is a configuration in which a plurality of memories under test exist in the configurations of the tenth embodiment, the eleventh embodiment, the twelfth embodiment, and the thirteenth embodiment.

FIG. 11 is a block diagram showing the structure of the memory inspection device according to the tenth embodiment, in which the second memory 8 to be inspected is added.

Next, the operation of the memory inspection device according to the fourteenth embodiment will be described with reference to FIG.

Regarding the operation of the fourteenth embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, the eighth embodiment, the ninth embodiment, the tenth embodiment and the eleventh embodiment. The second embodiment, the twelfth embodiment, and the thirteenth embodiment are the same, but the inspected memory information setting means 6 has here two inspected memory information of the inspected memory 2 and the second inspected memory 8. To set. The microprocessor 1 uses this information to inspect the memory 2 and the second memory 8 to be inspected.
Are tested individually or consecutively.

With such a structure, a plurality of memories under inspection can be continuously inspected, and the efficiency of inspection can be improved.

Even if there are not a plurality of inspectable memories, the inspected memory information setting means may be capable of setting information of a plurality of inspected memories. In this case, if the already-set memory information to be inspected can be used as it is, the inspection can be performed without re-registering.

Although the memory inspection device of the present invention has been described in the first to fourteenth embodiments, the invention can also be an invention of a memory inspection method, a memory inspection program storage medium, and a memory inspection program. .

[0118]

According to the present invention, the presence or absence of a short circuit that occurs between all the bits of the memory data bus is checked, and the value of the bit is fixed at "0" or "1". Both the fixed defect and the "1" fixed defect can be inspected with a smaller number of patterns than when the inspection is performed separately, and the inspection time can be further shortened.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory inspection device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a flowchart of a method of generating an inspection data pattern group used for inspection of a memory under inspection in the first embodiment.

FIG. 3 is a diagram showing a test data pattern group when the data bus width of the memory under test used in the memory test device according to the first embodiment is 16 bits.

FIG. 4 is a diagram showing a test data pattern group when the data bus width of the memory under test used in the memory test device according to the second embodiment is 16 bits;

FIG. 5 is a diagram showing a test data pattern group when the data bus width of the memory under test used in the memory test device according to the third embodiment is 16 bits;

FIG. 6 is a configuration diagram of a memory inspection device according to a fourth embodiment of the present invention.

FIG. 7 is a configuration diagram of a memory inspection device according to a fifth embodiment of the present invention.

FIG. 8 is a diagram showing a flowchart of a method of generating a test data pattern group when the data bus width of the memory under test is 9 bits in the eighth embodiment.

FIG. 9 is a diagram showing a flowchart of a method of generating a test data pattern group when the data bus width of the memory under test is 9 bits in the ninth embodiment.

FIG. 10 is a configuration diagram of a memory inspection device according to a tenth embodiment of the present invention.

FIG. 11 is a configuration diagram in which a second inspected memory is added to the configuration of the memory inspection device according to the tenth embodiment.

FIG. 12 is a diagram showing an inspection data pattern group used in a conventional memory inspection device.

[Explanation of symbols]

1 microprocessor 2 Inspected memory 3 Inspection program memory 4 Memory for inspection data pattern group 5 Inspection result display means 6 Inspected memory information setting means 7 Inspection data pattern group generation means 8 Second inspected memory

Continued front page    F term (reference) 2G132 AA08 AC03 AD06 AD15 AE14                       AE18 AE23 AG02 AG03 AL00                       AL09                 5L106 AA15 AA16 DD22 EE03

Claims (17)

[Claims] 1. An inspection program memory for storing a program for inspecting a memory to be inspected, and an inspection data pattern group memory for storing an inspection data pattern group used for the inspection, wherein the inspection data pattern group comprises: An inspection device for a memory, which uses a bit string generated by repeatedly dividing a binary sequence consisting of the same number of bits as the data bus width of the memory under test into two. 2. An inspection program memory for storing a program for inspecting a memory to be inspected, and an inspection data pattern group memory for storing an inspection data pattern group used for the inspection, wherein the inspection data pattern group comprises: It is possible to use a bit string that is generated by repeatedly dividing a binary number string consisting of the same number of bits as the data bus width of the memory under test into two, and a bit string that has all bits inverted for one bit string arbitrarily selected from the generated bit string. Characteristic memory inspection device. 3. An inspection program memory for storing a program for inspecting a memory to be inspected, and an inspection data pattern group memory for storing an inspection data pattern group used for the inspection, wherein the inspection data pattern group comprises: Using a bit string generated by repeatedly dividing a binary number string having the same number of bits as the data bus width of the memory under test into two and a bit string in which all bits are inverted for one bit string arbitrarily selected from the generated bit string, An inspection device for a memory, wherein one arbitrarily selected bit string is used again. 4. The memory inspection apparatus according to claim 1, further comprising a memory inspection result display unit that displays an inspection result after the inspection is completed. 5. The inspected memory information setting means for setting information of all or part of a data bus width, capacity, and address mapping of the inspected memory, further comprising: The memory inspection device according to item 1. 6. The test data pattern group memory stores a test data pattern group capable of testing a memory having a specific data bus width in advance and uses the test data pattern group. The inspection device for the described memory. 7. The inspection data pattern group memory generates and stores the inspection data pattern group based on the information of the data bus width of the inspected memory set in the inspected memory information setting means. The memory inspection device according to claim 5, wherein the inspection device is a memory. 8. The test data pattern group has a number of bits of a data bus width of a memory under test less than 2 to the n-th power (n is an integer of 2 or more) when the binary sequence is repeatedly divided into two. 2 is larger than the (n-1) th power, the binary number sequence in which the original binary number sequence is supplemented with bits is repeated so that the number of bits becomes 2 to the nth power. The memory inspection device according to claim 7, wherein the inspection device is generated by using a bit string that has been deleted and remains. 9. The test data pattern group is configured by repeatedly dividing the binary number sequence into two, when the number of bits of the data bus width of the memory under test is an odd number, or a number sequence divided in the process of dividing into two. When the number of bits of is an odd number, the binary number sequence is divided into two so that the original binary number sequence is supplemented with bits so that the number of bits becomes an even number. The memory inspection device according to claim 7, wherein the inspection device is generated by using the memory inspection device. 10. The generation of the inspection data pattern group is performed by LS.
The memory inspection device according to claim 7, further comprising an inspection data pattern group generation unit realized by hardware such as I. 11. The memory inspection apparatus according to claim 7, wherein the inspection data pattern group is generated by a program stored in the inspection program memory. 12. The inspection data pattern group memory comprises:
The number of bits of the data bus width of the memory under test is n of 2
In the case of a power (n is an integer of 2 or more), a test data pattern group capable of inspecting a memory having a specific data bus width is stored in advance, and the data bus width of the memory under test set in the memory information setting means under test is set. 6. The memory inspection device according to claim 5, wherein the inspection device is selected from the inspection data pattern groups stored in advance based on the information of 1. 13. The inspection data pattern group memory comprises:
The inspection data pattern group that can inspect the memory of the specific data bus width used when the number of bits of the data bus width of the inspection memory is 2 n (n is an integer of 2 or more) is stored in advance, and the inspection target When the number of bits of the data bus width of the memory to be inspected set in the memory information setting means is 2 to the n-th power (n is an integer of 2 or more), it is used by selecting from a pre-stored inspection data pattern group, 6. The inspection data pattern group is generated and used when the number of bits of the data bus width is other than 2 to the n-th power (n is an integer of 2 or more).
The memory inspection device according to 1. 14. The memory inspection device according to claim 5, wherein the inspected memory information setting means sets information in each of the plurality of inspected memories. 15. A program for inspecting a memory under test is stored, and a predetermined test data pattern group used for the test is stored, wherein the test data pattern group has the same number of bits as the data bus width of the memory under test. A method of inspecting a memory, which uses a bit string generated by repeatedly dividing a binary number sequence consisting of 16. The inspection data pattern group comprising: an inspection program memory for storing a program for inspecting a memory to be inspected; and an inspection data pattern group memory for storing a predetermined inspection data pattern group used for the inspection. Is
An inspection program storage medium for a memory, which uses a bit string generated by repeatedly dividing a binary number sequence having the same number of bits as the data bus width of the inspected memory into two parts. 17. A test data pattern group used for testing a memory under test is provided, wherein the test data pattern group repeats two divisions of a binary sequence consisting of the same number of bits as the data bus width of the memory under test. A memory inspection program using the generated bit string.