KR0186012B1 - Address and data bus testing method for memory - Google Patents

Abstract

In a system using a RAM as a memory device, a method for accurately testing the address of a memory for accessing data and a disconnection or short circuit condition of a data bus is provided.

After clearing the data of all addresses in the memory to the first initial value and setting the data of the highest address to the second initial value, the stored data of the memory is sequentially read from the data of the lowest address, and the data read is Incrementing to the first initial value temporary setting address and repeating, and when the repetition is completed, the data of the highest address is checked whether the second initial value is applied and displaying that the data of the highest address is normal to the second initial value temporary address and the data bus. When the data of the most significant address is not the second initial value, a data bus error is displayed together with the address bus normal. Also, if the read data is not the first initial value, it is checked whether the second initial value is displayed, and if it is not the second initial value, an address and a data bus error are displayed. Together, the display of address bus errors enables accurate and rapid detection of disconnection or short circuits in data and address buses in memory.

Description

Memory address and data bus test method

1 is a block diagram for carrying out the present invention.

2 is a conventional flow chart.

3 is a flow chart according to the present invention.

4 is a memory map diagram of the present invention.

* Explanation of symbols for main parts of the drawings

10: central processing unit 20: memory

30: display unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing the address and data bus of a memory. In particular, in a system using a RAM as a memory device, an address of a RAM for accessing data and an open or short state of the data bus can be accurately determined. It is about how to test.

In general, a system using RAM as a memory device includes a central processing unit 10, a memory 20 using a RAM as a memory device, and a display unit 30 as shown in FIG. The device 10 is configured to test the state of the memory 20 and display the result on the display 30 so that the user or inspector can take action. In this case, the display unit 30 typically uses an LCD (Liquid Crystal Display) panel.

In this case, the CPU 10 tests the state of the memory 20 as shown in the flowchart of FIG. 2. Referring to FIGS. 1 and 2, the conventional memory test method will be described below. .

When the power is turned on now, the central processing unit 10 of FIG. 1 sets the data of all addresses of the memory 20 to 1 in step (2a) of FIG. At this time, if one byte of data is stored in the designated storage area of one address, the one byte of data is written in FFH (hexadecimal value). In step (2b), data of all addresses of the memory 20 is read, and it is checked whether or not it is the same as the data written in step (2c). At this time, if the two data are the same, the memory state good indication is displayed on the display unit 30 in step 2d. If the two data are different, the memory state bad indication is displayed on the display unit 30 in step 2e. Accordingly, the inspector or the user takes action according to the display state of the display unit 30.

The conventional memory device test method as described above can only check whether or not the correct data has been written. When the address bus is disconnected, it cannot be checked. Therefore, when there are many disconnected terminals, only a part of the allocated data storage area can be written. There was no. In addition, even in the case of mass production, even if the address bus is disconnected, there is a problem that can be shipped with good quality. In addition, since the short circuit of the address bus or the disconnection and short circuit of the data bus is judged by the malfunction of the main system, an accurate short circuit position cannot be found and there is a problem of a decrease in productivity.

Accordingly, an object of the present invention is to provide a method for easily and accurately testing a disconnection or short circuit condition of an address and a data bus of a memory in a system using a RAM as a memory device.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The block diagram for carrying out the present invention is the same as the first drawing described above and the same reference numerals.

3 is a flow chart according to the present invention, which clears data of all addresses A (O) -A (N) (where N is a non-zero natural number) of the memory 20, sets it to the first initial value OOH, and sets the highest address. An initial setting of setting the data of A (N) to the second initial value FFH and then setting the addressing value j to 0, and sequentially reading from the data of the lowest address A (O) while increasing the addressing value j. A first search step of repeating the read data until the address designation value j becomes a set value at a first initial value OOH; and the highest address A when the address designation value j becomes a set value in the first search process. A second search step of reading data of (N) to check whether the second initial value FFH is applied; and in the second search step, the data of the highest address A (N) is the second initial value FFH temporary address and the data bus are normal; Normal display A first error detection process indicating a data bus error by displaying data of the highest address A (N) when the data of the highest address A (N) is not the second initial value FFH in the detection process and the second search process; A third search step of checking whether the data read in the first search process is not the first initial value OOH, and whether the data read in the third search process is not the second initial value FFH. The second error detection process indicating the address and data bus error by displaying the data of the corresponding address A (j) and the highest address A (N) and the corresponding address A (j), and the read data of the third search process. The second initial value FFH temporary data bus is normally displayed together with the corresponding address A (j) and the highest address A (N) to indicate a third error detection process indicating an address bus error.

3 is a flowchart of a memory test function of the central processing unit 10 of FIG. 1, wherein a data storage area of the memory 20 is allocated from addresses A (O) to A (N), and 1 byte of each address is used. An example would be when specifying data storage.

FIG. 4 is a memory map diagram of the present invention. FIG. 4A sets data D0-D7 of the highest address A (N) of the memory 20 to the second initial value FFH and the remaining address A (0). Shows that data (D0-D7) of -A (N-1) is set to the first initial value 00H, and FIG. 4 (B) shows the address bus at the jth address A (j) of the memory 20. When an error is detected, the data bus of the address A (j) is in a good state, indicating that the data D0-D7 of the A (j) is set to the second initial value FFH.

Hereinafter, an operation of an embodiment of the present invention will be described in detail with reference to the block diagram of FIG. 1, the flowchart of FIG. 3, and the memory map of FIG. 4.

First, there are four cases in which an error may occur in memory.

I) If both the address and data bus are normal

Ii) Only the address bus is an error

I) only data bus error

I) If both the address and data bus are errors

Therefore, when testing the memory, it is necessary to detect all four cases as well as check the error terminal when an error occurs so that accurate and rapid action can be taken.

Accordingly, when the power supply is turned on, the central processing unit 10 of FIG. 1 clears the data of all addresses in the memory 20 to the first initial value 00H, and then writes the second initial value FFH to the highest address A (N). This is read from the lowest address A (0) to the (N-1) th address A (N-1). In this process, if there is a j-th address A (j) where a value other than the first initial value 00H is obtained, the position is disconnected or short-circuited if only the wrong bit is checked compared to the highest address A (N).

If the data value at this time is read and only the bit that is 0 is checked, the position is a disconnected or shorted data terminal.

If the first initial value 00H is obtained in the above process, if there is no error, the address bus can detect the disconnected or shorted terminal by reading the data value of the highest address A (N) and checking only the bit that is zero. The method is based on the known fact that a disconnected input of a C-MOS memory is read as zero.

The above will be described with reference to the flowchart of FIG. 3.

When the power is turned on now, the central processing unit 10 of FIG. 1 clears data of all addresses from A (0) to A (N) of the memory 20 in step (3a) of FIG. After setting to 00H, in step 3b, the data of the highest address A (N) is written to the second initial value FFH and set. Accordingly, the memory map of the memory 20 is as shown in FIG. 4 (a).

In step (3c), the address designation value j is set to an initial value 0 in order to read the data of the memory 20 while sequentially increasing the address from the lowest address A (0). This is because all error terminals cannot be detected unless the address terminal reads from the lowest address A (0) when there are a plurality of errors.

Next, in step (3d)-(3e), the data of the lowest address A (0) whose address designation value j is 0 is read from the memory 20, and is cleared in step (3a). Check it.

If the first initial value is 00H, there is no problem. Therefore, go to step (3f) to check whether the address designation value j is (N-1). If not, proceed to step (3g) to increase the address designation value j by one. After that, the above-described process is repeated by looping to step (3e).

That is, as the address designation value j increases, the address is read sequentially while the address is sequentially increased from the lowest address A (0) to the (N-1) th address A (N-1) to determine whether the first initial value is 00H. To check.

If all data up to the (N-1) th address A (N-1) in step (3f) are the first initial value 00H, it is determined that the address bus is normal, and the process proceeds to (3h) to check the data bus. . In step (3h), data of the most significant address A (N) written in step (3b) is read, and it is checked in step (3i) whether it is the second initial value FFH. If the second initial value FFH is displayed on the display unit 30 that both the address and the data bus are normal in step (3j), and if the second initial value FFH is not, the data of the highest address A (N) is displayed in step (3k). The display unit 30 displays the data bus error. A terminal corresponding to a bit other than 1 in the data of the highest address A (N) displayed in step (3k) becomes a data bus error occurrence terminal.

On the other hand, if the data of the j-th address A (j) is read other than the first initial value 00H in steps (3d) to (3e), the address bus is in an error state.

In this case, the data bus must also be checked, so the process proceeds to step 3l to check whether the data of the address A (j) is the second initial value FFH.

If the second initial value FFH in step (3l) is also an error in the data bus, in step (3m) the data of the corresponding address A (j) and the highest address A (N) and the corresponding address A (j) is displayed. Display at the same time, indicating that both the address and data bus are errors.

Comparing the corresponding address A (j) and the highest address A (N) displayed in the step (3m), the terminals corresponding to different bits are the address bus error occurrence terminal and the data bus error occurrence terminal is the (3k) step You can find it like this:

If the data of the corresponding address A (j) is the second initial value FFH in step (3l), the memory map of the memory 20 is as shown in FIG. 4 (b). The address A (j) and the highest address A (N) are displayed together with the fault, indicating an address bus error. At this time, the address bus error occurrence terminal may be found as in step (3m).

By performing the above process, both the error occurrence terminal of the address and the data bus can be inspected.

As described above, the present invention can prevent a decrease in memory efficiency caused by disconnection of an address bus of a memory, which is the biggest problem of the prior art, in a system using a RAM as a memory device. Accurately identifying shorted areas can reduce repair time during production and use.

Claims (5)

A memory 20 having a storage area for storing and reading data, a central processing unit 10 for accessing and processing data in the memory 20, and a system operating state under control of the central processing unit In a system having a display unit (30), a memory address and data bus test method, the data of all addresses of the memory is cleared and set to a first initial value, and the data of the highest address is set to a second initial value. And a first search process of sequentially reading the stored data of the memory from the data of the lowest address and incrementing and reading the read data up to the first initial value temporary setting address, and the first search process. A second step of checking whether the data of the highest address is applied to the second initial value when it is repeatedly completed up to the address; A color detection process, a normal detection process for displaying data of the highest address in the second search process and the second initial value temporary address and data bus in normal state, and data of the highest address in the second search process A first error detection process of displaying a data bus error on the display unit together with an address bus normal when the second initial value is not the second initial value; and when the data read in the first search process is not the first initial value. A third search process for checking whether the second initial value is applied; a second error detection process for displaying an address and a data bus error on the display unit when the second initial value is not found in the third search process; and the third search. In the process, the address bus error is displayed on the display unit together with the second initial value data bus normal. The address and data bus test method of the memory, characterized in that the third error detection process. The method of claim 1, wherein the first initial value is set to 00H and the second initial value is set to FFH. 3. The address and data bus test of a memory according to claim 2, wherein the address and data bus error display of the second error detection process displays the corresponding address and the highest address where the address bus error occurred and the data of the corresponding address. Way. 4. The method of claim 3, wherein a terminal of a bit having different data of the most significant address from the corresponding address issued by the address bus error is an address bus error occurrence terminal. And a data bus terminal of a data bit other than 1 in the data of the corresponding address where the address bus error occurs, the data bus error generating terminal.