JP3538298B2 - Semiconductor integrated circuit inspection apparatus and data setting method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a per-pin configuration having hardware resources for each pin that can be individually connected to a connection portion such as a connection node on a chip of a semiconductor integrated circuit or a connection terminal of a package. The present invention relates to an inspection device and a data setting method thereof.

[0002]

2. Description of the Related Art Conventionally, a tester 1 having a per-pin configuration as shown in FIG. 7 has been used as a semiconductor integrated circuit inspection device for shipping inspection of semiconductor integrated circuits. In the tester 1 having a per-pin configuration, a hardware resource 4 is provided for each pin together with a common controller 2 and a device power supply 3. The hardware resources 4 ₁ , 4 ₂ ,..., 4 _n from the 1st pin to the nth pin can individually set the waveform timing, voltage level, pattern data, etc. given to the semiconductor integrated circuit to be tested. The controller 2 selects one of the device power supply 3 and the hardware resources 4 ₁ , 4 ₂ ,... 4 _n by an address signal transmitted via the address bus 5, and sets data via the data bus 6. Or input data.

As a semiconductor integrated circuit inspection device, a shared resource type tester is known in addition to the per-pin resource type tester 1 as shown in FIG. The shared resource type tester has a configuration in which resources such as a timing generator are commonly used for a plurality of pins. All testers in the early days used such a shared resource method, and the number of resources was small, so that hardware costs could be kept low. Although the shared resource type tester has such advantages, there is a problem that individual data cannot be set for each pin because one resource is commonly used by a plurality of pins.

[0004] On the other hand, the tester of the per-pin resource system has all the resources for each pin, and thus has an advantage that the data can be freely set for each pin. However, there is a problem that the time required for data setting becomes enormous due to a large increase in hardware resources and an increase in the number of setting items. Although the cost increase due to an increase in the amount of hardware was initially a problem, due to the development of design and manufacturing techniques for semiconductor integrated circuits for specific applications called ASICs, semiconductor integrated circuits can be manufactured economically even in relatively small lots. It is becoming possible to use such an ASIC as a resource for each pin of a tester having a per-pin configuration. Using the same ASIC for each pin,
The cost can be reduced rather than a shared resource type tester having individually configured resources, and since the same configuration can be used for each pin, advantages such as easy calibration can be obtained. For this reason, the time required to set data for the hardware resource for each pin is a much larger problem than the above-described problem.

A prior art for solving such a problem is disclosed in, for example, JP-A-6-94798. FIG. 8 shows the basic concept of this prior art. The prior art tester 10 has a group select circuit 11, a pin select circuit 12, and a resource select circuit 13 for each pin, and the resources 14 can be selected collectively as a group or individually. It is possible. When a group is selected, an address signal is transmitted from a controller or the like via the address bus 15 and setting data is transmitted from the data bus 16. The storage content of the participant memory 17 accessed by the address signal sent to the address bus 15 is set to 11, and if a group select signal is given, the group select circuit 11 simply represented by an AND gate is used. It becomes enabled. The pin select circuit 12, which is simply represented by an OR gate, is enabled when the group select circuit 11 is enabled or when a pin select signal is given.
It becomes enabled. When a resource select signal is further applied, the resource select circuit 13 represented by an AND gate is enabled, and the individual resources 14 can be accessed. In an actual semiconductor integrated circuit test, a plurality of pin data may be the same, and by providing hardware capable of simultaneously setting data for a plurality of pins on which the same data can be set, the data setting can be performed. To reduce the time required,
The above-mentioned problem is solved.

[0006]

In the prior art described above,
In order to reduce the time required for data setting when the number of hardware resources is large, a pin tester is used to divide pins into groups using participant memory, and data can be set in parallel in group units. However, the data that can be set is the same data for each group. Although the grouping can be changed by rewriting the storage contents of the participation memory, it is necessary to repeat the data setting for the participation memory for each pin a plurality of times in order to change the pin combination.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit inspection apparatus and a data setting method thereof which can easily perform grouping of pins by a tester having a per-pin configuration.

Another object of the present invention is to provide a semiconductor integrated circuit inspection apparatus capable of simultaneously setting data for a plurality of groups.

It is still another object of the present invention to provide a semiconductor integrated circuit inspection apparatus capable of simultaneously setting different data for a plurality of groups.

[0010]

The present invention comprises a plurality of pins individually connectable to a connection portion of a semiconductor integrated circuit,
In a semiconductor integrated circuit inspection device that has the same hardware resource for each pin and the hardware resource for each pin can be connected to a common controller, the controller uses three predetermined portions of an address bus. The first part can transmit broadcast enable information, the second part can transmit group identification valid information, and the third part can transmit individual identification information. When validating the group identification valid information, Group identification information is transmitted using a predetermined information portion, data is transmitted using a data portion of the data bus other than the information portion, and provided for each pin, the group identification information can be set. Group setting means and individual identification information provided for each pin and individually identifying each pin can be set A separate setting means, provided for each pin, receiving the second part of the address bus and the information part of the data bus, the group identification validity information is valid, and the received group identification information and the group setting means are set. Group comparing means for comparing whether or not the group identification information matches the group identification information, and a third part of the address bus which is provided for each pin, receives the third part of the address bus, and sets the received individual identification information and the individual setting means. Individual comparing means for comparing whether or not the individual identification information is coincident with each other, provided for each pin,
When the broadcast enable information received from the first portion of the address bus is valid or determined by the group comparing means or the individual comparing means to be coincident, the hardware based on the data transmitted from the controller via the data bus Control means for enabling access to resources.

According to the present invention, a semiconductor integrated circuit inspection apparatus includes a plurality of pins that can be individually connected to connection portions such as connection terminals and connection nodes of the semiconductor integrated circuit, and the same hardware is provided for each pin. This is a per-pin resource method having resources, and data is set by a common controller. Group setting means, individual setting means, group comparing means, individual comparing means, and control means are provided for each pin. Group identification information and individual identification information can be set in the group setting means and the individual setting means, respectively. The controller uses three predetermined portions of the address bus, and can transmit broadcast enable information in the first portion, group identification valid information in the second portion, and individual identification information in the third portion. When the controller enables the broadcast enable information on the first portion of the address bus, the control means for each pin enables the controller to access hardware resources via the data bus, so that the controller Can access resources simultaneously. When the controller makes the group identification validity information valid in the second part of the address bus, the group identification information transmitted via the information part of the data bus matches the group identification information set in the group setting means. Control means enables the controller to access the hardware resources via the data portion of the data bus, so that the controller can simultaneously access the hardware resources of the pins belonging to the group having the same group identification information.
The control means of the pin whose individual identification information transmitted from the controller via the third part of the address bus matches the individual identification information set in the individual setting means is configured to access the hardware resource from the controller via the data bus. , The controller can individually access the hardware resources of the pins whose individual identification information matches.

Further, according to the present invention, a plurality of pins which can be individually connected to a connection portion of a semiconductor integrated circuit are provided, each pin has an equivalent hardware resource, and each pin has a common hardware resource. In a semiconductor integrated circuit inspection device connectable to a controller, the controller uses three predetermined portions of an address bus, a first portion includes broadcast enable information, a second portion includes group identification valid information, and a third portion. In the part, the individual identification valid information can be transmitted, and when validating the group identification valid information or the individual identification valid information,
Group identification information or individual identification information is transmitted using a predetermined information portion of the data bus, and data is transmitted using a data portion of the data bus other than the information portion. Provided, a group setting means capable of setting group identification information, provided for each pin, individual setting means capable of setting individual identification information for individually identifying each pin, provided for each pin, Receiving the second part of the address bus and the information part of the data bus, and determining whether the group identification validity information is valid and whether the received group identification information matches the group identification information set in the group setting means; And a group comparing means provided for each pin, for receiving the third part of the address bus and the information part of the data bus, and the individual identification validity information is valid, Individual comparing means for comparing whether the received individual identification information matches the individual identification information set in the individual setting means, and a broadcast provided for each pin and received from the first part of the address bus Control means for enabling access to the hardware resources by data sent from the controller via the data bus when the enable information is valid or determined to be identical by the group comparing means or the individual comparing means; And a semiconductor integrated circuit inspection device.

According to the present invention, a semiconductor integrated circuit inspection apparatus includes a plurality of pins that can be individually connected to connection portions such as connection terminals and connection nodes of the semiconductor integrated circuit, and the same hardware is provided for each pin. This is a per-pin resource method having resources, and data is set by a common controller. Group setting means, individual setting means, group comparing means, individual comparing means, and control means are provided for each pin. Group identification information and individual identification information can be set in the group setting means and the individual setting means, respectively. The controller uses three predetermined portions of the address bus. The first portion can transmit broadcast enable information, the second portion can transmit group identification valid information, and the third portion can transmit individual identification valid information. When the controller enables the broadcast information on the first part of the address bus, the control means of each pin enables the controller to access hardware resources via the data bus, so that the controller can control the hardware resources of all pins. Can be accessed simultaneously. If the controller is on the second address bus
When validating group identification validity information,
The control means for the pin whose group identification information transmitted via the information part of the data bus matches the group identification information set in the group setting means is configured to access the hardware resource from the controller via the data part of the data bus. , The controller can simultaneously access the hardware resources of the pins belonging to the group having the matching group identification information. When validating the individual identification information in the third part of the address bus from the controller, the individual identification information transmitted via the information part of the data bus is the same as the individual identification information set in the individual setting means. The control means allows the controller to access the hardware resource via the data portion of the data bus, so that the controller can individually access the hardware resource of the pin whose individual identification information matches.

Further, in the present invention, when the group identification valid information or the individual identification valid information is valid, the data bus is divided such that a plurality of sets each including the information portion and the data portion are formed. The control means for each pin controls whether the group identification information or the individual identification information transmitted from the controller via the information portion of each set of the data bus is the group identification information or the group identification information set in the group setting means or the individual setting means. When matching with the individual identification information, it is possible to access the hardware resource by the data transmitted from the controller via the same set of data parts.

According to the present invention, the data bus is divided into a plurality of sets, and data can be individually transmitted to different sets from the controller. The control means for each pin is controlled by the address bus. When the indicated group identification effective information or individual identification effective information is valid, the group identification information or the individual identification information transmitted to each set of information portions is received. If the received group identification information or individual identification information matches the group identification information or individual identification information set in the group setting means or the individual identification means,
The control means enables access to the hardware resource by data received through the same set of data parts as the set in which the matched group identification information or individual identification information is transmitted in the information part. Can be accessed simultaneously by specifying a group or individual pins.

Further, the present invention is characterized in that the group setting means and the individual setting means have registers each of which can set group identification information and individual identification information by the controller.

According to the present invention, since the group setting means and the individual setting means have registers in which the group identification information and the individual identification information can be respectively set by the controller, efficient data setting is performed while changing the grouping. It is also possible.

Further, according to the present invention, a plurality of pins that can be individually connected to a connection portion of a semiconductor integrated circuit are provided, each pin has the same hardware resource, and the hardware resource for each pin is transferred from the controller to the hardware resource for each pin. In a data setting method of a semiconductor integrated circuit testing device for setting data, a controller uses three predetermined portions of an address bus, a first portion has broadcast enable information, and a second portion has group identification validity. In the information and the third part, individual identification information can be transmitted. When the group identification validity information is made valid, the group identification information is transmitted using a predetermined information part of the data bus, and the data bus. Data is transmitted using the data portion excluding the information portion, and group identification information is provided for each pin. When the broadcast enable information transmitted via the first part of the address bus is valid, hardware is provided by data transmitted from the controller via the data bus at all pins. When the group identification validity information transmitted through the second part of the address bus is valid, the group in which the group identification information transmitted through the information part of the data bus is set is enabled. The pin that matches the identification information,
The individual identification information, which enables the data to be set in the hardware resource by the data transmitted from the controller via the data portion of the data bus, and is set with the individual identification information transmitted via the third portion of the address bus A data setting method for a semiconductor integrated circuit inspection device, characterized in that it is possible to set data in a hardware resource by data transmitted from a controller via a data bus with a pin corresponding to (1).

According to the present invention, the group identification information and the individual identification information are set for each pin of the semiconductor integrated circuit inspection device having the hardware resource for each of the plurality of pins. The common controller for setting data is
Three predetermined portions of the address bus are used. Broadcast enable information can be transmitted in the first portion, group identification validity information can be transmitted in the second portion, and individual identification information can be transmitted in the third portion. When the controller enables the broadcast enable information on the first part of the address bus, the controller can access hardware resources via the data bus, so that the controller can simultaneously access the hardware resources of all pins. it can. When the controller makes the group identification valid information valid in the second part of the address bus, the controller transmits the group identification information transmitted through the information part of the data bus to the pin corresponding to the set group identification information. Can access the hardware resources via the data portion of the data bus, so that the controller can simultaneously access the hardware resources of the pins belonging to the group whose group identification information matches. When the individual identification information sent from the controller via the third part of the address bus matches the set individual identification information, the controller can access the hardware resource via the data bus, and thus the controller Data can be individually set for the hardware resources of the pins whose individual identification information matches.

Further, according to the present invention, a plurality of pins that can be individually connected to the connection portion of the semiconductor integrated circuit are provided, each pin has the same hardware resource, and the hardware resource for each pin is transferred from the controller to the hardware resource for each pin. In a data setting method of a semiconductor integrated circuit testing device for setting data, a controller uses three predetermined portions of an address bus, a first portion has broadcast enable information, and a second portion has group identification validity. The information and the third part can transmit the individual identification validity information. When the group identification validity information or the individual identification validity information is made valid, the group identification information or the predetermined information part of the data bus is used. The data part which transmits the individual identification information and excludes the information part in the data bus And the data is transmitted, and the group identification information and the individual identification information are set for each pin. When the broadcast enable information transmitted via the first part of the address bus is valid, all the pins are used. It is possible to set data in a hardware resource by data transmitted from the controller via the data bus, and when the group identification validity information transmitted via the second part of the address bus is valid, the information part of the data bus is enabled. At the pin that matches the group identification information set by the group identification information sent via
Each of the controllers enables data to be set in the hardware resource by data transmitted from the controller via the data portion of the data bus, and when the individual identification validity information transmitted via the third portion of the address bus is valid, The pin that matches the individual identification information that is set via the data part of the corresponding information can be set to the hardware resource by the data sent from the controller via the data part of the data bus. A data setting method for a semiconductor integrated circuit inspection device.

According to the present invention, the group identification information and the individual identification information are set for each pin of the semiconductor integrated circuit inspection device having the hardware resource for each of the plurality of pins. The common controller for setting data is
Using three predetermined portions of the address bus, the first portion can transmit broadcast enable information, the second portion can transmit group identification valid information, and the third portion can transmit individual identification valid information. When the controller enables the broadcast enable information on the first part of the address bus, the controller can access hardware resources via the data bus, so that the controller can simultaneously access the hardware resources of all pins. it can. When the controller makes the group identification valid information valid in the second part of the address bus, the controller transmits the group identification information transmitted through the information part of the data bus to the pin corresponding to the set group identification information. Can access the hardware resources via the data portion of the data bus, so that the controller can simultaneously access the hardware resources of the pins belonging to the group whose group identification information matches. When the individual identification validity information is enabled from the controller in the third part of the address bus, the individual identification information transmitted through the information part of the data bus is transmitted from the controller to the pin corresponding to the set individual identification information. Since access to hardware resources via the data portion of the data bus becomes possible,
The controller can individually set data for the hardware resources of the pins whose individual identification information matches.

Further, in the present invention, when the group identification valid information or the individual identification valid information is valid, the data bus is divided so that a plurality of sets each including the information portion and the data portion are formed. When the group identification information or the individual identification information transmitted from the controller via the information portion of each set of the data bus matches the set group identification information or the individual identification information,
It is characterized in that it is possible to set data in a hardware resource by data transmitted from the controller via the same set of data parts.

According to the present invention, the data bus is divided into a plurality of sets, and the data can be individually transmitted to different sets from the controller. When the group identification information or the individual identification information indicated by a part of the address bus is valid, the group identification information or the individual identification information transmitted to the information part of each set is set to each pin. Or, if the individual identification information matches, it is possible to set the data to the hardware resource by the data received through the same set of data parts as the group in which the matched group identification information or individual identification information is transmitted in the information part. Therefore, a plurality of groups or individual pins can be designated from the controller and data can be set simultaneously.

Further, in the present invention, a register is provided for each of the pins so that the group identification information and the individual identification information can be set by the controller.

According to the present invention, since each pin is provided with a register in which the group identification information and the individual identification information can be set by the controller, efficient data setting can be performed while changing the grouping. is there.

[0026]

[0027]

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a schematic configuration of a form on which the present invention is based. FIG. 1A shows an electrical configuration of the tester 20, and FIG. 1B shows a partial configuration of an address bus supplied to hardware of the tester 20. The tester 20 has a per-pin configuration, and a control circuit 21 is provided for each pin.
When the identification information given from the common controller 22 matches the identification information set in the setting circuit 23 in advance, the hardware resource 24 can be accessed from the controller 22. In the present basic mode, a group ID as group identification information and an individual pin ID as individual identification information are provided from the controller 22 via the address bus 25.

As shown in FIG. 1B, the address signal supplied from the address bus has a width of 1 + m + n + p bits, and the MSB as the most significant bit is a broadcast enable signal. The next m bits represent a group ID code. The next n bits represent an individual pin ID code. The lower-order p bits represent resource selection data. The controller 22 as shown in FIG. 1A includes a CPU, a program memory, and the like.
Are generally larger than those shown in FIG. 1B. Therefore, the data bus width provided to the tester 20 is a part of the data bus width transmitted by the CPU of the controller 22, and the hardware resources 24 for each pin are occupied in a part of the memory space of the CPU. Can be accessed.

The setting circuit 23 shown in FIG. 1A includes a group ID storage register 31 and an individual pin ID storage register 32 which can be accessed from the controller 22 and can store the group ID and the individual pin ID. The group ID storage register 31 and the individual pin ID storage register 32 are arranged in the memory space of the controller 22 so as to be in an area different from the hardware resource 24 for each pin.

The control circuit 21 includes a broadcast enable signal detection circuit 33 and a group ID code comparator 3
4, an individual pin ID code comparator 35 and an access permission circuit 36 are included. From the controller 22, a hardware enable signal for enabling the control circuit 21 for each pin of the tester 20 is provided. The hardware enable signal is created by decoding an address higher than the address signal shown in FIG. 1B among the address signals sent from the CPU of the controller 22.

The broadcast enable signal detection circuit 33 is a two-input AND gate. When the hardware enable signal has a logical value "1" and the broadcast enable signal shown in FIG. 1B has a logical value "1". Outputs a logical value of "1". When the hardware enable signal has the logical value “1”, the group ID code comparator 34 compares the group ID data stored in the group ID storage register 31 with the address bus 2.
5 with the group ID code given via
When they match, a logical value “1” is output. Individual pin ID
The code comparator 35 compares the individual pin ID data stored in the individual pin ID storage register 32 with the address bus 25.
Individual pin ID given from the controller 22 through the
The logic value is compared with the code, and when the comparison result matches and the hardware enable signal has the logic value “1”, the logic value “1” is output. The access permission circuit 36 has three inputs O
If the absolute value from the broadcast enable signal detection circuit 33, the group ID code comparator 34, or the individual pin ID code comparator 35 is at least one logical value "1", the logical value is "1". Is supplied to the address decoder 27 as an enable signal. The address decoder 27 decodes the lower p bits of the address bus 25 and selects a hardware resource 24.

FIG. 2 shows a tester 20 of the basic form shown in FIG.
Shows the procedure for setting data. The procedure starts from step a1, and data to be set is input in step a2. The data to be set is determined based on the specifications of the semiconductor integrated circuit to be inspected. In step a3, the group ID and the individual pin ID are set for the group ID storage register 31 and the individual pin ID storage register 32 for each pin, corresponding to the hardware resource commonly set by the setting data. In step a4, it is determined whether or not there is broadcast data in the setting data. If there is broadcast data, the address M given to the control circuit 21 for each pin in step a5
SB = 1 is set, and data for resource selection is set in the lower p bits. In step a6, setting data is output to the data bus, and common data setting is performed for the hardware resources of each pin. When the setting data output in step a6 is completed, the process returns to step a4. Steps a4 to a6 are repeated, and when all the broadcast data has been transmitted, the process proceeds to step a7.

At step a7, it is determined whether or not there is group data in the setting data. If there is group data, in step a8, the MSB of the address is set to 0, the group ID is set to the next m bits, all 0s are set to the next n bits, and the resource selection data is set to the lower p bits. I do. At step a9, setting data is output from the data bus. Step a7 to Step a
When the transmission of all the group data is completed by repeating Steps 9 through 9, it is determined in Step a10 whether or not there is individual data in the setting data. If there is individual data, in step a11, all 0s are set from the MSB to the (m + 1) th bit of the address, the individual pin ID code is set in the next n bits, and data for resource selection is set in the lower p bits. . At step a12, setting data is output from the data bus. Steps a10 to a12 are repeated as long as there is individual data, and when there is no more individual data, the procedure ends in step a13.

For example, it is assumed that the same timing data is set for hardware resources 24 for 10 pins in an actual test program. This one
In order to perform data setting with the 0 pins as the same group, data 1 is sequentially written, for example, as group 0 into the group ID storage register 31 of the resources for 10 pins at step a3 in FIG. Next, in steps a7 to a9, data for 10 pins can be set simultaneously for group 0 once. In this example only, it is necessary to access each pin in order to individually set the group ID for the 10 pins in the group ID storage register 31, so that the data is set once for the hardware resource 24. Although it can be performed, the time required for data setting remains the same as when the data setting is performed individually. However, usually
Once a group is determined, it hardly changes after that. Therefore, in this basic mode, the time required for data setting can be much shorter than in the case of individually setting data in repeated condition setting.

Further, if the broadcast enable signal is used, the same data can be set to all pins at the same time, so that data setting such as opening the driver connection relays of all pins collectively can be performed at high speed. It can be carried out. Of course, individual pin ID for each pin
Since it has the storage register 32 and data can be individually set by an individual pin ID code, it is easy to set data only to a specific pin. The group ID and individual pin ID of each pin are stored in the controller 22.
Instead of storing in the group ID storage register 31 or the individual pin ID storage register 32 accessible from
It can be set mechanically with a DIP switch, etc.
For example, the ROM can be replaced as necessary, or it can be rewritten as electrically programmable.

FIG. 3 shows a schematic electrical configuration of a tester 40 which is a semiconductor integrated circuit inspection device according to an embodiment of the present invention. In the present embodiment, portions corresponding to the basic form in FIG. 1A are denoted by the same reference numerals, and redundant description will be omitted. The tester 40 has a hardware resource 24, an address decoder 27, a group ID storage register 31, an individual pin ID storage register 32, and a control circuit 41 for each pin of the per-pin configuration. In the control circuit 41, a broadcast enable signal detection circuit 43, group ID code comparators 44a and 44b, individual pin IDs
Code comparator 45, access permission circuit 46, switch 47
And a group access enable signal detection circuit 48. The broadcast enable signal detection circuit 43 and the group access enable signal detection circuit 48 each formed by a two-input AND gate include a hardware enable signal having a logical value “1” when the controller attempts to access the hardware of the tester 40. , And outputs a logical value “1” when the broadcast enable signal or the group access enable signal has a logical value “1”. In the individual pin ID code comparator 45, the hardware enable signal has the logical value “1”, and the individual signal ID data stored in the individual pin ID storage register 32 matches the individual pin ID code given from the address bus 25. Output a logical value "1". The access permission circuit 46 composed of a three-input OR gate outputs a logical value "1" from any of the broadcast enable signal detection circuit 43, the group access enable signal detection circuit 48, and the individual pin ID code comparator 45. Output a logical value "1". The output of the access permission circuit 46 is a logical value "1"
, The output of the address decoder 27 becomes valid,
The lower p bits of the address bus 25 select one of the hardware resources 24.

In the present embodiment, the data bus 26 can be divided into two, and the group ID code and the setting data can be provided separately for each group. At this time, two group ID code comparators 44a and 44b are provided, and the two group ID codes given via the data bus 26 are compared with the group ID data stored in the group ID storage register 31 and matched. In this case, a logical value "1" is output. Group ID code comparators 44a, 44b
Is activated when the group access enable signal detecting circuit 48 outputs a logical value “1”, and the output is
7 individually. The output from the access permission circuit 46 is also given to the switch 47. The switch 47 switches the setting data provided via the data bus 26 to the one having the same group ID code, and switches to the preset one at the time of broadcasting or at the time of individual pin access. The setting data switched and selected by the switch 47 is set in the hardware resource 24 selected by the address decoder 27.

FIG. 4 shows the bit configuration of the address bus and the data bus of this embodiment. In the bit configuration of the address bus shown in FIG. 4A, the MSB is a broadcast enable signal, and if the logical value is "1", the broadcast is valid. The next one bit of the MSB is used as a group access enable signal. If the logical value is “1”, the bit is valid. The data bus shown in FIG. 4B, in which the next n bits are used as an individual pin ID code for identifying a pin and the remaining p bits are used as resource selection bits for selecting hardware at each pin, The upper m bits of the two divided bit strings are set as bits for designating a group ID, and the remaining bits are set as data for the group. When the data bus is divided into two in this way, two groups of group IDs and data can be derived at the same time, and the time required for data setting can be reduced by half. When the data bus width of the CPU used for the controller becomes large and the width of the data bus to be set in the hardware resource for each pin may be small,
Further, the number of divisions can be increased. If the data can be divided into n groups, different data can be set for n groups by one access, and the time required for data setting can be greatly reduced.

FIG. 5 shows a schematic configuration of a tester 50 as a semiconductor integrated circuit inspection apparatus according to still another embodiment of the present invention. FIG. 1A shows a tester 50 according to the present embodiment.
The same reference numerals are given to portions corresponding to the tester 20 shown in FIG. The tester 50 having a per-pin configuration according to the present embodiment includes a hardware resource 24, an address decoder 27, a group ID storage register 31, an individual pin ID storage register 32, and a control circuit 51 for each pin. In the present embodiment, the group ID code and the individual pin ID code are provided via the data bus 26 together with the setting data. Moreover, the ID code and the setting data are given at the same time by dividing the data bus 26 into two sets. Whether the data bus is provided with the group ID code or the individual pin ID code is indicated by a group access enable signal or an individual pin access enable signal included in the address bus.

The control circuit 51 includes a broadcast enable signal detecting circuit 53, group ID code comparators 54a and 54b, and individual pin ID code comparators 55a and 55.
5b, an access permission circuit 56, a switch 57, a group access enable signal detection circuit 58, and an individual pin access enable signal detection circuit 59. The broadcast enable signal detection circuit 53, the group access enable signal detection circuit 58, and the individual pin access enable signal detection circuit 59 are configured such that the hardware enable signal has a logical value of “1” and the broadcast enable signal, the group access enable signal, or the individual pin access enable. When the signal has the logical value “1”, the logical value “1” is output. When the group access enable signal detection circuit 58 outputs the logical value “1”, the group ID code comparators 54 a and 54 b output the group ID stored in the group ID storage register 31.
A group 1 ID code and a group 2I which are divided into two groups via data and a data bus 26;
Each D code is compared. When the individual pin access enable signal detection circuit 50 outputs the logical value "1", the individual pin ID code comparators 55a and 55b output the individual pin IDs stored in the individual pin ID storage register 32.
The data is compared with an individual pin 1 ID code and two individual pin 2 ID codes provided from the data bus 26, and outputs a logical value "1" if they match.

The access permission circuit 56 is a three-input OR gate, and the broadcast enable signal detection circuit 5
3. If one of the group access enable signal detection circuit 58 and the individual pin access enable signal detection circuit 59 outputs a logical value “1”, the logical value “1”
To the address decoder 20 to permit the selection of the hardware resource 24 by the lower p bits of the address bus 25. The data set in the hardware resource 24 is switched by the switch 57 in accordance with the outputs of the group ID code comparators 54a and 54b, the individual pin ID code comparators 55a and 55b, and the access permission circuit 56. The switch 57 is provided with a group ID or an individual I
The setting data with the matching D is selected from one of the divided data buses 26, or the setting data at the time of broadcasting is selected from a predetermined one and set in the hardware resource 24.

FIG. 6 shows the bit configuration of the address bus and the data bus of this embodiment. FIG. 6A shows the bit configuration of the address bus. The MSB is a broadcast enable signal, the next one bit is a group access enable signal, the next one bit is an individual pin access enable signal, and the lower p bits are for resource selection. Separate from bits. The broadcast enable signal, the group access enable signal, or the individual pin access enable signal is valid when the logic value is “1”. FIG. 6 (b)
Indicates that the logical value of the group access enable signal is "1"
Indicates the bit configuration of the data bus at the time of group access. The data bus is divided into two, and the upper m bits of each set indicate the ID code of the group, and the remaining bits indicate data. FIG. 6C shows the bit configuration of the data bus when the individual pin access enable signal has the logical value “1”, that is, when the individual pin is accessed. As in the case of group access, the data bus is divided into two
Bits are used as IDs of individual pins, and data is allocated to the remaining bits.

[0044]

As described above, according to the present invention, the group setting means and the individual setting means provided for each pin include:
The group identification information and the individual identification information are set respectively, and when the group identification information or the individual identification information sent from the controller matches the set identification information, the control means for each pin sets the Since the controller can access hardware resources, it is possible to easily perform data setting as a group for a plurality of pins and individual data setting for each pin. The combination of pins forming a group can be performed by setting common group identification information, so that the combination can be easily changed. Also,
If you enable broadcast information from the controller, you can set data for all pins at the same time, so hardware resources that set the same data for all pins and almost all pins On the other hand, data can be set efficiently for hardware resources that set the same data. Further, when validating the group identification information using a part of the address bus, the group identification information is provided from the controller to the control means for each pin via the data bus, so that the address bus can be effectively used. Access to hardware resources of each pin can be performed.

[0045]

Further, according to the present invention, the group identification information and the individual identification information are set in the group setting means and the individual setting means provided for each pin, respectively.
The hardware resources can be accessed based on the broadcast enable information, the group identification information, or the individual identification information sent from the controller. When the controller enables the broadcast enable information on the first portion of the address bus, the control means for each pin enables the controller to access hardware resources via the data bus, so that the controller Can access resources simultaneously. When the controller validates the group identification valid information or the individual identification valid information in the second or third part of the address bus, the group identification information or the individual identification information transmitted via the information part of the data bus is used for setting the group. The control means of the pin corresponding to the group identification information or the individual setting information set in the means or the individual setting means enables the controller to access hardware resources via the data portion of the data bus, so that the controller It is possible to access the hardware resources of the pins belonging to the group whose identification information matches or the pins whose individual identification information matches.

Further, according to the present invention, the data bus is divided into a plurality of sets, and the control means for each pin controls each group when the group identification valid information or the individual identification valid information indicated by the address bus is valid. If the group identification information or the individual identification information sent to the information part of the above is received and matches the group identification information or the individual identification information set in the group setting means or the individual identification means, the control means sets the same set of data. Since the hardware resource can be accessed by the data received via the part, a plurality of groups or individual pins can be designated from the controller and accessed simultaneously. Since the data bus can be divided into a plurality of sets and a plurality of data can be set at the same time, the time required for data setting can be reduced.

Further, according to the present invention, since each pin has a register in which the group identification information and the individual identification information can be set by the controller, efficient data setting can be performed while changing the grouping.

Further, according to the present invention, the group identification information and the individual identification information are set for each pin of the semiconductor integrated circuit inspection device having a hardware resource for each of the plurality of pins, and the controller operates the address bus. Second
The group identification validity information is validated in the portion, and the group identification information transmitted through the information portion of the data bus, or the group identification information in which the individual identification information transmitted through the third portion of the address bus is set, or When the data matches the individual identification information, the data can be set from the controller to the hardware resource.
The controller can make data settings to hardware resources of multiple pins or individual pins.

Further, according to the present invention, the group identification information and the individual identification information are set for each pin of the semiconductor integrated circuit inspection device having a hardware resource for each of the plurality of pins, and the controller operates the address bus. Second
The group identification valid information or the individual identification information is validated in the portion or the third portion, and the group identification information or the individual identification information set via the data bus information portion is set to the group identification information or the individual identification information, respectively. When they match, the controller can set data to hardware resources, so that the controller can set data to hardware resources of a plurality of pins or individual pins. Since the group identification information and the individual identification information are transmitted via the data bus, the address bus can be used with a margin for designating hardware resources.

Further, according to the present invention, when setting data in a semiconductor integrated circuit inspection apparatus having a per-pin configuration having hardware resources for each of a plurality of pins, group identification information and individual identification information are set for each pin. And set
It is easy to set the same data for a plurality of pins as a group at the same time or to set individual data for each pin. In other words, by setting the same group identification information for the pins for which the same data is to be set and setting the data at the same time, the data can be set in the shortest time. Even in the case of a device, it is possible to avoid an increase in the time required for setting as compared with a shared resource type tester. Since different data can be set for a plurality of groups or a plurality of pins at the same time, the time required for data setting can be minimized. Specifically, assuming that the number of group units in which different data can be set at the same time is n, the tester hardware access time, which is the time required for data setting, is 1
/ N. This n depends on the data bus width used for tester hardware access. The data bus width of a CPU having a general configuration at present is 64 bits. Experience shows that with this bus width, two or more types of different data can be set at the same time. For example, two types of different data are set at the same time, and the time required for data setting is reduced by 1 /
It can be 2. It is clear that the effect of the present invention will be further increased if the data bus width of the CPU becomes larger in the future.

Further, according to the present invention, since the group identification information and the individual identification information can be respectively set by the controller in the register provided for each pin, efficient data setting can be performed while changing the grouping. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic electrical configuration of a basic embodiment of the present invention and a diagram showing a bit configuration of an address bus.

FIG. 2 is a flowchart showing a data setting procedure of the basic mode of FIG. 1;

FIG. 3 is a block diagram showing a schematic electrical configuration of an embodiment of the present invention.

FIG. 4 is a diagram showing a bit configuration of an address bus and a data bus of the embodiment of FIG. 3;

FIG. 5 is a block diagram showing a schematic electrical configuration of still another embodiment of the present invention.

FIG. 6 is a diagram showing a bit configuration of an address bus and a data bus of the embodiment of FIG. 5;

FIG. 7 is a block diagram showing a schematic electrical configuration of a conventional tester having a per-pin configuration.

FIG. 8 is a simplified block diagram showing a schematic electrical configuration of the prior art.

[Explanation of symbols]

20, 40, 50 Testers 21, 41, 51 Control circuit 22 Controller 23 Setting circuit 24 Hardware resources 25 Address bus 26 Data bus 27 Address decoder 31 Group ID storage register 32 Individual pin ID storage registers 33, 43, 53 Broadcast enable signal Detection circuit 34, 44a, 44b, 54a, 54b Group ID
Code comparators 35, 45, 55a, 55b Individual pin ID code comparators 36, 46, 56 Access permission circuits 47, 57 Switches 48, 58 Group access enable signal detection circuit 59 Individual pin access enable detection circuit

Claims (8)

(57) [Claims] 1. A semiconductor integrated circuit comprising a plurality of pins that can be individually connected to a connection portion thereof, each pin having the same hardware resource, and the hardware resource of each pin connected to a common controller. In a possible semiconductor integrated circuit testing device, the controller uses three predetermined portions of the address bus, the broadcast enable information in the first portion, the group identification validity information in the second portion, and the individual portion in the third portion. The identification information can be transmitted, and when the group identification validity information is made valid, the group identification information is transmitted using a predetermined information portion of the data bus, and the data of the data bus excluding the information portion is excluded. Group setting means for transmitting data using a portion and providing group identification information provided for each pin An individual setting means provided for each pin and capable of setting individual identification information for individually identifying each pin; and receiving a second portion of the address bus and an information portion of the data bus provided for each pin. Group comparison means for comparing whether the group identification validity information is valid, and whether the received group identification information matches the group identification information set in the group setting means, and provided for each pin. An individual comparing means for receiving the third part of the address bus and comparing whether the received individual identification information matches the individual identification information set in the individual setting means, provided for each pin. The broadcast enable information received from the first part of the address bus is valid,
Control means for enabling access to the hardware resources by data transmitted from the controller via the data bus when the group comparison means or the individual comparison means determines that they match. Semiconductor integrated circuit inspection equipment. 2. A semiconductor integrated circuit comprising: a plurality of pins that can be individually connected to a connection portion thereof; each pin having equal hardware resources; and a hardware resource of each pin connected to a common controller. In a possible semiconductor integrated circuit testing device, the controller uses three predetermined portions of the address bus, the broadcast enable information in the first portion, the group identification validity information in the second portion, and the individual portion in the third portion. The identification valid information can be respectively transmitted, and when the group identification valid information or the individual identification valid information is made valid, the group identification information or the individual identification information is transmitted using a predetermined information portion of the data bus, respectively, Data is transmitted using the data portion of the data bus other than the information portion, and is set for each pin. Group setting means capable of setting group identification information; individual setting means provided for each pin and capable of setting individual identification information for individually identifying each pin; and address setting provided for each pin. Receiving the second portion of the bus and the information portion of the data bus to determine whether the group identification validity information is valid, and whether the received group identification information matches the group identification information set in the group setting means. Group comparing means for comparing, a third part of the address bus and an information part of the data bus provided for each pin, the individual identification validity information being valid, and the received individual identification information and the individual setting means An individual comparing means for comparing whether or not the set individual identification information matches; and a broadcast provided for each pin and received from the first part of the address bus. Or enable information is valid,
Control means for enabling access to the hardware resources by data transmitted from the controller via the data bus when the group comparison means or the individual comparison means determines that they match. Semiconductor integrated circuit inspection equipment. 3. The data bus, when the group identification valid information or the individual identification valid information is valid,
A control unit for each pin is divided so that a plurality of sets each including the information portion and the data portion are formed, and the group identification information transmitted from the controller via the information portion of each set of the data bus or the individual When the identification information matches the group identification information or the individual identification information set in the group setting means or the individual setting means, access to the hardware resource by data transmitted from the controller through the same set of data portions. 3. The semiconductor integrated circuit inspection device according to claim 2, wherein: 4. The apparatus according to claim 1, wherein said group setting means and said individual setting means have registers each of which can set group identification information and individual identification information by said controller. Semiconductor integrated circuit inspection equipment. 5. A semiconductor integrated circuit comprising a plurality of pins that can be individually connected to connection portions, each pin having the same hardware resource, and setting data from the controller to the hardware resource for each pin. In the data setting method of the semiconductor integrated circuit inspection device for performing the above, the controller uses three predetermined portions of the address bus, the first portion has broadcast enable information, the second portion has group identification valid information, and In the third part, the individual identification information can be transmitted respectively. When the group identification validity information is made valid, the group identification information is transmitted using a predetermined information part of the data bus, and the group identification information is transmitted in the data bus. Data is transmitted using the data portion excluding the information portion, and group identification information and individual identification for each pin Information is set, and when the broadcast enable information transmitted through the first part of the address bus is valid, all pins are used to transmit data from the controller via the data bus to the hardware resources. Data setting is enabled, and when the group identification validity information transmitted via the second part of the address bus is valid, the group identification information transmitted via the information part of the data bus is set to the group identification information. The matching pins enable the data to be set in the hardware resources by the data transmitted from the controller via the data portion of the data bus, and the individual identification information transmitted via the third portion of the address bus is set. Pin that matches the individual identification information Data setting method of a semiconductor integrated circuit testing device, characterized in that to enable data setting hardware resources f by data sent Te. 6. A plurality of pins that can be individually connected to a connection portion of a semiconductor integrated circuit, each pin has an equivalent hardware resource, and data is set from a controller to a hardware resource for each pin. In the data setting method of the semiconductor integrated circuit inspection device for performing the above, the controller uses three predetermined portions of the address bus, the first portion has broadcast enable information, the second portion has group identification valid information, and In the third part, the individual identification validity information can be transmitted, and when the group identification validity information or the individual identification validity information is made valid, the group identification information or the individual identification information is determined by using a predetermined information portion of the data bus. Are transmitted, and the data portion of the data bus except for the information portion is used. And the group identification information and the individual identification information are set for each pin, and when the broadcast enable information transmitted via the first part of the address bus is valid, the data is transmitted from the controller to each of all the pins. Data can be set to hardware resources by data transmitted via the bus, and when group identification validity information transmitted via the second part of the address bus is valid, transmission via the information part of the data bus is enabled. The pin corresponding to the group identification information to be set is set to the pin corresponding to the group identification information, and the data transmitted to the hardware resource by the data transmitted from the controller via the data portion of the data bus can be set. When the individual identification validity information transmitted via the three parts is valid, At the pin corresponding to the individual identification information set with the individual identification information transmitted through the information portion of the tabus, the data setting to the hardware resource by the data transmitted from the controller via the data portion of the data bus is performed. A data setting method for a semiconductor integrated circuit inspection device, wherein the method is enabled. 7. When the group identification valid information or the individual identification valid information is valid, the data bus is
Grouping is performed so that a plurality of sets each including the information portion and the data portion are formed, and group identification information or individual identification information transmitted from the controller via the information portion of each set of the data bus is set. 7. The method according to claim 6, wherein when the group identification information matches the group identification information or the individual identification information, the data set to the hardware resource by the data transmitted from the controller through the same set of data portions is enabled. A data setting method for a semiconductor integrated circuit inspection device. 8. A register for each of the pins, wherein a register in which group identification information and individual identification information can be respectively set by the controller is provided.
8. The data setting method of the semiconductor integrated circuit inspection device according to any one of 7.