JPS62112076A - Pattern generator - Google Patents

Abstract

PURPOSE:To generate pattern data by a data memory of small-bit-number constitution by composing data stored in plural addresses at need and thus generating data consisting of a large number of bits. CONSTITUTION:When an IC 34 to be inspected is a 128-pin IC memory, 128-bit pattern data in each test step is divided into two 64-bit parts and written in two addresses succeeding to, for example, the starting address of the memory 12. Address information which specifies the starting address of the memory 12 is set in address register 16 through an address updating circuit 18 by a controller 20 prior to the start of pattern generating operation. Load timing signals L1 and L2 are generated in even-numbered and odd-numbered addresses respectively and 128-bit pattern data consisting of stored data in the two successive addresses are composed on two registers 26 and 28 are inputted to a waveform formatter 30.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pattern generator that generates pattern data of multiple viats, and more particularly, to a pattern generator that generates pattern data of a plurality of viats, and more specifically, a pattern signal that is applied to a bin of an IIC to be tested in an IC41E system. The present invention relates to a pattern generation device that can be used for purposes such as generating pattern data corresponding to.

[Prior Art] An IC testing system is equipped with a pattern generator for generating pattern signals corresponding to pins of an IC to be tested.

Such a pattern generation device stores a series of pattern data corresponding to a pattern signal to be generated in a memory IJ (RAM).
The pattern data is sequentially read out from the memory to generate a pattern signal.

In fact, in that memory, the pattern data is not related to the number of bits actually required to test the IC (i.e., it is treated as data with the number of bits necessary to test an IC with the maximum number of pins). There is.

[Problems to be Solved] To be more specific, for example, conventional pattern generators used in IC testing systems that can test IC memories with up to 128 pins are Even if the IC memory has 64 pins and only 64 bits of pattern data are required for one test step, it is treated as 128 bits of data in the memory and occupies that much memory space.

Therefore, data corresponding to the number of bits corresponding to the difference between the actual number of focus points and the maximum number of bits is wasted, and memory is wasted by that amount, resulting in poor memory usage efficiency. Ta.

[L1 aspect of the invention It is an object of the invention to improve the utilization efficiency of memory for storing pattern data by reducing such jlls.
It is an object of the present invention to provide a pattern generating device that has the following characteristics.

[Means for Solving the Problems] To achieve this objective, according to the present invention, a pattern generation device generates a memory for storing pattern data and address information for accessing this memory. It includes an address generation circuit and a data output circuit that outputs read data from the memory to the outside,
It has a first mode and a second mode, and the memory is sequentially accessed while specifying addresses using address information generated by the address generation circuit, and in the first mode, the data output circuit reads from multiple addresses in the memory. The output data is assembled into two pattern data and output, and in the second mode, the data output circuit outputs the data read from each address of the memory as one pattern data.

[Operation] Because of this configuration, if there are 7 thorns that generate pattern data with more bits fi than the word length of the memory, the pattern data is divided into consecutive addresses 2 to 1. By storing the data in the first mode and operating in the first mode, pattern data can be generated.

On the other hand, if there are seven patterns that generate pattern data with a number of bits less than the word length of the memory, by storing one pattern data in one address of the memory and operating in the second mode, that pattern can be generated. Data can be generated.

Therefore, when generating pattern data with a number of bits equal to the word length of the memory, and when generating pattern data with a number of bits that is an integral multiple of the word length of the memory,
There is no wastage of memory, and memory can be used with maximum efficiency.

When generating pattern data shorter than the word length of the memory, j% useless bits occur for each address. Similarly, when generating pattern data with a number of bits that is not divisible by the word length of the memory, for each address corresponding to one pattern data, some jH! This results in poor focus. However, if you choose the memory word length to minimize such wasted bits,
Even in cases where such wasted bits occur,
Memory usage efficiency can be greatly improved compared to conventional methods.

In fact, for example, the number of pins of IC memory is 64 pins, 128 pins,
Like pins, the word length is divisible by a certain number or increases or decreases in a close relationship, so it is relatively easy to select a word length that meets such conditions.

As described above, according to the present invention, the usage efficiency of the memory for storing pattern data can be significantly improved compared to the conventional method, so that pattern data with a larger number of steps than the conventional method can be generated using a fixed capacity memory. or reduce memory capacity.

[Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram of an embodiment of a pattern generator according to the present invention. Here, the pattern generator 10 will be described as being used in an IC inspection system capable of inspecting a 128-pin IC memory or the like.

In FIG. 1, reference numeral 12 denotes a memory for storing pattern data, which here has a word length of 64 bits.

14 is an address generation circuit that generates address information for accessing the memory 12. The address generation circuit 14 includes an address register 16 and an address update circuit 18, and operates together with a timing generation circuit 22 and a controller 20.

Prior to the start of the pattern data generation operation, initial address information is set in the address register 16 by the controller 20 via the address update circuit 18. After that, the timing generation circuit 22 sends the update timing signal UP to 9.
．． Each time the address update circuit 18 updates the address information held in the address register 16, the updated address t+7 information is set in the address register 16. Address information is also input manually to the controller 20.

This pattern generator 10 has a first mode and a second mode as operating modes, and one of them can be specified.

The operation mode is determined by the mode signal MO from the controller 20.
D is transmitted to address update circuit 18 and timing generation circuit 22.

The address update circuit 18 updates (increases) the address information by 1 in the first mode, but updates (adds) the address information by 2 in the second mode.

Incidentally, pattern data is loaded into this memory 12 from a host device (not shown), but the writing system is omitted in the figure.

24 is a data output circuit for outputting read data from the memory 12 to the outside, and cooperates with the timing generation circuit 22. Here, the data output circuit 24 is composed of two 64-bit 7-stars 28.28. Output data (64 bits) from memory 12 is input to both registers 26 and 28 simultaneously. Load timing signals L1 and L2 for each register 26 and 28 are supplied from the timing generation circuit 22. The generation of this load timing signal differs depending on the operation mode, which will be described later.

In this embodiment, the pattern data generated by the pattern generator 10 is sent to the waveform formatter 3.
It is input to 0. The waveform formatter 30 outputs a pin-corresponding pattern signal corresponding to the pattern data, and inputs it to the driver circuit 32 . Driver circuit 3
2 consists of a circuit corresponding to the pin of the IC to be tested 34, and drives the corresponding pin of the IC to be tested in accordance with the input pattern signal.

Next, the pattern data generation operation by this pattern generation device 10 will be explained.

For example, assume that the IC 34 to be tested is a 128-pin IC memory and generates 128-bit pattern data. In this case, the 128 and gutter pattern data of each test I step are divided into two parts of 64 bits each, and stored in the memory I.
For example, the data is distributed and written to two consecutive addresses starting from the first address. Further, the operation mode is set to the first mode.

Prior to the start of the pattern generation operation, address information specifying the start address of the memory 12 is set in the address register 16 from the controller 20 via the address update circuit 18 (in the case of the start address, the address information is set in the address register 16).
), then the controller 20 supplies the timing generation circuit 22 with a start signal ST.

By this start signal ST, the timing generation circuit 22
starts generating timing signals. The update timing signal UP is sent out at a constant cycle, but since this is the first mode, the address history new circuit 18 sequentially updates the address information by 1 each time the update timing signal UP is generated. 12 consecutive addresses are accessed sequentially and their stored data (64 bits each)
is read from memory 12.

In the first mode, the load timing signal L1 immediately after the data stored in the even address of the memory 12 is read out.
is generated, and the read data is set in one register 26. Furthermore, each time the data stored at an odd address in the memo IJ12 is read, a load timing signal L2 is generated, and the read data is set in the other register 28. In this way, 128-bit pattern data consisting of storage data of two consecutive addresses is assembled on the two registers 26 and 28 and input to the waveform formatter 30.

Note that the load timing signal L2 is also added to the waveform formatter 30 as a pattern data acquisition signal.

In this way, 128-bit pattern data is sequentially generated and converted into a corresponding pattern signal-3 by the waveform formatter 30, and each bin of the IC to be tested 34 is driven accordingly.

Next, a case where the IC 34 to be tested is, for example, a 64-pin IC memory and generates 64-bit pattern data will be described. In this case, the 64-bit pattern data of each test step is written, for example, to even-numbered addresses sequentially from the first address of the memory 12, and after reaching the final even-numbered address, it is sequentially written to odd-numbered addresses starting from address 1. It will be done. Further, the operation mode is set to the second mode.

Prior to the start of the pattern generation operation, address information specifying the start address of the memory 12 is set in the address register 16 by the controller 20 via the address update circuit 18, and then the controller 20 sends a start signal ST to the timing generation circuit 22. is supplied.

By this start signal ST, the timing generation circuit 22
starts generating timing signals. The update timing signal UP is sent at a constant cycle, but since the second mode is here, the address update circuit 18 sequentially updates the address information by 2 each time the update timing signal UP is generated, and the address information is updated by 2 in the memory 12. The even address is accessed mr* times, and its stored data (64 bits each)
is read from memory 12.

The controller 20 monitors the address information, and when the address information is updated to the final even address, it sets the address information specifying address 1 in the address register 16 again. After this, the address information is 2 as well.
Since the data is updated one by one, odd addresses in the memory 12 are sequentially accessed.

In the second mode, one load timing signal L is activated each time storage data at each address of the memory 12 is read.
2 is generated, and the read data is set in the register 26.

In this way, 64-bit pattern data is sequentially generated and input to the waveform formatter 30.

As described above, according to this pattern generating device 10, when generating pattern data of the same length or twice the word length (64 bits) of the memory 12, the memory 12 has ! ! 1 (Since no useless bits are generated, the utilization efficiency of the memory 12 is the highest.

Pattern data having less than 64 bits can also be generated in the second mode. Also, from 65 bits to 127
Pattern data up to bits can be similarly generated in the first mode.

When generating 64-bit ungrooved pattern data, there are wasted bits at each address in the memory, but compared to when using a 128-bit word length memory, the wasted bits are small and the memory usage efficiency is not much worse. do not.

Furthermore, when generating pattern data from 65 bits to 127 bits, a useless bit will occur at one of two consecutive addresses. However, since the number of pins of IC memory etc. is not decided arbitrarily, for example, if the word length of memory 12 is set to 64 bits,
One like that! ! (The number of useless bits can be kept relatively small, and in practice sufficient utilization efficiency can be maintained.

In this embodiment, in the first mode, two addresses worth of storage data are combined into one pattern data 17. However, for example, it is also possible to configure the register to hold the read data of the memory 12 on three sides and to assemble one pattern data from the stored data of three or more addresses. be.

Furthermore, in the first mode, it is also possible to variably set the number of read data for assembling one pattern data. In this way, it is possible to further reduce the word length of the memory 12 and generate more wasteful bits, thereby further improving memory usage efficiency.

Furthermore, it is also possible to make the even and odd addresses of the memory 12 substantially simultaneously accessible by interleaving, thereby speeding up the generation operation of pattern data of 65 bits or more.

Furthermore, the present invention can be similarly applied to patterns other than the pattern generator of the ICM anzu system.

[Effects of the Invention] As is clear from the explanation in 1- below, the pattern generation device according to the present invention includes a memory for storing pattern data and an address generation device for generating address information for accessing this memory. The circuit includes a data output circuit that outputs read data from the memory to the outside, and has a first mode and a second mode. In the first mode, the data output circuit assembles the data read from multiple addresses in the memory into one pattern data and outputs it, and in the second mode, the data output circuit is configured to output data read from each address as one pattern data.

With this configuration, when generating pattern data for focus equal to the word length of the memory, and when generating pattern data with a number of bits that is an integral multiple of the word length of the memory, all the memory is wasted. ! 1 (and memory can be used with maximum efficiency.

When generating pattern data shorter than the word length of the memory, wasteful bits occur for each address. Similarly, when generating pattern data due to a focus that is not divisible by the word length of the memory, some wasted bits are generated for each address among a plurality of addresses corresponding to one pattern data. However, if the word length of the memory is chosen to minimize such wasted bits, even in cases where such wasted bits occur, memory usage efficiency can be significantly improved compared to the conventional method. .

In fact, for example, the number of pins of IC memory is 64 pins, 128 pins,
Like pins, the word length is divisible by a certain number or increases or decreases in a close relationship, so it is relatively easy to select a word length that meets such conditions.

As described above, according to the present invention, the utilization efficiency of the memory for storing pattern data can be greatly improved compared to the conventional method.
Therefore, it becomes possible to generate pattern data with a larger number of steps than in the past using a memory of a certain capacity, or it is possible to achieve the effect of reducing the memory capacity 11k.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of a pattern generator according to the present invention. lO...Pattern generator, 12...Memory for storing pattern data, 14...Address generation circuit, 20.
...Controller, 22...Timing generation circuit, 2
4...Data output circuit.

Claims (2)

[Claims] (1) A memory for storing pattern data, an address generation circuit for generating address information for accessing this memory, and a data output circuit for outputting read data from the memory to the outside; 1 mode and a second mode, in which the memory is sequentially accessed while specifying addresses using the address information generated by the address generation circuit, and in the first mode, the data output circuit accesses a plurality of memories in the memory. The data read from the addresses are assembled into one pattern data and outputted, and in the second mode, the data read from each address of the memory is outputted as one pattern data by the data output circuit. Characteristic pattern generator. (2) In the first mode, the address generation circuit continuously updates the address information while accessing the memory, and in the second mode, the address generation circuit updates the address information two by two while accessing the memory. 2. The pattern generating device according to claim 1, wherein the pattern generating device is configured to access the pattern generating device.