JP2710456B2 - Scan path data collection method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan path data collection method, and more particularly to a scan path data collection method for reading an output of a scan path circuit in a logic integrated circuit.

[Conventional technology]

Conventionally, a scan path data collection method for reading data of a scan path circuit incorporated for testing in a logic integrated circuit by a diagnostic control device uses a diagnostic control clock output from the diagnostic control device to store a scan path. The information in the element is shifted one bit at a time, the shift output is taken into the diagnostic control device, and the data is grouped every eight bits.
It was converted to hexadecimal digits and displayed on a terminal device or the like.

[Problems to be solved by the invention]

In the conventional scan path data collection method described above, the data stored in each storage element constituting the scan path includes not only 8-bit data but also data of an arbitrary number of bits and an error detection code. Despite the above, the shift output is compiled in 8-bit units without editing
Since the data is displayed in hexadecimal, it is difficult to analyze the output data, and it takes a long time to judge the test result.

For example, when the 7-bit data “6A” in hexadecimal notation and the error detection code “1” are output, the 7-bit data and the error detection code are output left-justified without being distinguished. Therefore, they are grouped into 8 bits and displayed as a hexadecimal number “D5”. For this reason, manual conversion is required to restore the original data, which results in a time-consuming data analysis.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a scan path data collection method that separates and displays data and error detection codes having different numbers of constituent bits and facilitates data analysis.

[Means for solving the problem]

A scan path data collection method according to the present invention includes a diagnostic control device that generates a diagnostic control clock and a diagnostic control signal that instructs a diagnostic operation of a logic integrated circuit, and a shift mode control circuit that generates a shift mode signal based on the diagnostic control signal. A shift register is formed in the logic integrated circuit to be diagnosed by the shift mode signal, and edit information of scan path data corresponding to a connection state of the scan path circuit for sequentially outputting the held information as scan path data is stored. And a clock control circuit that outputs the diagnostic control clock to the scan path circuit to be diagnosed as an operation clock when the edit control signal is “1” during shift mode operation and stops the output when the edit control signal is “0” during shift mode operation Counting the diagnostic control clock to generate an address signal for the editing information storage device, Control information generating means for reading the collected information and supplying the edit control signal; and "0" when the edit control signal is "0" operated by the diagnostic control clock.
And a scan register for inputting the scan path data when "1" is input.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention.

The circuit shown in FIG. 1 includes a diagnostic control device 1 for outputting a diagnostic control clock 15 and a diagnostic control device 11, and a shift mode signal.
A shift mode control circuit 2 for generating 12; an address counter 3 for starting counting of a diagnostic control clock 15 by the shift mode signal 12; and a 1-bit edit information storage device 4 for holding scan path data edit information. The clock control circuit 5 which outputs the diagnostic control clock 15 as the operation clock 16 when the edit control signal 14 is "1" during the shift mode operation and stops the output when the edit control signal 14 is "0", and the scan path circuit to be diagnosed is Operates with the constituent registers 6 to 9 and the diagnostic control clock 15, and is "0" when the edit control signal 14 is "0".
And a scan register 10 for inputting scan path data from the register 9 when it is "1".

FIG. 2 is a time chart showing the operation of this embodiment. Hereinafter, the operation of FIG. 1 will be described with reference to FIG.

The diagnostic control device 1 sends a diagnostic control signal 11 to the shift mode control circuit 2 when the scan path data is collected, and sets the shift mode signal 12 to logic "1". The address counter 3 resets the address signal 13 to “0” when the shift mode signal 12 changes from logic “0” to “1”, and thereafter, resets the address signal 13 by 1 every one cycle of the diagnosis control clock 15. increase.

The editing information storage device 4 is a 1-bit memory,
Edit information for converting data of an arbitrary number of bits of the scan path circuit into an 8-bit format and outputting the converted data is stored in bit units. Now, during normal operation, registers 7-9
Assuming that 3-bit data is stored in the register 6 and parity bits are stored in the register 6, each data is output as 8-bit right-justified data in order to display the 3-bit data portion and the parity bits separately. Edit information to be performed is stored in the 1-bit edit information storage device 4. That is, as edit information for outputting the first 3-bit data, "0" is recorded in 5 bits from address 0 to address 4 and "1" is recorded in 3 bits from address 5 to address 7. ing. Similarly, in order to output a parity bit, "0" is assigned to 7 bits from addresses 8 to 14,
At address 15, "1" is recorded.

Each of the registers 6 to 9 operates by a common operation clock 16 and normally holds information from the data inputs 21 to 24. However, when the shift mode signal 12 becomes logic "1", the registers 6 to 9 A shift operation is performed in the direction.

When the shift mode signal 12 is logic "0", the clock control circuit 5 controls the system clock for normal logic operation.
26 is supplied to each of the registers 6-9. Shift mode signal 12
Becomes "1", the diagnostic control clock 15 is output as the operation clock 16 when the edit control signal 14 is logic "1", and the registers 6 to 9 perform the shift operation, but when the logic is "0". , The output is set to logic "0" and the shift operation of the registers 6 to 9 is stopped.

Since the output of the edit information storage device 4 is directly input to the clock control circuit 5 as the edit control signal 14, the diagnosis is started, and the edit control signal is output during the five clocks of the address signal 13 from "0" to "4". 14 is "0" and no shift operation is performed. When the address signal 13 becomes "5", the edit control signal 14
Becomes "1", the operation clock 16 is output, and the shift operation is performed.

The scan register 10 is operated by the diagnostic control clock 15, and inputs “0” when the edit control signal 14 is “0”. When the edit control signal 14 becomes “1”, the scan register 10 registers the last register 9 of the scan path circuit. Input output 20. Thus, the scan register output 25 edited by the edit control signal 14 is output.
Are transmitted to the diagnostic control apparatus 1 bit by bit by the diagnostic control clock 15, converted into 8-bit right-justified parallel data, and displayed as hexadecimal digits.

When the diagnosis is started, five bits of "0" are successively taken into the scan register 10 by editing. During this time, the outputs 17 to 20 of the registers 6 to 9 hold the previous state. When the address is further added and "1" is output from the editing information storage device 4, three operation clocks are output, and the registers 6 to 9 perform a shift operation, and a register (not shown) connected to the preceding stage is connected. From "X-
0 to X-2. The scan register 10 takes in the output 20 of the register 9 as scan data, and sends “data 0” to “data 2” held in the registers 7 to 9 to the diagnostic control device 1 as a scan register output 25.

FIG. 3 is a block diagram of a second embodiment of the present invention, and FIG. 4 is a time chart showing the operation thereof.

The main difference between FIG. 3 and FIG. 1 is that the editing information storage device 4a
Is a multi-bit configuration, the editing information is held as numerical information for each address, and the editing information storage device 4a
Means for reading out edit information from the CPU and generating an edit control signal 14 of the clock control circuit 5 includes a frequency dividing circuit 3a for dividing the diagnostic control clock 15 by 8, an address counter 3 for counting its output, and an edit information storage device. This is a counter 3b that performs a subtraction process from the output numerical value of 4a and outputs “1” when it becomes “0”.

The shift mode control circuit 2a outputs a reset signal 12a for a fixed time in synchronization with the shift mode signal 12. Divider 3
“a” divides the diagnostic control clock 15 by 8, and outputs a divided clock 27. The address counter 3 is reset by the reset signal 12a, and thereafter increases the read address by one by the divided clock 27.

The edit information storage device 4a stores "5" and "7" as edit information for outputting 3-bit data and 1-bit parity as 8-bit right justified data, respectively. When the address counter 3 is reset by the reset signal 12a, "5" is set in the counter 3b from the editing information storage device 4a. Counter 3b is diagnostic control clock 15
When the count value becomes "0", the output edit control signal 14 is set to "1" and the operation is stopped. Divider circuit
When the divided clock 27 is supplied from 3a, the edit control signal 14
Is reset to “0”, and the edit information storage device 4a outputs “7”
Is read into the counter 3c and the subtraction is resumed. When the edit control signal 14 becomes "1", the operation after the operation clock 16 is supplied to the registers 6 to 9 is exactly the same as in the case of the first embodiment described with reference to FIGS.

In the above description, the editing information of the 3-bit signal is set to "5", the editing information of the 1-bit parity is set to "7", and the counter 3c performs the subtraction operation. Is "3", parity is "1",
For example, a method may be used in which the counter performs an adding operation and the output becomes “1” when the count value becomes “8”.

〔The invention's effect〕

As described in detail above, the present invention provides an editing information storage device that holds editing information, a clock control circuit that controls the stop of transmission of a clock signal by an editing control signal, and reads out editing information to generate an editing control signal. It has control information generating means and displays data with different numbers of bits and error detection codes separately, so that scan path data can be easily analyzed and the effect of improving the efficiency of evaluation and maintenance of logic integrated circuits can be improved. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a time chart showing the operation of the first embodiment, and FIG. 3 is the configuration of the second embodiment of the present invention. FIG. 4 is a time chart showing the operation of the second embodiment. 1 ... diagnosis control device, 2,2a ... shift mode control circuit,
3 ... Address counter, 3a ... Division circuit, 3b ... Counter, 4 ... Edit information storage device, 5 ... Clock control circuit, 6-9 ... Register, 10 ... Scan register.

Claims (3)

(57) [Claims] A diagnostic control device for generating a diagnostic control clock and a diagnostic control signal for instructing a diagnostic operation of a logic integrated circuit; a shift mode control circuit for generating a shift mode signal based on the diagnostic control signal; An edit information storage device that holds edit information of scan path data corresponding to a connection state of a scan path circuit that configures a shift register in a logic integrated circuit to be diagnosed by a signal and sequentially outputs information held as scan path data A clock control circuit that outputs the diagnostic control clock to the scan path circuit to be diagnosed as an operation clock when the edit control signal is “1” during a shift mode operation and stops the output when the edit control signal is “0”; A clock is counted to generate an address signal of the editing information storage device, the editing information is read, and the editing is performed. A control information generating means for supplying a control signal; a scan register which operates according to the diagnostic control clock, inputs "0" when the edit control signal is "0", and inputs the scan path data when the edit control signal is "1". A scan path data collection method, comprising: 2. The editing information storage device holds 1-bit editing information, and the control information generating means comprises an address counter for counting the diagnostic control clock. 2. The scan path data collection method according to claim 1, wherein the data is supplied as a control signal. 3. The edit information storage device holds the edit information as bit number information, and the control information generating means includes a frequency dividing circuit for dividing the diagnostic control clock by 8, an address counter for counting the output thereof. And a counter configured to add / subtract the number of bits output from the editing information storage device for each diagnostic clock and set the editing control signal to "1" when a predetermined value is reached. Scan path data collection method.