JPH04151578A - Scan-path-data sampling method - Google Patents

Abstract

PURPOSE:To separate and display the data having the different constituent numbers and detected error symbols and to facilitate the analysis of the data by maintaining editing data, reading the data, forming editing control signals, and controlling the sending and stopping of clock signals. CONSTITUTION:For example, data in three-bit format and parity bits stored in a scan-path circuit are classified and displayed. For this purpose, an editing- data memory device 4 maintains the editing data which are outputted as the right-justified 8-bit data. In a clock control circuit 5 wherein an editing control signal 14 of the device 4 is inputted, registers 6 - 9 are shifted and operated with a diagnosis control clock 15 as an operating clock when a shift-mode signal 12 becomes 1 and the signal 14 is a logic 1. When the logic is 0, the operation is stopped. During the period when an address signal 13 is 0 - 4, the signal 14 becomes 1 when the signal 13 becomes 5, and the shifting operation is performed. An output 20 of a the register 9 is inputted into a scanning register 10. In this way, an output 25 of the scanning register is sent into a diagnosis controlling device 1 by every 1 bit. The data are converted and displayed as the right-justified 8-bit data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a scan path data acquisition method, and more particularly to a scan path data acquisition method for reading out the output of a scan path circuit in a logic integrated circuit.

[Conventional technology]

Conventionally, the scan path data collection method used when a diagnostic control device reads out data from a scan path circuit built into a logic integrated circuit for testing is a memory that forms a scan path using a diagnostic control clock output from the diagnostic control device. The information in the element is shifted 1 bit at a time, the shifted output is taken into the diagnostic control device, and each 8 bits are combined into 1 bit.
It was converted into hexadecimal numbers and displayed on a terminal device, etc.

[Problem to be solved by the invention]

In the conventional scan path data acquisition method described above, the data stored in each storage element constituting the scan path includes not only 8-bit data but also data of an arbitrary number of bits, error detection codes, etc. Despite the
Since it is displayed in hexadecimal notation, it is difficult to analyze the output data and it takes time to judge the test results.

For example, when 7-bit data that is "6A" in hexadecimal notation and an error detection code "1" are output, the 7-bit data and error detection code are not distinguished and are output left-justified. Therefore, it is summarized into 8 bits and becomes a hexadecimal number “D
5" is displayed. Therefore, manual conversion is required to restore the original data, resulting in a time-consuming data analysis.

SUMMARY OF THE INVENTION An object of the present invention is to provide a scan path data collection method that separates and displays data and error detection codes having different numbers of constituent bits and facilitates data analysis.

[Means to solve the problem]

The scan path data acquisition method of the present invention includes a diagnostic control device that generates a diagnostic control clock and a diagnostic control signal that instructs a diagnostic operation of a logic integrated circuit, and a shift mode control circuit that generates a shift mode signal based on the diagnostic control signal. and,
Editing that configures a shift register in the logic integrated circuit to be diagnosed using the shift mode signal and sequentially outputs the held information as scan path data.Editing that holds editing information of the scan path data corresponding to the connection state of the scan path circuit. an information storage device; a clock control circuit that outputs the diagnostic control clock as an operating clock to the scan path circuit to be diagnosed when the edit control signal is "1" during shift mode operation, and stops outputting when the edit control signal is "0"; control information generating means for counting the diagnostic control clock to generate an address signal for the editing information storage device and reading the editing information to generate the editing control signal; When “0”
and a scan register which inputs the scan path data when the scan path data is input when the scan path data is input as "0" and "1".

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

The circuit shown in FIG. 1 includes a diagnostic control device 1 that outputs a diagnostic control clock 15 and a diagnostic control signal 11, a shift mode control circuit 2 that generates a shift mode signal 12, and a shift mode control circuit 2 that outputs a diagnostic control clock 15 using the shift mode signal 12. The address counter 3 that starts counting, the 1-bit edit information storage device 4 that holds the edit information of the scan path data, and the diagnostic control clock 15 when the edit control signal 14 is "1" during shift mode operation. A clock control circuit 5 that outputs a clock 16 and stops output when it is '0'', registers 6 to 9 that constitute the scan path circuit to be diagnosed, and an editing control signal circuit 4 that operates with the diagnostic control clock 15. It is composed of a scan register 10 which inputs "0" when it is "O" and inputs scan path data from the register 9 when it is '1'.

FIG. 2 is a time chart showing the operation of this embodiment.

The operation shown in FIG. 1 will be explained below with reference to FIG.

The diagnostic control device 1 sends the diagnostic control signal 11 to the shift mode control circuit 2 when collecting scan path data, and sets the shift mode signal 12 to logic "1". The address counter 3 resets the address signal 13 to "0" when the shift mode signal 12 changes from logic "0" to "1", and then resets the address signal 13 by 1 every cycle of the diagnostic control clock 15. increase.

The editing information storage device 4 is a 1-bit memory, and stores editing information for converting data of an arbitrary number of bits of the scan path circuit into an 8-bit format and outputting the data in bit units. Now, suppose that 3-bit data is stored in registers 7 to 9 during normal operation, and a parity pit is stored in register 6. In order to display the 3-bit data part and the parity bit separately, Editing information for outputting as 8-bit right-justified data is held in the editing information storage device 4 having a 1-bit configuration. That is, as editing information for outputting the first 3-bit data, "0" is recorded in 5 bits from address O to address 4, and "1" is recorded in 3 bits from address 5 to address 7. ing. Similarly, in order to output the parity pit, the 7 bits from address 8 to address 14 are set to “0”.
”, but “1” is recorded at address 15.

Registers 6 to 9 are each operated by a common operating clock 16 and normally hold information from data inputs 21 to 24, but when shift mode signal 12 becomes logic "1", registers 6 to 9 are Perform a shift operation in the direction.゛The clock control circuit 5 receives the shift mode signal 1
2 is logic "0", a system clock 26 for normal logic operation is supplied to each register 6-9. When the shift mode signal 12 becomes "1", the diagnostic control clock 15 is output as the operation clock 16 when the edit control signal 14 is logic "1", and the registers 6 to 9 are made to perform a shift operation. In the case of "0", the output is set to logic "0" and the shift operation of registers 6 to 9 is stopped.

Since the output of the editing information storage device 4 is directly input to the clock control circuit 5 as the editing control signal 14, the editing control signal is not input during the 5 clocks from when the address signal 13 is "0" to "4" after diagnosis is started. 14 is "0", no shift operation is performed. When the address signal 13 becomes "5", the edit control signal 14 becomes "1", the operation clock 16 is output, and a shift operation is performed.

The scan register 10 is operated by the diagnostic control clock 15, and when the edit control signal 14 is "0", "O" is input, and when the edit control signal 14 is "1", the last register 9 of the scan path circuit is inputted. Enter output 20. In this way, the scan register output 25 edited by the edit control signal 14 is set to 1 by the diagnostic control clock 15.
The data is sent bit by bit to the diagnostic control unit 11, converted into 8-bit right-aligned parallel data, and displayed as hexadecimal numbers.

When the diagnosis is started, five consecutive bits of "0" are loaded into the scan register 10 by editing, but during this time the outputs 17-20 of the registers 6-9 maintain their previous states. When the address is further added and "1" is output from the editing information storage device 4, the operating clock 16 is set to 3.
The clock is output and registers 6 to 9 perform shift operations.
rX-OJ to rX-2J are sequentially taken in from registers (not shown) connected to the previous stage. The scan register 10 takes in the output 20 of the register 9 as scan data, and uses the r data O held in the registers 7 to 9.
” to “data 2” are sent to the diagnostic control device 1 as the scan register output 25.

FIG. 3 is a block diagram of the second embodiment of the present invention, and FIG. 4 is a time chart showing its operation.

The main difference between FIG. 3 and FIG. 1 is that the editing information storage device 4a
has a multi-bit configuration, editing information is held as numerical information for each address, and this editing information storage device 4
The diagnostic control clock 15 is a means for reading the editing information from the clock control circuit 5 (a) and issuing the editing control signal 14 of the clock control circuit 5.
A divide-by-2 circuit 3a that divides the frequency by eight, an address counter 3 that counts the output, and a counter 3b that performs subtraction processing from the output numerical value of the editing information storage device 4a and outputs "1" when it becomes "0". It is configured.

The shift mode control circuit 2a outputs the reset signal 12a at a certain time in synchronization with the shift mode No. 012. The frequency dividing circuit 3a divides the frequency of the diagnostic control clock 15 by eight and outputs a divided clock 27. The address counter 3 is reset by the reset signal 12a, and thereafter the read address is incremented by one by the divided clock 27.

The editing information storage device 4a stores "5" and "7" as editing information for outputting 3-bit data and 1-bit parity as 8-bit right-justified data. When the address counter 3 is reset by the reset signal 12a, "5" is set in the counter 3b from the editing information storage device 4a. The counter 3b decrements by 1 every diagnostic control clock 15, and when the count value reaches rOJ, the output editing control signal 14 is set to "1" and the operation is stopped. When the frequency dividing clock 27 is supplied from the frequency dividing circuit 3a, the editing control signal 14 is reset to "0", "7" is read into the counter 3c from the editing information storage device 4a, and subtraction is restarted. When the editing control signal 14 becomes "1", the operation clock 16 is supplied to the registers 6-9, and the subsequent operations are exactly the same as in the first embodiment described with reference to FIGS. 1 and 2.

Note that in the above explanation, the editing information of the 3-bit signal is
'', it was explained that the 1-bit parity editing information is ``7'' and the counter 3c performs a subtraction operation, but the editing information is 3-bit signal is ``3'', the parity is ``1'', and the counter performs an addition operation. A method such as setting the output to "1" when the count value reaches "8" may be used.

〔Effect of the invention〕

As described in detail above, the present invention includes an editing information storage device that holds editing information, a clock control circuit that controls the stop of sending a clock signal based on an editing control signal, and a clock control circuit that reads the editing information and generates the editing control signal. It has a control information generation means and displays data with different number of constituent bits and error detection codes separately, so scan path data can be easily analyzed and has the effect of improving the efficiency of evaluation and maintenance of logic integrated circuits. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a time chart showing the operation of the first embodiment,
FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention, and FIG. 4 is a time chart showing the operation of the second embodiment. 1... Diagnosis control device, 2, 2a... Shift mode control circuit, 3... Address counter, 3a... Frequency dividing circuit, 3b... ...Counter, 4...Editing information storage device, 5...
Clock control circuit, 6 to 9...Register, 10
...Scan register.

Claims (1)

[Scope of Claims] 1. A diagnostic control device that generates a diagnostic control clock and a diagnostic control signal that instructs a diagnostic operation of a logic integrated circuit; and a shift mode control circuit that generates a shift mode signal based on the diagnostic control signal; Editing that configures a shift register in the logic integrated circuit to be diagnosed using the shift mode signal and sequentially outputs the held information as scan path data.Editing that holds editing information of the scan path data corresponding to the connection state of the scan path circuit. an information storage device; a clock control circuit that outputs the diagnostic control clock as an operating clock to the scan path circuit to be diagnosed when the edit control signal is "1" during shift mode operation, and stops outputting when the edit control signal is "0"; control information generating means for counting the diagnostic control clock to generate an address signal for the editing information storage device and reading the editing information to generate the editing control signal; A scan path data acquisition method comprising: a scan register that inputs "0" when it is "0" and inputs the scan path data when it is "1". 2. The editing information storage device holds editing information in a 1-bit configuration, and the control information generating means includes an address counter that counts the diagnostic control clock, and the output of the editing information storage device is used as the editing control signal. 2. The scan path data acquisition method according to claim 1. 3. The editing information storage device holds the editing information as bit number information, and the control information generating means includes a frequency dividing circuit that divides the frequency of the diagnostic control clock by eight, an address counter that counts the output thereof, and the editing 2. The scan path according to claim 1, further comprising a counter that adds or subtracts the number of bits output from the information storage device every said diagnostic clock and sets said editing control signal to "1" when a predetermined value is reached. Data collection method.