JP2003133384A - Substrate evaluation element, manufacturing method therefor and evaluating method of soi substrate - Google Patents
Substrate evaluation element, manufacturing method therefor and evaluating method of soi substrateInfo
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- JP2003133384A JP2003133384A JP2001327153A JP2001327153A JP2003133384A JP 2003133384 A JP2003133384 A JP 2003133384A JP 2001327153 A JP2001327153 A JP 2001327153A JP 2001327153 A JP2001327153 A JP 2001327153A JP 2003133384 A JP2003133384 A JP 2003133384A
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- silicon layer
- substrate
- oxide film
- island
- layer
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は絶縁物または絶縁層
(以下、両者を含めて絶縁層と記す)の上にシリコン層
が形成された構造のSOI(Silicon On Insulator) 基
板と呼称される基板の評価用素子、その製造方法及び該
基板評価用素子を用いたSOI基板の評価方法に関し、
より詳細には該SOI基板における前記絶縁層の品質を
正当に評価するための基板評価用素子、その製造方法及
び該基板評価用素子を用いたSOI基板の評価方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate called an SOI (Silicon On Insulator) substrate having a structure in which a silicon layer is formed on an insulator or an insulating layer (both of which are referred to as an insulating layer). Of the evaluation element, the manufacturing method thereof, and the evaluation method of the SOI substrate using the substrate evaluation element,
More specifically, the present invention relates to a substrate evaluation element for validly evaluating the quality of the insulating layer in the SOI substrate, a manufacturing method thereof, and an SOI substrate evaluation method using the substrate evaluation element.
【0002】[0002]
【従来の技術】システムソフトウェアの高機能化、デ−
タの大容量化が進み、また携帯端末の発展に伴って、次
世代の半導体集積回路には、高速かつ低消費電力のもの
が切望されている。SOI基板は、既存のLSI製造プ
ロセスを大幅に変更することなく、今まで使用していた
バルクウェ−ハの代わりに使用するだけで、その上に作
製された半導体装置の高速化及び低消費電力化が実現可
能な半導体基板として注目されている。2. Description of the Related Art Highly functional system software
With the increasing capacity of computers and the development of mobile terminals, next-generation semiconductor integrated circuits are desired to have high speed and low power consumption. The SOI substrate does not significantly change the existing LSI manufacturing process and can be used in place of the bulk wafer that has been used up to now, to speed up and reduce the power consumption of the semiconductor device manufactured thereon. Is attracting attention as a semiconductor substrate that can realize
【0003】このSOI基板を利用して製造された半導
体装置は、耐電圧が高く、α線のソフトエラー率が低く
なるという大きな利点を有する。また、特に薄膜SOI
基板(1μm以下の厚みのシリコン活性層を有するSO
I基板)上に形成されたMOS型半導体装置は、完全空
乏型で動作させた場合、ソ−ス・ドレインのPN接合面
積を小さくできるため、寄生容量が低減され、デバイス
駆動の高速化を図ることができる。また、絶縁層として
の埋め込み酸化膜の容量がゲ−ト酸化膜直下に形成され
る空乏層容量と直列に挿入されているため実質的に空乏
層容量が減少し、このためMOS型半導体装置のサブシ
ュレッド係数を理論限界値近くにまで低減することが可
能であり、低消費電力化を実現することができる。この
ようにSOI基板上に形成されたMOS型半導体装置
は、既存のLSI製造プロセスを大幅に変更することな
く、高速化及び低消費電力化を実現することができる。A semiconductor device manufactured by using this SOI substrate has a great advantage that it has a high withstand voltage and a low α-ray soft error rate. In addition, especially thin film SOI
Substrate (SO having silicon active layer with a thickness of 1 μm or less
When the MOS type semiconductor device formed on the (I substrate) is operated in a fully depleted type, the PN junction area of the source / drain can be reduced, so that the parasitic capacitance is reduced and the device driving speed is increased. be able to. In addition, since the capacitance of the buried oxide film as the insulating layer is inserted in series with the capacitance of the depletion layer formed immediately below the gate oxide film, the depletion layer capacitance is substantially reduced, and therefore the MOS type semiconductor device has It is possible to reduce the subshred coefficient to a value close to the theoretical limit value, and it is possible to realize low power consumption. As described above, the MOS semiconductor device formed on the SOI substrate can achieve high speed and low power consumption without significantly changing the existing LSI manufacturing process.
【0004】通常のバルク基板の品質を評価する場合、
MOS耐圧評価法という方法が広く一般に用いられてき
た(極薄シリコン酸化膜の形成と界面評価技術 p.96:
リアライズ社、1997年発行)。この方法によれば、
p型シリコン基板の品質を評価する場合、シリコン基板
が蓄積状態になるように上部メタル電極に負のバイアス
を印加し、ゲ−ト酸化膜が絶縁破壊する電圧を求め、所
定の判定電圧より高耐圧を示すMOS型半導体装置を良
品とする。そして1枚の基板の中で良品MOS型半導体
装置の占める割合によりシリコン基板の品質を判断す
る。一般的なCZ法により得られたシリコン基板では4
0〜60%、エピタキシャルウェ−ハでは、ほぼ100
%の耐圧良品率を得ることができる。When evaluating the quality of a normal bulk substrate,
A method called MOS withstand voltage evaluation method has been widely used (formation of ultra-thin silicon oxide film and interface evaluation technology p.96:
Realize, published in 1997). According to this method
When evaluating the quality of a p-type silicon substrate, a negative bias is applied to the upper metal electrode so that the silicon substrate is in an accumulation state, and the voltage at which the gate oxide film causes dielectric breakdown is determined. A MOS type semiconductor device exhibiting a withstand voltage is regarded as a good product. Then, the quality of the silicon substrate is determined by the ratio of good MOS semiconductor devices in one substrate. 4 for silicon substrate obtained by general CZ method
0-60%, with epitaxial wafers almost 100
It is possible to obtain a non-defective breakdown voltage rate of%.
【0005】SOI基板においては、絶縁層(埋め込み
酸化膜)があるため、通常、基板裏面側から電気的コン
タクトを取ることができず、基板表面側に電気的コンタ
クトを形成する必要がある。SOI基板のシリコン層が
比較的厚い場合には、コンタクト抵抗を低減する方法、
例えば、コンタクト用メタルと接触するシリコン層部分
の不純物濃度を上げる、シンタリング熱処理を施す等の
方法を採用すれば、従来のMOS耐圧評価法と同等程度
の評価が可能であった。Since an SOI substrate has an insulating layer (buried oxide film), it is usually impossible to make an electrical contact from the back side of the substrate, and it is necessary to form an electrical contact on the front side of the substrate. A method of reducing contact resistance when the silicon layer of the SOI substrate is relatively thick,
For example, if a method such as increasing the impurity concentration of the silicon layer portion in contact with the contact metal, performing sintering heat treatment, or the like was employed, it was possible to evaluate the same level as the conventional MOS breakdown voltage evaluation method.
【0006】図6は従来のSOI基板を評価するための
MOS型評価用素子を示した断面図であり、図中10は
SOI基板を示しており、SOI基板10はSi支持基
板11の上に埋め込み酸化膜12が形成され、埋め込み
酸化膜12の上にシリコン層13が形成された構成とな
っている。シリコン層13の上にはゲート酸化膜14が
形成され、ゲート酸化膜14の上にはポリSi電極15
が形成され、これらシリコン層13、ゲート酸化膜1
4、ポリSi電極15によりMOS型半導体素子が構成
されている。また、ポリSi電極15近傍のゲート酸化
膜14には孔16が形成され、孔16の周辺にはトップ
コンタクト17が形成され、トップコンタクト17下方
のシリコン層13には拡散層18が形成され、トップコ
ンタクト17とシリコン層13との低接触抵抗化が図ら
れている。FIG. 6 is a cross-sectional view showing a MOS type evaluation element for evaluating a conventional SOI substrate. In the figure, 10 shows an SOI substrate, and the SOI substrate 10 is on a Si support substrate 11. The buried oxide film 12 is formed, and the silicon layer 13 is formed on the buried oxide film 12. A gate oxide film 14 is formed on the silicon layer 13, and a poly-Si electrode 15 is formed on the gate oxide film 14.
Are formed, and these silicon layer 13 and gate oxide film 1 are formed.
4. The poly-Si electrode 15 constitutes a MOS type semiconductor element. A hole 16 is formed in the gate oxide film 14 near the poly-Si electrode 15, a top contact 17 is formed around the hole 16, and a diffusion layer 18 is formed in the silicon layer 13 below the top contact 17, The contact resistance between the top contact 17 and the silicon layer 13 is reduced.
【0007】SOI基板10では埋め込み酸化膜12が
存在するため、例えばMOS型半導体素子の絶縁破壊特
性等を評価する際、SOI基板10の裏面側とポリSi
電極15とで電気的接続を図ることができず、上記した
ようにシリコン層13側にトップコンタクト17を形成
していた。トップコンタクト17と拡散層18との接触
抵抗はシリコン層13部分のキャリア濃度を高く(>1
019/cm3 程度)すればかなり低く抑えることができ
る。Since the buried oxide film 12 exists in the SOI substrate 10, for example, when evaluating the dielectric breakdown characteristics of a MOS type semiconductor element, the back surface side of the SOI substrate 10 and the poly Si
The electrode 15 could not be electrically connected, and the top contact 17 was formed on the silicon layer 13 side as described above. The contact resistance between the top contact 17 and the diffusion layer 18 increases the carrier concentration in the silicon layer 13 portion (> 1).
0 19 / cm 3 or so) can be suppressed to a significantly lower if.
【0008】また、SOI基板10ではシリコン層13
の品質と共に、埋め込み酸化膜12の品質も重要とな
る。上記方法ではシリコン層13の品質は評価できて
も、埋め込み酸化膜12の電気的特性を評価することは
不可能である。この埋め込み酸化膜12の耐圧を評価す
る方法の一つとしてシリコン層13の層厚が1μm以下
の薄いものになると、シリコン層13全体の不純物濃度
を上げてシリコン層13を電極として利用し、埋め込み
酸化膜12をゲ−ト酸化膜に見立てての耐圧の評価を行
う方法が採用されている。Further, in the SOI substrate 10, the silicon layer 13
The quality of the buried oxide film 12 is important as well as the quality of the above. Although the quality of the silicon layer 13 can be evaluated by the above method, the electrical characteristics of the buried oxide film 12 cannot be evaluated. As one of the methods for evaluating the breakdown voltage of the buried oxide film 12, when the layer thickness of the silicon layer 13 is as thin as 1 μm or less, the impurity concentration of the entire silicon layer 13 is increased and the silicon layer 13 is used as an electrode. A method of evaluating the breakdown voltage by using the oxide film 12 as a gate oxide film is adopted.
【0009】[0009]
【発明が解決しようとする課題】しかしながら埋め込み
酸化膜12の膜厚は通常のゲ−ト酸化膜と比べて非常に
厚く、埋め込み酸化膜12の膜質が改善された最近のS
OI基板10や、絶縁層が実質的に熱酸化膜である貼り
合わせSOI基板では、埋め込み酸化膜が絶縁破壊を生
じる確率は低く、上記した基板評価方法が有効な薄膜S
OI基板評価法であるとは言い難いといった課題があっ
た。However, the thickness of the buried oxide film 12 is much thicker than that of a normal gate oxide film, and the quality of the buried oxide film 12 has been improved recently.
In the OI substrate 10 and the bonded SOI substrate in which the insulating layer is a substantially thermal oxide film, the buried oxide film has a low probability of causing dielectric breakdown, and the thin film S for which the above-described substrate evaluation method is effective.
There is a problem that it is difficult to say that this is an OI substrate evaluation method.
【0010】今後は、埋め込み酸化膜の固定電荷や可動
イオン、埋め込み酸化膜とシリコン層の界面準位密度の
評価が重要になってくると考えられる。これらの項目を
比較的単純な素子を用いて評価し、SOI基板製造プロ
セスに迅速にフィ−ドバックすることが切望されてい
る。In the future, it will be important to evaluate the fixed charges and mobile ions of the buried oxide film and the interface state density between the buried oxide film and the silicon layer. It is desired to evaluate these items using a relatively simple device and quickly feed back to the SOI substrate manufacturing process.
【0011】本発明は上記課題に鑑みなされたものであ
って、SOI基板における絶縁層(埋め込み酸化膜)の
固定電荷や可動イオン、埋め込み酸化膜とシリコン層と
の界面準位密度等の評価を可能にする、比較的単純な構
成の基板評価用素子、その製造方法及び該基板評価用素
子を用いたSOI基板の評価方法を提供することを目的
としている。The present invention has been made in view of the above problems, and evaluates fixed charges and mobile ions of an insulating layer (buried oxide film) in an SOI substrate, interface state density between the buried oxide film and a silicon layer, and the like. It is an object of the present invention to provide a substrate evaluation element having a relatively simple structure, a manufacturing method thereof, and an SOI substrate evaluation method using the substrate evaluation element that enable the same.
【0012】[0012]
【課題を解決するための手段及びその効果】上記目的を
達成するために本発明に係る基板評価用素子(1)は、
絶縁層上にシリコン層が形成された基板における前記絶
縁層を評価するための基板評価用素子において、前記基
板上の前記シリコン層が島状に分離され、該島状分離シ
リコン層表面に絶縁膜が形成され、前記島状分離シリコ
ン層に少なくとも3つの電極が前記絶縁膜を貫通するコ
ンタクトホ−ルを介して接続されていることを特徴とし
ている。上記基板評価用素子(1)によれば、前記少な
くとも3つの電極の内、2つの電極をMOSFETにお
けるソ−ス、ドレインとみなし、前記絶縁層の支持基板
をゲ−トとみなしてId−Vg特性を評価することによ
り、SOI基板における前記絶縁層の固定電荷や可動イ
オン、前記絶縁層と前記シリコン層との界面準位密度等
の評価が可能になる。In order to achieve the above object, the substrate evaluation element (1) according to the present invention comprises:
In a substrate evaluation element for evaluating the insulating layer in a substrate having a silicon layer formed on the insulating layer, the silicon layer on the substrate is separated into islands, and an insulating film is formed on the surface of the island-shaped separated silicon layer. Is formed, and at least three electrodes are connected to the island-shaped isolation silicon layer via contact holes penetrating the insulating film. According to the substrate evaluation element (1), two electrodes of the at least three electrodes are regarded as the source and drain of the MOSFET, and the supporting substrate of the insulating layer is regarded as the gate of Id-Vg. By evaluating the characteristics, it becomes possible to evaluate fixed charges and movable ions of the insulating layer in the SOI substrate, interface state density between the insulating layer and the silicon layer, and the like.
【0013】また、本発明に係る基板評価用素子(2)
は、上記基板評価用素子(1)において、前記少なくと
も3つの電極の内、少なくとも2つの電極が接続される
前記島状分離シリコン層の所定領域に独立的高濃度不純
物拡散層が形成されていることを特徴としている。上記
基板評価用素子(2)によれば、前記少なくとも2つの
電極が接続される前記島状分離シリコン層の独立的高濃
度不純物拡散層をMOSFETにおけるソ−ス、ドレイ
ンとみなしてId−Vg特性を評価することにより、前
記独立的高濃度不純物拡散層が電極となり、印加電圧は
効率的に前記絶縁層にかかることになる。このため、前
記シリコン層の薄膜化に影響されることなく、また前記
絶縁層に電界集中箇所を生ずることなく、SOI基板に
おける前記絶縁層の正しい品質評価を行うことができ、
SOI基板における前記絶縁層の固定電荷や可動イオ
ン、前記絶縁層と前記シリコン層との界面準位密度等の
評価がより正確に行えるようになる。A substrate evaluation element (2) according to the present invention
In the substrate evaluation element (1), an independent high-concentration impurity diffusion layer is formed in a predetermined region of the island-shaped isolation silicon layer to which at least two electrodes of the at least three electrodes are connected. It is characterized by that. According to the substrate evaluation element (2), the independent high-concentration impurity diffusion layer of the island-shaped isolation silicon layer to which the at least two electrodes are connected is regarded as the source and drain of the MOSFET, and the Id-Vg characteristic is obtained. By evaluating the above, the independent high-concentration impurity diffusion layer becomes an electrode, and the applied voltage is efficiently applied to the insulating layer. Therefore, it is possible to perform a correct quality evaluation of the insulating layer in the SOI substrate without being affected by the thinning of the silicon layer and without generating an electric field concentration portion in the insulating layer.
The fixed charges and mobile ions of the insulating layer in the SOI substrate and the interface state density between the insulating layer and the silicon layer can be evaluated more accurately.
【0014】また、本発明に係る基板評価用素子(3)
は、上記基板評価用素子(1)又は(2)において、前
記島状分離シリコン層の分離が、前記シリコン層の部分
的除去による空間的分離であることを特徴としている。
また、本発明に係る基板評価用素子(4)は、上記基板
評価用素子(1)又は(2)において、前記島状分離シ
リコン層の分離が、絶縁物の介在による分離であること
を特徴としている。上記基板評価用素子(3)又は
(4)によれば、前記島状分離シリコン層の形成を容易
に行うことができ、また前記シリコン層の分離を確実に
実現することができる。The substrate evaluation element (3) according to the present invention
Is characterized in that in the substrate evaluation element (1) or (2), the separation of the island-shaped separation silicon layer is spatial separation by partial removal of the silicon layer.
The substrate evaluation element (4) according to the present invention is characterized in that, in the substrate evaluation element (1) or (2), the island-shaped separation silicon layer is separated by interposing an insulator. I am trying. According to the substrate evaluation element (3) or (4), the island-shaped isolation silicon layer can be easily formed, and the isolation of the silicon layer can be reliably realized.
【0015】また、本発明に係る基板評価用素子の製造
方法(1)は、
(a)絶縁層上にシリコン層が形成された基板における
前記シリコン層をパタ−ニングして島状に分離する工程
(b)前記島状シリコン層上に酸化膜を形成し、その
後、前記島状シリコン層を少なくとも2つの領域に分離
するように前記酸化膜をパタ−ニングする工程
(c)該酸化膜をマスクにして前記島状シリコン層に不
純物を拡散させて少なくとも2つの独立的高濃度不純物
拡散層領域を形成する工程
(d)前記酸化膜を除去し、その後層間絶縁酸化膜を形
成する工程
(e)前記島状分離シリコン層の異なる少なくとも3つ
の領域にそれぞれ接続されるコンタクトホ−ルを形成
し、これらのコンタクトホ−ル部分に電極を形成する工
程
を含んでいることを特徴としている。上記基板評価用素
子の製造方法(1)によれば、SOI基板における前記
絶縁層の正しい品質評価を行うことができる基板評価用
素子を容易に製造することができる。In the method (1) for manufacturing a device for evaluating a substrate according to the present invention, (a) the silicon layer on a substrate having a silicon layer formed on an insulating layer is patterned to be separated into islands. Step (b) Forming an oxide film on the island-shaped silicon layer, and then patterning the oxide film so as to separate the island-shaped silicon layer into at least two regions. (C) Forming the oxide film D) Impurities are diffused into the island-shaped silicon layer by using a mask to form at least two independent high-concentration impurity diffusion layer regions (d) The oxide film is removed, and then an interlayer insulating oxide film is formed (e) ) Forming contact holes respectively connected to at least three different regions of the island-shaped isolation silicon layer, and forming electrodes on these contact hole portions. There is. According to the method (1) for manufacturing a substrate evaluation element described above, it is possible to easily manufacture a substrate evaluation element capable of performing a correct quality evaluation of the insulating layer in the SOI substrate.
【0016】また、本発明に係るSOI基板の評価方法
(1)は、上記基板評価用素子(2)を用い、少なくと
も2つの前記独立的高濃度不純物拡散層領域をソ−ス、
ドレイン、不純物が拡散されていない島状分離シリコン
層領域をボディ、前記絶縁層をゲ−ト酸化膜とみなして
MOSFETの静特性に基づいて前記絶縁層を評価する
ことを特徴としている。上記SOI基板の評価方法
(1)によれば、SOI基板における前記シリコン層の
薄膜化に影響されることなく、前記絶縁層に電界集中箇
所を生じさせることなく、SOI基板における前記絶縁
層の正しい品質評価を行うことができ、また前記絶縁層
と前記シリコン層との界面準位密度等の評価も可能にな
る。Further, an SOI substrate evaluation method (1) according to the present invention uses the substrate evaluation element (2) described above, and uses at least two independent high-concentration impurity diffusion layer regions as sources.
It is characterized in that the drain and the island-shaped isolation silicon layer region in which impurities are not diffused are regarded as a body, and the insulating layer is regarded as a gate oxide film, and the insulating layer is evaluated based on the static characteristics of the MOSFET. According to the method (1) for evaluating an SOI substrate described above, the insulating layer in the SOI substrate is not affected by the thinning of the silicon layer in the SOI substrate, the electric field is not concentrated in the insulating layer, and the insulating layer in the SOI substrate is correct. The quality can be evaluated, and the interface state density between the insulating layer and the silicon layer can be evaluated.
【0017】[0017]
【発明の実施の形態】以下、本発明に係る基板評価用素
子、その製造方法及び該基板評価用素子を用いたSOI
基板の評価方法の実施の形態を図面に基づいて説明す
る。図1(a)〜(d)及び図2(a)〜(c)は実施
の形態に係る基板評価用素子の製造工程の概略を示す断
面図であり、図1(a)は製造工程が施される前の状態
のSOI基板20を示している。図中21はSi支持基
板を示しており、Si支持基板21の上には埋め込み酸
化膜(絶縁層)22が形成され、埋め込み酸化膜22の
上にはシリコン層23が形成されている。BEST MODE FOR CARRYING OUT THE INVENTION A device for evaluating a substrate according to the present invention, a method for manufacturing the same, and an SOI using the device for evaluating a substrate are described below.
An embodiment of a board evaluation method will be described with reference to the drawings. 1 (a) to 1 (d) and 2 (a) to 2 (c) are cross-sectional views showing the outline of the manufacturing process of the substrate evaluation element according to the embodiment, and FIG. 1 (a) shows the manufacturing process. It shows the SOI substrate 20 in a state before being applied. In the figure, reference numeral 21 denotes a Si supporting substrate. A buried oxide film (insulating layer) 22 is formed on the Si supporting substrate 21, and a silicon layer 23 is formed on the buried oxide film 22.
【0018】まず、このSOI基板20のシリコン層2
3上にレジスト(図示せず)を塗布し、露光、現像して
このレジストを島状に分離された形状にパタ−ニング
し、このレジストパタ−ンをマスクとしてシリコン層2
3にエッチングを施し、その後レジストパタ−ンを除去
する(図1(b))。このシリコン層23のエッチング
には例えば、HF/HNO3 /H2 O、あるいはHF/
HNO3 /CH3 COOH/H2 Oを用いたウエットエ
ッチングを採用する。First, the silicon layer 2 of the SOI substrate 20.
3 is coated with a resist (not shown), exposed and developed to pattern this resist into island-shaped separated shapes, and the resist pattern is used as a mask to form the silicon layer 2
3 is etched, and then the resist pattern is removed (FIG. 1 (b)). For etching the silicon layer 23, for example, HF / HNO 3 / H 2 O or HF /
Wet etching using HNO 3 / CH 3 COOH / H 2 O is adopted.
【0019】次にエッチングされ、島状に分離された形
状の各シリコン層23を2つの領域に分離する形状のC
VD酸化膜24を形成するために、まずSOI基板20
の全面にCVD酸化膜(図示せず)を800〜1000
℃、40〜80分、圧力0.3〜0.7hPa、100
%の酸素雰囲気の条件で、厚さ50〜150nm程度形
成する。次に、このCVD酸化膜上にレジスト(図示せ
ず)を塗布し、露光、現像して所定の島状に分離された
形状の各シリコン層23を2つの領域に分離する形状の
レジストパタ−ン(図示せず)を形成し、このレジスト
パタ−ンをマスクとしてCVD酸化膜をエッチングし、
その後このレジストパタ−ンを除去する(図1
(c))。このCVD酸化膜のエッチングには例えば、
HF、あるいはBHFを用いたウエットエッチングを採
用する。この時点におけるSOI基板20の平面図を図
3に示す。島状に分離された形状の各シリコン層23が
CVD酸化膜24により2つの領域に分離されている。Next, a C shape is formed which separates each of the island-shaped separated silicon layers 23 into two regions by etching.
In order to form the VD oxide film 24, first, the SOI substrate 20 is formed.
A CVD oxide film (not shown) on the entire surface of
C, 40 to 80 minutes, pressure 0.3 to 0.7 hPa, 100
% Oxygen atmosphere, a thickness of about 50 to 150 nm is formed. Next, a resist pattern (not shown) is applied on the CVD oxide film, exposed and developed to separate each silicon layer 23 having a predetermined island shape into two regions. (Not shown) is formed, and the CVD oxide film is etched using this resist pattern as a mask.
After that, this resist pattern is removed (see FIG. 1).
(C)). For etching the CVD oxide film, for example,
Wet etching using HF or BHF is adopted. A plan view of the SOI substrate 20 at this point is shown in FIG. Each island-shaped silicon layer 23 is separated into two regions by a CVD oxide film 24.
【0020】次に、このCVD酸化膜24をマスクとし
て2つの領域に分離された各シリコン層23にn型拡散
層23a、23bの形成を目的として不純物拡散、例え
ばリン拡散を行う(図1(d))。このリン拡散処理は
例えば、POCl3 +N2 +O2 の雰囲気で、850〜
950℃の条件で、3〜10分間行う。Next, using the CVD oxide film 24 as a mask, impurity diffusion such as phosphorus diffusion is performed on each silicon layer 23 separated into two regions for the purpose of forming n-type diffusion layers 23a and 23b (see FIG. 1 ( d)). This phosphorus diffusion treatment is performed, for example, in an atmosphere of POCl 3 + N 2 + O 2 at 850-
It is performed for 3 to 10 minutes under the condition of 950 ° C.
【0021】不純物拡散工程の後、マスクに用いたCV
D酸化膜24をHF、あるいはBHFを用いたウエット
エッチングにより除去する(図2(a))。その後、S
iH4 +N2 Oを原料ガスとして800〜900℃、4
0〜80分、圧力0.3〜0.7hPaの条件で、厚さ
50〜150nm程度の層間絶縁酸化膜26を形成する
(図2(b))。この層間絶縁酸化膜26の形成は、上
記CVD法による他、別の実施の形態では、700〜1
200℃、希釈酸素雰囲気あるいは100%酸素雰囲気
の条件下での熱酸化法によっても差し支えない。CV used as a mask after the impurity diffusion step
The D oxide film 24 is removed by wet etching using HF or BHF (FIG. 2A). Then S
iH 4 + N 2 O as raw material gas at 800 to 900 ° C., 4
The interlayer insulating oxide film 26 having a thickness of about 50 to 150 nm is formed under the conditions of 0 to 80 minutes and the pressure of 0.3 to 0.7 hPa (FIG. 2B). The interlayer insulating oxide film 26 is formed by the above-described CVD method, or 700 to 1 in another embodiment.
The thermal oxidation method under the conditions of 200 ° C., diluted oxygen atmosphere or 100% oxygen atmosphere may be used.
【0022】次に、リン拡散が行われた2つの領域、及
びリン拡散が行われていない領域の、合計3つの領域の
それぞれにコンタクトホ−ル26a、26b、26cを
形成するために、まず層間絶縁酸化膜26の上にフォト
レジスト層(図示せず)を形成し、フォトリソ工程を施
して所定形状のコンタクトホ−ルパタ−ン(図示せず)
を形成する。次に、このフォトレジストパタ−ンをマス
クにして、層間絶縁酸化膜26にエッチング処理を施
す。このエッチング処理は、HF、あるいはBHFを用
いたウエットエッチング、あるいはCF4 、CHF3 、
C6 F3 、C3 F8 等を用いたプラズマドライエッチン
グで行う。Next, in order to form contact holes 26a, 26b, 26c in each of a total of three regions, that is, two regions where phosphorus diffusion has been performed and regions where phosphorus diffusion has not been performed, first. A photoresist layer (not shown) is formed on the interlayer insulating oxide film 26, and a photolithography process is performed to form a contact hole pattern (not shown) having a predetermined shape.
To form. Next, using this photoresist pattern as a mask, the interlayer insulating oxide film 26 is subjected to etching treatment. This etching treatment is performed by wet etching using HF or BHF, or CF 4 , CHF 3 ,
It is performed by plasma dry etching using C 6 F 3 , C 3 F 8 or the like.
【0023】その後、トップコンタクトとなる電極2
7、28、29を形成するために、Al、Al−Si−
Cu、W、Ti等からなる金属層(図示せず)をスパッ
タ法あるいはCVD法により厚さ0.5〜3μm程度形
成する。次にこの金属層の上にフォトレジスト層(図示
せず)を形成し、フォトリソ工程を施して所定形状の電
極パタ−ンを有するフォトレジストパタ−ン(図示せ
ず)を形成する。次に、このフォトレジストパタ−ンを
マスクにして、前記金属層にエッチング処理を施し、電
極27、28、29を形成する。この金属層のエッチン
グ処理は、前記金属層がAlで形成されている場合に
は、H3 PO3 +CH3 COOH等の混合溶液によるウ
エットエッチングか、CCl4 、BCl3 、BBr3 、
HBr等を用いたプラズマドライエッチングで行う。こ
れで基板評価用素子の製造は完了である(図2
(c))。After that, the electrode 2 to be the top contact
In order to form 7, 28 and 29, Al, Al-Si-
A metal layer (not shown) made of Cu, W, Ti or the like is formed to a thickness of about 0.5 to 3 μm by a sputtering method or a CVD method. Next, a photoresist layer (not shown) is formed on the metal layer, and a photolithography process is performed to form a photoresist pattern (not shown) having an electrode pattern of a predetermined shape. Next, using the photoresist pattern as a mask, the metal layer is etched to form electrodes 27, 28 and 29. When the metal layer is made of Al, the metal layer is etched by wet etching with a mixed solution of H 3 PO 3 + CH 3 COOH, CCl 4 , BCl 3 , BBr 3 , or the like.
Plasma dry etching using HBr or the like is performed. This completes the manufacture of the board evaluation element (see FIG. 2).
(C)).
【0024】上記した工程により、SOI基板20に、
埋め込み酸化膜22をゲ−ト酸化膜とし、リン拡散が行
われていないシリコン層23領域、拡散層23a、23
b、及びSi支持基板21からなるMOSキャパシタ3
0が形成されることとなる。Through the above steps, the SOI substrate 20 is
The buried oxide film 22 is used as a gate oxide film, and the silicon layer 23 region in which phosphorus is not diffused and the diffusion layers 23a and 23 are formed.
b and a MOS capacitor 3 including the Si support substrate 21
0 will be formed.
【0025】MOSFETの線形領域におけるId−V
g特性は、
Id=(μeff CoxWeff /Leff )((Vg−Vt)
Vd−(1/2)×Vd2 )
で表わされる。ここで、
μeff : 実効的チャネル移動度
Cox : 埋め込み酸化膜をゲ−ト酸化膜とした時のゲ
−ト酸化膜容量
Weff : MOSFETの実効チャネル幅
Leff : MOSFETの実効チャネル長
Vg : ゲ−ト電圧
Vt : 閾値電圧
Vd : ドレイン電圧
をそれぞれ表わしている。Id-V in linear region of MOSFET
The g characteristic is Id = (μ eff Cox W eff / L eff ) ((Vg−Vt)
It is represented by Vd− (½) × Vd 2 ). Here, μ eff : Effective channel mobility C ox : Gate oxide film capacitance W eff when the buried oxide film is a gate oxide film: Effective channel width L eff of MOSFET: Effective channel length Vg of MOSFET : Gate voltage Vt: Threshold voltage Vd: Drain voltage, respectively.
【0026】Id−Vg特性の傾きの最大値より、実効
的チャネル移動度μeff が求まり、このμeff は埋め込
み酸化膜界面の特性を反映しており、埋め込み酸化膜界
面の優劣を評価することができる。また埋め込み酸化膜
22の閾値電圧Vtは、埋め込み酸化膜22内の固定電
荷に依存するので、この閾値電圧Vtから埋め込み酸化
膜22の固定電荷の評価をすることができる。また、1
50〜250℃の高温下でSi支持基板21とリン拡散
が行われていないシリコン層23領域との間にバイアス
をかけておき、バイアス印加前後の閾値電圧Vtの変化
から可動イオン量を見積もることができる。このよう
に、通常のMOSFETにおいてよく知られている解析
方法を、実施の形態に係るMOSキャパシタ30(基板
評価用素子)に適用すれば、埋め込み酸化膜22及び埋
め込み酸化膜22界面の評価を行うことができる。From the maximum value of the slope of the Id-Vg characteristic, the effective channel mobility μ eff is obtained, and this μ eff reflects the characteristics of the buried oxide film interface, and the superiority or inferiority of the buried oxide film interface should be evaluated. You can Further, since the threshold voltage Vt of the buried oxide film 22 depends on the fixed charge in the buried oxide film 22, the fixed charge of the buried oxide film 22 can be evaluated from the threshold voltage Vt. Also, 1
A bias is applied between the Si support substrate 21 and the region of the silicon layer 23 in which phosphorus is not diffused at a high temperature of 50 to 250 ° C., and the amount of mobile ions is estimated from the change in the threshold voltage Vt before and after the bias application. You can As described above, if the well-known analysis method for a normal MOSFET is applied to the MOS capacitor 30 (substrate evaluation element) according to the embodiment, the buried oxide film 22 and the interface of the buried oxide film 22 are evaluated. be able to.
【0027】[0027]
【実施例】以下、本発明に係る基板評価用素子、その製
造方法及び該基板評価用素子を用いたSOI基板の評価
方法の実施例を説明する。まず、以下に示す条件によ
り、図2(c)に示す実施例に係るMOSキャパシタ3
0(基板評価用素子)を製造した。EXAMPLES Examples of a substrate evaluation element, a manufacturing method thereof and an SOI substrate evaluation method using the substrate evaluation element according to the present invention will be described below. First, under the following conditions, the MOS capacitor 3 according to the embodiment shown in FIG.
0 (element for substrate evaluation) was manufactured.
【0028】実施例1
・用いたSOI基板 SIMOX
・シリコン層23 厚さ :100nm
シリコン層23のエッチング HF/HNO3 /H2
Oを用いたウエットエッチング
シリコン層23へのリン拡散処理 POCl3 +N2
+O2 の雰囲気で、900℃、5分間
・埋め込み酸化膜22 膜厚 :100nm
・CVD酸化膜24 膜厚 :100nm
CVD酸化膜24のエッチング HFを用いたウエッ
トエッチング
・層間絶縁酸化膜26 膜厚 :100nm
層間絶縁酸化膜26の形成 SiH4 +N2 Oを原料ガ
スとして850℃、60分、圧力0.35hPa
・MOSFETのゲ−ト長 500μm
・MOSFETのゲ−ト幅 500μm実施例2
・用いたSOI基板 貼り合わせSOI
・その他の条件は実施例1と同じ実施例3
・用いたSOI基板 SIMOX
・評価用素子を形成する前に、1000℃、30分、N
2 雰囲気でアニ−ルを行って固定電荷密度の低減を図っ
ておいた
・その他の条件は実施例1と同じ基板評価用素子の特性測定
図4に、上記各条件により製造した実施例1、2に係る
基板評価用素子を用いて、MOSFETの線形領域のI
d−Vg特性を測定した結果を示す。Id−Vg特性の
傾きの最大値より、実効的チャネル移動度μeff を求め
た結果、実施例1に係るSIMOXの場合、μeff は9
00cm2 /Vs、実施例2に係る貼り合わせSOI基
板の場合、μeff は1100cm2 /Vsとなり、貼り
合わせSOI基板を用いたものの方が、埋め込み酸化膜
22界面の状態は良好であると言える。これは、貼り合
わせSOI基板の方が埋め込み酸化膜22とシリコン層
23との界面の界面順位密度が低いことを示唆してい
る。 Example 1 SOI substrate used SIMOX Silicon layer 23 thickness: 100 nm Etching of silicon layer HF / HNO 3 / H 2
Wet etching using O to diffuse phosphorus into silicon layer 23 POCl 3 + N 2
900 ° C. for 5 minutes in + O 2 atmosphere ・ Built-in oxide film 22 film thickness: 100 nm ・ CVD oxide film 24 film thickness: 100 nm CVD oxide film 24 etching Wet etching using HF ・ Interlayer insulating oxide film 26 film thickness: Formation of 100 nm interlayer insulating oxide film 26 Using SiH 4 + N 2 O as a source gas at 850 ° C. for 60 minutes, pressure 0.35 hPa ・ Gate length of MOSFET 500 μm ・ Gate width of MOSFET 500 μm Example 2・ SOI used before the substrate bonding SOI-other conditions for forming the SOI substrate SIMOX-evaluation device using the same example 3, example 1, 1000 ℃, 30 min, N
Annealing was carried out in 2 atmospheres to reduce the fixed charge density. Other conditions are the same as in Example 1 and the measurement of the characteristics of the substrate evaluation element is shown in FIG. Using the substrate evaluation element according to No. 2, I in the linear region of the MOSFET
The result of having measured the d-Vg characteristic is shown. As a result of obtaining the effective channel mobility μ eff from the maximum value of the slope of the Id-Vg characteristics, in the case of SIMOX according to the first embodiment, μ eff is 9
In the case of the bonded SOI substrate of 00 cm 2 / Vs and Example 2, μ eff is 1100 cm 2 / Vs, and it can be said that the state of the buried oxide film 22 interface is better when using the bonded SOI substrate. . This suggests that the bonded SOI substrate has a lower interface rank density at the interface between the buried oxide film 22 and the silicon layer 23.
【0029】図5に、実施例1、実施例3に係る基板評
価用素子を用い、Id−Vg特性を測定した結果を示
す。固定電荷密度は、主に埋め込み酸化膜22中のシリ
コン層23界面近傍に存在する酸素欠損が原因とされて
いるが、埋め込み酸化膜22の形成後、不活性ガス雰囲
気で高温アニ−ルを行なうと、固定電荷密度は低減する
ことが知られている。従って、実施例3に係る基板評価
用素子の場合、固定電荷密度の低減が図られている。FIG. 5 shows the results of measurement of Id-Vg characteristics using the substrate evaluation elements according to Examples 1 and 3. The fixed charge density is mainly caused by oxygen vacancies existing near the interface of the silicon layer 23 in the buried oxide film 22, but after the buried oxide film 22 is formed, high temperature annealing is performed in an inert gas atmosphere. It is known that the fixed charge density decreases. Therefore, in the case of the substrate evaluation element according to Example 3, the fixed charge density is reduced.
【0030】Id−Vg特性の傾きが最大となる接線が
x軸と交わる交点より、閾値電圧Vtが求められる。高
温アニ−ル処理が施され、固定電荷密度の低減が図られ
た実施例3に係る基板評価用素子の場合、閾値電圧Vt
は1.12Vとなり、高温アニ−ル処理が施されていな
い、実施例1に係る基板評価用素子の場合、閾値電圧V
tは0.414Vであった。これらの閾値電圧から固定
電荷密度Nssを計算する。The threshold voltage Vt is obtained from the intersection point where the tangent line having the maximum gradient of the Id-Vg characteristic intersects the x axis. In the case of the substrate evaluation element according to Example 3 in which the high-temperature annealing treatment was performed to reduce the fixed charge density, the threshold voltage Vt
Is 1.12 V, which is the threshold voltage V in the case of the substrate evaluation element according to Example 1 which is not subjected to the high temperature annealing treatment.
t was 0.414V. The fixed charge density N ss is calculated from these threshold voltages.
【0031】Vt=Vfb+2φf+qNaWmax/Cox
ここで
φf=kT/q{ln(Na/ni)}
Wmax=(2×εs×ε0×2φf/qNa)1/2
Cox=εsio2ε0 S/TBox
上記4式より、
Na=5e15[cm-3],k=1.38e-23[J/
k]
T=300[k],q=1.6e-19[C]
ni=1.45e10[cm-3],εS=11.7,εsio2
=3.82
ε0=8.85e-12[F/m],Tox=100[nm]
として、Vfbを求め
Vfb=φms−Nss×q/Cox
φms=ψm−ψs=kT/q{ln(Nsub/ni)}−k
T/q{ln(Na/Ni)}
Nsub=1e15[cm-3]
より、固定電荷密度Nssを求めた。Vt = V fb + 2φ f + qNaW max / C ox where φ f = kT / q {ln (Na / n i )} W max = (2 × ε s × ε 0 × 2φ f / qNa) 1 / 2 C ox = ε sio 2 ε 0 S / T Box From the above formula 4, Na = 5e 15 [cm −3 ], k = 1.38e −23 [J /
k] T = 300 [k], q = 1.6e −19 [C] n i = 1.45e 10 [cm −3 ], ε S = 11.7, ε sio 2
= 3.82 ε 0 = 8.85e -12 [F / m] and Tox = 100 [nm], V fb is calculated and V fb = φ ms −N ss × q / C ox φ ms = ψ m − ψ s = kT / q {ln (N sub / n i )}-k
The fixed charge density N ss was calculated from T / q {ln (Na / N i )} N sub = 1e 15 [cm −3 ].
【0032】実施例3に係る評価用素子の場合、1×e
11cm-2となり、実施例1に係る評価用素子の場合、
2.5×e11cm-2となった。このように、実施例に係
る基板評価用素子の閾値電圧を評価することで、埋め込
み酸化膜22の固定電荷密度を評価することができる。In the case of the evaluation element according to Example 3, 1 × e
It becomes 11 cm -2 , and in the case of the evaluation element according to Example 1,
It became 2.5 × e 11 cm −2 . Thus, the fixed charge density of the buried oxide film 22 can be evaluated by evaluating the threshold voltage of the substrate evaluation element according to the example.
【図1】(a)〜(d)は本発明の実施の形態に係る基
板評価用素子の製造工程の概略を示す断面図である。1A to 1D are cross-sectional views showing an outline of a manufacturing process of a substrate evaluation element according to an embodiment of the present invention.
【図2】(a)〜(c)は実施の形態に係る基板評価用
素子の製造工程の概略を示す断面図である。2A to 2C are cross-sectional views showing an outline of a manufacturing process of a substrate evaluation element according to an embodiment.
【図3】本発明の実施の形態に係る基板評価用素子の製
造途中における状態を示す平面図である。FIG. 3 is a plan view showing a state in the middle of manufacturing the substrate evaluation element according to the embodiment of the present invention.
【図4】実施例に係る基板評価用素子のId−Vg特性
を示すグラフである。FIG. 4 is a graph showing Id-Vg characteristics of the substrate evaluation element according to the example.
【図5】実施例に係る基板評価用素子のId−Vg特性
を示すグラフである。FIG. 5 is a graph showing Id-Vg characteristics of the substrate evaluation element according to the example.
【図6】従来の基板評価用素子としてのMOSキャパシ
タを示す断面図である。FIG. 6 is a sectional view showing a conventional MOS capacitor as a substrate evaluation element.
20 SOI基板 21 Si支持基板 22 埋め込み酸化膜 23 シリコン層 23a、23b n型拡散層 24 CVD酸化膜 26 層間絶縁酸化膜 26a、26b、26c コンタクトホ−ル 27 電極 28 電極 29 電極 30 MOSキャパシタ 20 SOI substrate 21 Si support substrate 22 Embedded oxide film 23 Silicon layer 23a, 23b n-type diffusion layer 24 CVD oxide film 26 Interlayer insulating oxide film 26a, 26b, 26c contact holes 27 electrodes 28 electrodes 29 electrodes 30 MOS capacitor
Claims (6)
における前記絶縁層を評価するための基板評価用素子に
おいて、前記基板上の前記シリコン層が島状に分離さ
れ、該島状分離シリコン層表面に絶縁膜が形成され、前
記島状分離シリコン層に少なくとも3つの電極が前記絶
縁膜を貫通するコンタクトホ−ルを介して接続されてい
ることを特徴とする基板評価用素子。1. A substrate evaluation element for evaluating the insulating layer in a substrate having a silicon layer formed on the insulating layer, wherein the silicon layer on the substrate is separated into islands, and the island-shaped isolated silicon is formed. An element for evaluating a substrate, wherein an insulating film is formed on a layer surface, and at least three electrodes are connected to the island-shaped isolation silicon layer via a contact hole penetrating the insulating film.
とも2つの電極が接続される前記島状分離シリコン層の
所定領域に独立的高濃度不純物拡散層が形成されている
ことを特徴とする請求項1記載の基板評価用素子。2. An independent high-concentration impurity diffusion layer is formed in a predetermined region of the island-shaped isolation silicon layer to which at least two electrodes of the at least three electrodes are connected. 1. The element for evaluating a substrate according to 1.
シリコン層の部分的除去による空間的分離であることを
特徴とする請求項1又は請求項2記載の基板評価用素
子。3. The device for evaluating a substrate according to claim 1, wherein the separation of the island-shaped isolation silicon layer is a spatial separation by partially removing the silicon layer.
物の介在による分離であることを特徴とする請求項1又
は請求項2記載の基板評価用素子。4. The substrate evaluation element according to claim 1 or 2, wherein the island-shaped isolation silicon layer is separated by interposing an insulating material.
た基板における前記シリコン層をパタ−ニングして島状
に分離する工程 (b)前記島状シリコン層上に酸化膜を形成し、その
後、前記島状シリコン層を少なくとも2つの領域に分離
するように前記酸化膜をパタ−ニングする工程 (c)該酸化膜をマスクにして前記島状シリコン層に不
純物を拡散させて少なくとも2つの独立的高濃度不純物
拡散層領域を形成する工程 (d)前記酸化膜を除去し、その後層間絶縁酸化膜を形
成する工程 (e)前記島状分離シリコン層の異なる少なくとも3つ
の領域にそれぞれ接続されるコンタクトホ−ルを形成
し、これらのコンタクトホ−ル部分に電極を形成する工
程 を含んでいることを特徴とする基板評価用素子の製造方
法。5. A step of: (a) patterning the silicon layer on a substrate having a silicon layer formed on an insulating layer to separate the silicon layer into island shapes; and (b) forming an oxide film on the island silicon layer. Then, the step of patterning the oxide film so as to separate the island-shaped silicon layer into at least two regions (c) At least 2 by diffusing impurities into the island-shaped silicon layer using the oxide film as a mask. Forming two independent high-concentration impurity diffusion layer regions (d) removing the oxide film, and then forming an interlayer insulating oxide film (e) connecting to at least three different regions of the island-shaped isolation silicon layer And a step of forming electrodes on the contact holes, and a step of forming electrodes on the contact holes.
少なくとも2つの前記独立的高濃度不純物拡散層領域を
ソ−ス、ドレイン、不純物が拡散されていない島状分離
シリコン層領域をボディ、前記絶縁層をゲ−ト酸化膜と
みなしてMOSFETの静特性に基づいて前記絶縁層を
評価することを特徴とするSOI基板の評価方法。6. The substrate evaluation device according to claim 2,
At least two independent high-concentration impurity diffusion layer regions are regarded as sources and drains, island-shaped isolation silicon layer regions in which impurities are not diffused are regarded as bodies, and the insulating layer is regarded as a gate oxide film. A method for evaluating an SOI substrate, characterized in that the insulating layer is evaluated based on the above.
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