JP2003133384A - Substrate evaluation element, manufacturing method therefor and evaluating method of soi substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the substrate evaluation element having a comparatively simple constitution, which evaluates fixed charges and movable ions in an insulating layer (embedded oxide film), in an SOI substrate and interface level density between the embedded oxide film and a silicon layer. SOLUTION: In the substrate evaluation element evaluates the embedded oxide film 22 in the SOI substrate 20, where the silicon layer 23 is formed on the embedded oxide film 22, the silicon layer 23 is isolated in an island shape, and an interlayer insulation oxide film 26 is formed on the surface of the island-like separation silicon layer 23. At least three electrodes 27, 28 and 29 are connected to the island-like isolation silicon layer 23 via contact holes 26a, 26b and 26c which pass through the interlayer insulation oxide film 26.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate called an SOI (Silicon On Insulator) substrate having a structure in which a silicon layer is formed on an insulator or an insulating layer (both of which are referred to as an insulating layer). Of the evaluation element, the manufacturing method thereof, and the evaluation method of the SOI substrate using the substrate evaluation element,
More specifically, the present invention relates to a substrate evaluation element for validly evaluating the quality of the insulating layer in the SOI substrate, a manufacturing method thereof, and an SOI substrate evaluation method using the substrate evaluation element.

[0002]

2. Description of the Related Art Highly functional system software
With the increasing capacity of computers and the development of mobile terminals, next-generation semiconductor integrated circuits are desired to have high speed and low power consumption. The SOI substrate does not significantly change the existing LSI manufacturing process and can be used in place of the bulk wafer that has been used up to now, to speed up and reduce the power consumption of the semiconductor device manufactured thereon. Is attracting attention as a semiconductor substrate that can realize

A semiconductor device manufactured by using this SOI substrate has a great advantage that it has a high withstand voltage and a low α-ray soft error rate. In addition, especially thin film SOI
Substrate (SO having silicon active layer with a thickness of 1 μm or less
When the MOS type semiconductor device formed on the (I substrate) is operated in a fully depleted type, the PN junction area of the source / drain can be reduced, so that the parasitic capacitance is reduced and the device driving speed is increased. be able to. In addition, since the capacitance of the buried oxide film as the insulating layer is inserted in series with the capacitance of the depletion layer formed immediately below the gate oxide film, the depletion layer capacitance is substantially reduced, and therefore the MOS type semiconductor device has It is possible to reduce the subshred coefficient to a value close to the theoretical limit value, and it is possible to realize low power consumption. As described above, the MOS semiconductor device formed on the SOI substrate can achieve high speed and low power consumption without significantly changing the existing LSI manufacturing process.

When evaluating the quality of a normal bulk substrate,
A method called MOS withstand voltage evaluation method has been widely used (formation of ultra-thin silicon oxide film and interface evaluation technology p.96:
Realize, published in 1997). According to this method
When evaluating the quality of a p-type silicon substrate, a negative bias is applied to the upper metal electrode so that the silicon substrate is in an accumulation state, and the voltage at which the gate oxide film causes dielectric breakdown is determined. A MOS type semiconductor device exhibiting a withstand voltage is regarded as a good product. Then, the quality of the silicon substrate is determined by the ratio of good MOS semiconductor devices in one substrate. 4 for silicon substrate obtained by general CZ method
0-60%, with epitaxial wafers almost 100
It is possible to obtain a non-defective breakdown voltage rate of%.

Since an SOI substrate has an insulating layer (buried oxide film), it is usually impossible to make an electrical contact from the back side of the substrate, and it is necessary to form an electrical contact on the front side of the substrate. A method of reducing contact resistance when the silicon layer of the SOI substrate is relatively thick,
For example, if a method such as increasing the impurity concentration of the silicon layer portion in contact with the contact metal, performing sintering heat treatment, or the like was employed, it was possible to evaluate the same level as the conventional MOS breakdown voltage evaluation method.

FIG. 6 is a cross-sectional view showing a MOS type evaluation element for evaluating a conventional SOI substrate. In the figure, 10 shows an SOI substrate, and the SOI substrate 10 is on a Si support substrate 11. The buried oxide film 12 is formed, and the silicon layer 13 is formed on the buried oxide film 12. A gate oxide film 14 is formed on the silicon layer 13, and a poly-Si electrode 15 is formed on the gate oxide film 14.
Are formed, and these silicon layer 13 and gate oxide film 1 are formed.
4. The poly-Si electrode 15 constitutes a MOS type semiconductor element. A hole 16 is formed in the gate oxide film 14 near the poly-Si electrode 15, a top contact 17 is formed around the hole 16, and a diffusion layer 18 is formed in the silicon layer 13 below the top contact 17, The contact resistance between the top contact 17 and the silicon layer 13 is reduced.

Since the buried oxide film 12 exists in the SOI substrate 10, for example, when evaluating the dielectric breakdown characteristics of a MOS type semiconductor element, the back surface side of the SOI substrate 10 and the poly Si
The electrode 15 could not be electrically connected, and the top contact 17 was formed on the silicon layer 13 side as described above. The contact resistance between the top contact 17 and the diffusion layer 18 increases the carrier concentration in the silicon layer 13 portion (> 1).
0 ¹⁹ / cm ³ or so) can be suppressed to a significantly lower if.

Further, in the SOI substrate 10, the silicon layer 13
The quality of the buried oxide film 12 is important as well as the quality of the above. Although the quality of the silicon layer 13 can be evaluated by the above method, the electrical characteristics of the buried oxide film 12 cannot be evaluated. As one of the methods for evaluating the breakdown voltage of the buried oxide film 12, when the layer thickness of the silicon layer 13 is as thin as 1 μm or less, the impurity concentration of the entire silicon layer 13 is increased and the silicon layer 13 is used as an electrode. A method of evaluating the breakdown voltage by using the oxide film 12 as a gate oxide film is adopted.

[0009]

However, the thickness of the buried oxide film 12 is much thicker than that of a normal gate oxide film, and the quality of the buried oxide film 12 has been improved recently.
In the OI substrate 10 and the bonded SOI substrate in which the insulating layer is a substantially thermal oxide film, the buried oxide film has a low probability of causing dielectric breakdown, and the thin film S for which the above-described substrate evaluation method is effective.
There is a problem that it is difficult to say that this is an OI substrate evaluation method.

In the future, it will be important to evaluate the fixed charges and mobile ions of the buried oxide film and the interface state density between the buried oxide film and the silicon layer. It is desired to evaluate these items using a relatively simple device and quickly feed back to the SOI substrate manufacturing process.

The present invention has been made in view of the above problems, and evaluates fixed charges and mobile ions of an insulating layer (buried oxide film) in an SOI substrate, interface state density between the buried oxide film and a silicon layer, and the like. It is an object of the present invention to provide a substrate evaluation element having a relatively simple structure, a manufacturing method thereof, and an SOI substrate evaluation method using the substrate evaluation element that enable the same.

[0012]

In order to achieve the above object, the substrate evaluation element (1) according to the present invention comprises:
In a substrate evaluation element for evaluating the insulating layer in a substrate having a silicon layer formed on the insulating layer, the silicon layer on the substrate is separated into islands, and an insulating film is formed on the surface of the island-shaped separated silicon layer. Is formed, and at least three electrodes are connected to the island-shaped isolation silicon layer via contact holes penetrating the insulating film. According to the substrate evaluation element (1), two electrodes of the at least three electrodes are regarded as the source and drain of the MOSFET, and the supporting substrate of the insulating layer is regarded as the gate of Id-Vg. By evaluating the characteristics, it becomes possible to evaluate fixed charges and movable ions of the insulating layer in the SOI substrate, interface state density between the insulating layer and the silicon layer, and the like.

A substrate evaluation element (2) according to the present invention
In the substrate evaluation element (1), an independent high-concentration impurity diffusion layer is formed in a predetermined region of the island-shaped isolation silicon layer to which at least two electrodes of the at least three electrodes are connected. It is characterized by that. According to the substrate evaluation element (2), the independent high-concentration impurity diffusion layer of the island-shaped isolation silicon layer to which the at least two electrodes are connected is regarded as the source and drain of the MOSFET, and the Id-Vg characteristic is obtained. By evaluating the above, the independent high-concentration impurity diffusion layer becomes an electrode, and the applied voltage is efficiently applied to the insulating layer. Therefore, it is possible to perform a correct quality evaluation of the insulating layer in the SOI substrate without being affected by the thinning of the silicon layer and without generating an electric field concentration portion in the insulating layer.
The fixed charges and mobile ions of the insulating layer in the SOI substrate and the interface state density between the insulating layer and the silicon layer can be evaluated more accurately.

The substrate evaluation element (3) according to the present invention
Is characterized in that in the substrate evaluation element (1) or (2), the separation of the island-shaped separation silicon layer is spatial separation by partial removal of the silicon layer.
The substrate evaluation element (4) according to the present invention is characterized in that, in the substrate evaluation element (1) or (2), the island-shaped separation silicon layer is separated by interposing an insulator. I am trying. According to the substrate evaluation element (3) or (4), the island-shaped isolation silicon layer can be easily formed, and the isolation of the silicon layer can be reliably realized.

In the method (1) for manufacturing a device for evaluating a substrate according to the present invention, (a) the silicon layer on a substrate having a silicon layer formed on an insulating layer is patterned to be separated into islands. Step (b) Forming an oxide film on the island-shaped silicon layer, and then patterning the oxide film so as to separate the island-shaped silicon layer into at least two regions. (C) Forming the oxide film D) Impurities are diffused into the island-shaped silicon layer by using a mask to form at least two independent high-concentration impurity diffusion layer regions (d) The oxide film is removed, and then an interlayer insulating oxide film is formed (e) ) Forming contact holes respectively connected to at least three different regions of the island-shaped isolation silicon layer, and forming electrodes on these contact hole portions. There is. According to the method (1) for manufacturing a substrate evaluation element described above, it is possible to easily manufacture a substrate evaluation element capable of performing a correct quality evaluation of the insulating layer in the SOI substrate.

Further, an SOI substrate evaluation method (1) according to the present invention uses the substrate evaluation element (2) described above, and uses at least two independent high-concentration impurity diffusion layer regions as sources.
It is characterized in that the drain and the island-shaped isolation silicon layer region in which impurities are not diffused are regarded as a body, and the insulating layer is regarded as a gate oxide film, and the insulating layer is evaluated based on the static characteristics of the MOSFET. According to the method (1) for evaluating an SOI substrate described above, the insulating layer in the SOI substrate is not affected by the thinning of the silicon layer in the SOI substrate, the electric field is not concentrated in the insulating layer, and the insulating layer in the SOI substrate is correct. The quality can be evaluated, and the interface state density between the insulating layer and the silicon layer can be evaluated.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION A device for evaluating a substrate according to the present invention, a method for manufacturing the same, and an SOI using the device for evaluating a substrate are described below.
An embodiment of a board evaluation method will be described with reference to the drawings. 1 (a) to 1 (d) and 2 (a) to 2 (c) are cross-sectional views showing the outline of the manufacturing process of the substrate evaluation element according to the embodiment, and FIG. 1 (a) shows the manufacturing process. It shows the SOI substrate 20 in a state before being applied. In the figure, reference numeral 21 denotes a Si supporting substrate. A buried oxide film (insulating layer) 22 is formed on the Si supporting substrate 21, and a silicon layer 23 is formed on the buried oxide film 22.

First, the silicon layer 2 of the SOI substrate 20.
3 is coated with a resist (not shown), exposed and developed to pattern this resist into island-shaped separated shapes, and the resist pattern is used as a mask to form the silicon layer 2
3 is etched, and then the resist pattern is removed (FIG. 1 (b)). For etching the silicon layer 23, for example, HF / HNO ₃ / H ₂ O or HF /
Wet etching using HNO ₃ / CH ₃ COOH / H ₂ O is adopted.

Next, a C shape is formed which separates each of the island-shaped separated silicon layers 23 into two regions by etching.
In order to form the VD oxide film 24, first, the SOI substrate 20 is formed.
A CVD oxide film (not shown) on the entire surface of
C, 40 to 80 minutes, pressure 0.3 to 0.7 hPa, 100
% Oxygen atmosphere, a thickness of about 50 to 150 nm is formed. Next, a resist pattern (not shown) is applied on the CVD oxide film, exposed and developed to separate each silicon layer 23 having a predetermined island shape into two regions. (Not shown) is formed, and the CVD oxide film is etched using this resist pattern as a mask.
After that, this resist pattern is removed (see FIG. 1).
(C)). For etching the CVD oxide film, for example,
Wet etching using HF or BHF is adopted. A plan view of the SOI substrate 20 at this point is shown in FIG. Each island-shaped silicon layer 23 is separated into two regions by a CVD oxide film 24.

Next, using the CVD oxide film 24 as a mask, impurity diffusion such as phosphorus diffusion is performed on each silicon layer 23 separated into two regions for the purpose of forming n-type diffusion layers 23a and 23b (see FIG. 1 ( d)). This phosphorus diffusion treatment is performed, for example, in an atmosphere of POCl ₃ + N ₂ + O ₂ at 850-
It is performed for 3 to 10 minutes under the condition of 950 ° C.

CV used as a mask after the impurity diffusion step
The D oxide film 24 is removed by wet etching using HF or BHF (FIG. 2A). Then S
iH ₄ + N ₂ O as raw material gas at 800 to 900 ° C., 4
The interlayer insulating oxide film 26 having a thickness of about 50 to 150 nm is formed under the conditions of 0 to 80 minutes and the pressure of 0.3 to 0.7 hPa (FIG. 2B). The interlayer insulating oxide film 26 is formed by the above-described CVD method, or 700 to 1 in another embodiment.
The thermal oxidation method under the conditions of 200 ° C., diluted oxygen atmosphere or 100% oxygen atmosphere may be used.

Next, in order to form contact holes 26a, 26b, 26c in each of a total of three regions, that is, two regions where phosphorus diffusion has been performed and regions where phosphorus diffusion has not been performed, first. A photoresist layer (not shown) is formed on the interlayer insulating oxide film 26, and a photolithography process is performed to form a contact hole pattern (not shown) having a predetermined shape.
To form. Next, using this photoresist pattern as a mask, the interlayer insulating oxide film 26 is subjected to etching treatment. This etching treatment is performed by wet etching using HF or BHF, or CF ₄ , CHF ₃ ,
It is performed by plasma dry etching using C ₆ F ₃ , C ₃ F ₈ or the like.

After that, the electrode 2 to be the top contact
In order to form 7, 28 and 29, Al, Al-Si-
A metal layer (not shown) made of Cu, W, Ti or the like is formed to a thickness of about 0.5 to 3 μm by a sputtering method or a CVD method. Next, a photoresist layer (not shown) is formed on the metal layer, and a photolithography process is performed to form a photoresist pattern (not shown) having an electrode pattern of a predetermined shape. Next, using the photoresist pattern as a mask, the metal layer is etched to form electrodes 27, 28 and 29. When the metal layer is made of Al, the metal layer is etched by wet etching with a mixed solution of H ₃ PO ₃ + CH ₃ COOH, CCl ₄ , BCl ₃ , BBr ₃ , or the like.
Plasma dry etching using HBr or the like is performed. This completes the manufacture of the board evaluation element (see FIG. 2).
(C)).

Through the above steps, the SOI substrate 20 is
The buried oxide film 22 is used as a gate oxide film, and the silicon layer 23 region in which phosphorus is not diffused and the diffusion layers 23a and 23 are formed.
b and a MOS capacitor 3 including the Si support substrate 21
0 will be formed.

Id-V in linear region of MOSFET
The g characteristic is Id = (μ _{eff Cox} W _eff / L _eff ) ((Vg−Vt)
It is represented by Vd− (½) × Vd ² ). Here, μ _eff : Effective channel mobility C _ox : Gate oxide film capacitance W _eff when the buried oxide film is a gate oxide film: Effective channel width L _{eff of} MOSFET: Effective channel length Vg of MOSFET : Gate voltage Vt: Threshold voltage Vd: Drain voltage, respectively.

From the maximum value of the slope of the Id-Vg characteristic, the effective channel mobility μ _eff is obtained, and this μ _eff reflects the characteristics of the buried oxide film interface, and the superiority or inferiority of the buried oxide film interface should be evaluated. You can Further, since the threshold voltage Vt of the buried oxide film 22 depends on the fixed charge in the buried oxide film 22, the fixed charge of the buried oxide film 22 can be evaluated from the threshold voltage Vt. Also, 1
A bias is applied between the Si support substrate 21 and the region of the silicon layer 23 in which phosphorus is not diffused at a high temperature of 50 to 250 ° C., and the amount of mobile ions is estimated from the change in the threshold voltage Vt before and after the bias application. You can As described above, if the well-known analysis method for a normal MOSFET is applied to the MOS capacitor 30 (substrate evaluation element) according to the embodiment, the buried oxide film 22 and the interface of the buried oxide film 22 are evaluated. be able to.

[0027]

EXAMPLES Examples of a substrate evaluation element, a manufacturing method thereof and an SOI substrate evaluation method using the substrate evaluation element according to the present invention will be described below. First, under the following conditions, the MOS capacitor 3 according to the embodiment shown in FIG.
0 (element for substrate evaluation) was manufactured.

Example 1 SOI substrate used SIMOX Silicon layer 23 thickness: 100 nm Etching of silicon layer HF / HNO ₃ / H ₂
Wet etching using O to diffuse phosphorus into silicon layer 23 POCl ₃ + N ₂
900 ° C. for 5 minutes in + O ₂ atmosphere ・ Built-in oxide film 22 film thickness: 100 nm ・ CVD oxide film 24 film thickness: 100 nm CVD oxide film 24 etching Wet etching using HF ・ Interlayer insulating oxide film 26 film thickness: Formation of 100 nm interlayer insulating oxide film 26 Using SiH ₄ + N ₂ O as a source gas at 850 ° C. for 60 minutes, pressure 0.35 hPa ・ Gate length of MOSFET 500 μm ・ Gate width of MOSFET 500 μm Example 2・ SOI used before the substrate bonding SOI-other conditions for forming the SOI substrate SIMOX-evaluation device using the same example 3, example 1, 1000 ℃, 30 min, N
Annealing was carried out in ₂ atmospheres to reduce the fixed charge density. Other conditions are the same as in Example 1 and the measurement of the characteristics of the substrate evaluation element is shown in FIG. Using the substrate evaluation element according to No. 2, I in the linear region of the MOSFET
The result of having measured the d-Vg characteristic is shown. As a result of _obtaining the effective channel mobility μ _eff from the maximum value of the slope of the Id-Vg characteristics, in the case of SIMOX according to the first embodiment, μ _eff is 9
In the case of the bonded SOI substrate of 00 cm ² / Vs and Example 2, μ _eff is 1100 cm ² / Vs, and it can be said that the state of the buried oxide film 22 interface is better when using the bonded SOI substrate. . This suggests that the bonded SOI substrate has a lower interface rank density at the interface between the buried oxide film 22 and the silicon layer 23.

FIG. 5 shows the results of measurement of Id-Vg characteristics using the substrate evaluation elements according to Examples 1 and 3. The fixed charge density is mainly caused by oxygen vacancies existing near the interface of the silicon layer 23 in the buried oxide film 22, but after the buried oxide film 22 is formed, high temperature annealing is performed in an inert gas atmosphere. It is known that the fixed charge density decreases. Therefore, in the case of the substrate evaluation element according to Example 3, the fixed charge density is reduced.

The threshold voltage Vt is obtained from the intersection point where the tangent line having the maximum gradient of the Id-Vg characteristic intersects the x axis. In the case of the substrate evaluation element according to Example 3 in which the high-temperature annealing treatment was performed to reduce the fixed charge density, the threshold voltage Vt
Is 1.12 V, which is the threshold voltage V in the case of the substrate evaluation element according to Example 1 which is not subjected to the high temperature annealing treatment.
t was 0.414V. The fixed charge density N _ss is calculated from these threshold voltages.

Vt = V _fb + 2φ _f + qNaW _max / C _ox where φ _f = kT / q {ln (Na / n _i )} W _max = (2 × ε _s × ε ₀ × 2φ _f / qNa) ^{1 / 2} C _ox = ε sio ₂ ε ₀ S / T _{Box From the} above formula 4, Na = 5e ¹⁵ [cm ⁻³ ], k = 1.38e ⁻²³ [J /
k] T = 300 [k], q = 1.6e ⁻¹⁹ [C] n _i = 1.45e ¹⁰ [cm ⁻³ ], ε _S = 11.7, ε sio ₂
= 3.82 ε ₀ = 8.85e ^-12 [F / m] and _Tox = 100 [nm], V _fb is calculated and V _fb = φ _ms −N _ss × q / C _ox φ _ms = ψ _m − ψ _s = kT / q {ln (N _sub / n _i )}-k
The fixed charge density N _ss was calculated from T / q {ln (Na / N _i )} N _sub = 1e ¹⁵ [cm ⁻³ ].

In the case of the evaluation element according to Example 3, 1 × e
^It becomes ¹¹ cm ^-2 , and in the case of the evaluation element according to Example 1,
It became 2.5 × e ¹¹ cm ⁻² . Thus, the fixed charge density of the buried oxide film 22 can be evaluated by evaluating the threshold voltage of the substrate evaluation element according to the example.

[Brief description of drawings]

1A to 1D are cross-sectional views showing an outline of a manufacturing process of a substrate evaluation element according to an embodiment of the present invention.

2A to 2C are cross-sectional views showing an outline of a manufacturing process of a substrate evaluation element according to an embodiment.

FIG. 3 is a plan view showing a state in the middle of manufacturing the substrate evaluation element according to the embodiment of the present invention.

FIG. 4 is a graph showing Id-Vg characteristics of the substrate evaluation element according to the example.

FIG. 5 is a graph showing Id-Vg characteristics of the substrate evaluation element according to the example.

FIG. 6 is a sectional view showing a conventional MOS capacitor as a substrate evaluation element.

[Explanation of symbols]

20 SOI substrate 21 Si support substrate 22 Embedded oxide film 23 Silicon layer 23a, 23b n-type diffusion layer 24 CVD oxide film 26 Interlayer insulating oxide film 26a, 26b, 26c contact holes 27 electrodes 28 electrodes 29 electrodes 30 MOS capacitor

Claims (6)

[Claims] 1. A substrate evaluation element for evaluating the insulating layer in a substrate having a silicon layer formed on the insulating layer, wherein the silicon layer on the substrate is separated into islands, and the island-shaped isolated silicon is formed. An element for evaluating a substrate, wherein an insulating film is formed on a layer surface, and at least three electrodes are connected to the island-shaped isolation silicon layer via a contact hole penetrating the insulating film. 2. An independent high-concentration impurity diffusion layer is formed in a predetermined region of the island-shaped isolation silicon layer to which at least two electrodes of the at least three electrodes are connected. 1. The element for evaluating a substrate according to 1. 3. The device for evaluating a substrate according to claim 1, wherein the separation of the island-shaped isolation silicon layer is a spatial separation by partially removing the silicon layer. 4. The substrate evaluation element according to claim 1 or 2, wherein the island-shaped isolation silicon layer is separated by interposing an insulating material. 5. A step of: (a) patterning the silicon layer on a substrate having a silicon layer formed on an insulating layer to separate the silicon layer into island shapes; and (b) forming an oxide film on the island silicon layer. Then, the step of patterning the oxide film so as to separate the island-shaped silicon layer into at least two regions (c) At least 2 by diffusing impurities into the island-shaped silicon layer using the oxide film as a mask. Forming two independent high-concentration impurity diffusion layer regions (d) removing the oxide film, and then forming an interlayer insulating oxide film (e) connecting to at least three different regions of the island-shaped isolation silicon layer And a step of forming electrodes on the contact holes, and a step of forming electrodes on the contact holes. 6. The substrate evaluation device according to claim 2,
At least two independent high-concentration impurity diffusion layer regions are regarded as sources and drains, island-shaped isolation silicon layer regions in which impurities are not diffused are regarded as bodies, and the insulating layer is regarded as a gate oxide film. A method for evaluating an SOI substrate, characterized in that the insulating layer is evaluated based on the above.