JP2003122557A - Sort circuit and sort method used for the circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sort circuit capable of shortening a time for notice to a main processor and a time for data comparison. SOLUTION: A shift amount calculation circuit 11 counts the bit number of '0' continued from the uppermost bit for parallel data a, and outputs shift amount data b. A comparison circuit 14 compares the magnitude of a shift amount temporarily held data c from a shift amount temporarily holding circuit 13 with that of a shift amount data b, and outputs a select signal d. A shift amount select circuit 12 selects the smaller one of the shift amount data b and the shift amount temporarily held data c by the select signal d, and outputs the selected data as shift amount selected data e. A shift amount latch circuit 15 latches the shift amount temporarily held data c by a shift amount latch pulse signal h from a shift amount timing generating circuit 16, and notifies the main processor 1 of shift amount latch data f.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sorting circuit and a sorting method used therein, and more particularly to a sorting circuit for detecting a maximum value in parallel data.

[0002]

2. Description of the Related Art Conventionally, in this type of sorting circuit,
Even if you just want to know whether the given data is large or small, the maximum value in the parallel data in the series of data groups is detected by comparing the parallel data itself regardless of the data bus width of the parallel data. ing.

[0003]

However, in the above-described conventional sorting circuit, when the bus width of the parallel data is larger than the data bus width of the main processor, the maximum value in the series of data groups is notified to the main processor. Since it is necessary to divide the data into two, it is difficult to notify in one processor cycle.

Further, in the conventional sort circuit, since the bit width for data comparison is required for the bus width of the parallel data, the data comparison time cannot be shortened when the bus width of the parallel data is large.

Therefore, an object of the present invention is to solve the above problems and to provide a sorting circuit and a sorting method used therefor which can speed up the notification time to the main processor and the data comparison time.

[0006]

A sorting circuit according to the present invention comprises a calculating means for calculating shift amount data by counting the number of consecutive "0" bits from the most significant bit for all series of parallel data. Comparing means for comparing the immediately preceding shift amount data with the shift amount data calculated by the calculating means each time the parallel data is inputted, and the parallel data is inputted according to the comparison result of the comparing means. Each of them is provided with notifying means for notifying one of the immediately preceding shift amount data and the shift amount data calculated by the calculating means to the higher-level device.

In the sorting method according to the present invention, the shift amount data is calculated by counting the number of consecutive "0" bits from the most significant bit for all the series of parallel data, and every time the parallel data is input. The calculated shift amount data and the shift amount data immediately before the calculation are compared with each other, and the shift amount data immediately before and the calculated shift amount data are input each time the parallel data is input according to the comparison result. One of them is notified to the host device.

That is, the sorting circuit according to the present invention detects the bit position which becomes "1" first from the most significant bit in all series of parallel data, and detects the bit position from the most significant bit to the bit position. By counting the number of consecutive "0" bits as shift amount data and comparing these shift amount data, the maximum value range detection in the parallel data group can be simply displayed. That is, it is possible to reduce the data notified as the maximum value range detection value.

More specifically, in the sorting circuit according to the present invention, the number of consecutive "0" bits from the most significant bit of the parallel data a is converted into the shift amount data b, and every time the parallel data a is input. The shift amount data b immediately before is compared with the converted shift amount data b, and the smaller shift amount data, that is, the larger parallel data a is held as the shift amount data, and this shift amount data is within the maximum value range. Notified as a detected value.

In the sorting circuit according to the present invention, by performing the above-described comparison operation within the maximum value range detection operation time, it is possible to detect the maximum value range in a series of parallel data groups.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a sorting circuit according to an embodiment of the present invention. In FIG. 1, the sorting circuit 1 includes a shift amount calculation circuit 11, a shift amount selection circuit 12, a shift amount temporary holding circuit 13, a comparison circuit 14, a shift amount latch circuit 15, and a shift amount timing generation circuit 16. Configured, main processor 2
Are connected.

The shift amount calculation circuit 11 detects the bit position which becomes "1" first from the most significant bit in the 16-bit parallel data a in the series of parallel data groups, and detects the bit from the most significant bit. The number of consecutive "0" bits up to the position is counted, and 5-bit shift amount data b is output.

The shift amount temporary holding circuit 13 holds the minimum value of the shift amount data at the present time and outputs the shift amount temporary holding data c. The shift amount timing generation circuit 16 has a shift amount clear pulse signal g for clearing the shift amount temporary holding data c of the immediately preceding parallel data group at the beginning of the maximum value range detecting operation, and a shift amount at the end of the maximum value range detecting operation. A shift amount latch pulse signal h for latching the temporarily held data c is generated and output.

The shift amount latch circuit 15 latches the shift amount temporary holding data c supplied from the shift amount temporary holding circuit 13 by the shift amount latch pulse signal h supplied from the shift amount timing generating circuit 16 and the shift amount latch data f. Notify the main processor 1.

The comparison circuit 14 is a shift amount temporary holding circuit 13.
The magnitude comparison between the shift amount temporary holding data c given by the shift amount and the shift amount data b given by the shift amount calculating circuit 11 is performed, and the select signal d is output. The shift amount selection circuit 12 shifts the shift amount data b given from the shift amount calculation circuit 11 and the shift amount temporary holding data c given from the shift amount temporary holding circuit 13 according to the select signal d given from the comparison circuit 14. The smaller amount is selected and output as shift amount selection data e.

FIG. 2 is a timing chart showing the operation of the sorting circuit 1 according to the embodiment of the present invention. These Figure 1
The operation of the sorting circuit 1 according to the embodiment of the present invention will be described with reference to FIG.

The shift amount calculation circuit 11 detects a bit position which is "1" first from the most significant bit in the 16-bit parallel data a in the series of parallel data groups, and detects the bit from the most significant bit. The number of consecutive "0" bits up to the position is counted, and 5-bit shift amount data b is output.

The comparison circuit 14 is the minimum value of the shift amount data b given from the shift amount calculating circuit 11 and the current shift amount data given from the shift amount temporary holding circuit 13 every time the parallel data a is inputted. The magnitude comparison is performed with the shift amount temporary holding data c, and the select signal d for selecting the smaller shift amount is output.

The shift amount selection circuit 12 responds to the select signal d given from the comparison circuit 14 with the minimum value of the shift amount data b given from the shift amount calculation circuit 11 and the current shift amount data given from the shift amount temporary holding circuit 13. One of the shift amount temporary holding data c which has the smaller shift amount is selected and output as shift amount selection data e.

The shift amount temporary holding circuit 13 temporarily holds the shift amount selection data e supplied from the shift amount selection circuit 12, and outputs the shift amount holding data c as the holding data. The shift amount timing generation circuit 16 generates a clear signal at the beginning of the maximum value range detection time in order to clear the shift amount temporary holding data c of the parallel data group within the immediately preceding maximum value range detection time, and outputs the clear signal. The clear pulse signal g is given to the shift amount temporary holding circuit 13.

Further, the shift amount timing generation circuit 16 generates a latch pulse signal at the end of the maximum value range detecting operation in order to hold the maximum value range of a series of parallel data groups within the maximum value range detection time, and Is given to the shift amount latch circuit 15 as a shift amount latch pulse signal h.

The shift amount latch circuit 15 latches the shift amount temporary holding data c given from the shift amount temporary holding circuit 13 by the shift amount latch pulse signal h given from the shift amount timing generating circuit 16 to obtain the maximum value range. The maximum value range of the parallel data group within the detection time is notified to the main processor 1 as the shift amount latch data f.

The operation of the sorting circuit 1 according to the embodiment of the present invention will be specifically described by using the output timing of the shift amount calculating circuit shown in FIG. FIG. 2 shows the timing when three types of 16-bit parallel data are input from the parallel data a and the maximum value range detection operation is performed on the three types of data from the beginning of the parallel data.

Since the shift amount temporary holding data c remains the data at the time of the previous maximum value range detection, it is cleared by the shift amount clear pulse g at the beginning of the maximum value range detection operation, and "10h" is output.

In the first parallel data "0010h", since the number of bits of "0" consecutive from the most significant bit is "11", the shift amount data b becomes "0Bh". The comparison circuit 14 compares the shift amount data b value “0Bh” with the shift amount temporary holding data c value “10h” and outputs the select signal d. As a result, “0Bh”, which is the shift amount data b value with the small shift amount, is output from the shift amount selection circuit 12 as the shift amount selection data e.

In the next parallel data "1000h", since the number of bits of "0" consecutive from the most significant bit is "3", the shift amount data b becomes "03h". Comparison circuit 1
Reference numeral 4 compares the shift amount data b value '03h' with the shift amount temporary holding data c value '0Bh' and outputs the select signal d. As a result, the shift amount data b value “03h” having a small shift amount is output from the shift amount selection circuit 12 as the shift amount selection data e.

In the next parallel data "0100h", the number of consecutive "0" s from the most significant bit is "7", so the shift amount data "b" is "07h". Comparison circuit 1
Reference numeral 4 compares the shift amount data b value of '07h' with the shift amount temporary holding data c value of '03h', and outputs the select signal d. As a result, the shift amount temporary holding data c value “03h” having a small shift amount is output from the shift amount selection circuit 12 as the shift amount selection data e.

The shift amount latch data f, which is the maximum value range of the parallel data group within the maximum value range detection time, is the clock CL in the section where the shift amount latch pulse signal h is "1".
'03h' is output by taking in the shift amount temporary holding data c value at the rising edge of K.

As described above, in this embodiment, the 16-bit parallel data "a" is first detected at the bit position which becomes "1", and the continuous "0" from the most significant bit to the bit position is detected. By converting the shift amount data b of 5 bits by counting the number of bits and comparing these shift amount data b with all the data in the data group, the maximum value range detection can be simplified. Can be done.

At this time, a series of parallel data a is compared by 16
Since it is performed on the data after the conversion from the bit data width to the 5-bit data width, the scale of data comparison for detecting the maximum value range of the parallel data a in the series of data groups within a fixed time is reduced. Therefore, the maximum value range can be easily detected.

In the embodiment of the present invention, the bit position which becomes "1" for the first time is detected for 16-bit parallel data a in a series of data groups within a fixed time, and the bit position is determined from the most significant bit. The comparison for counting the number of consecutive "0" bits up to and detecting the maximum value range in this 5-bit shift amount data has been described. Parallel data of a series of data groups and shift amount data after conversion have been described. There is no limitation on the data length in the bit width of.

Further, in one embodiment of the present invention, the comparison circuit 14
In the above, the magnitude comparison is performed between the shift amount data b and the shift amount temporary holding data c which is the minimum value of the shift amount data at the present time, and the maximum value range is detected by selecting the smaller shift amount. It is also possible to detect the minimum value range by selecting the one with the larger shift amount and setting the shift amount temporary holding data value to all “0” when the maximum value range detection operation is first cleared. .

Further, in connection with the description of the claims, the present invention can have the following aspects.

(1) The shift amount data is calculated by counting the number of consecutive "0" bits from the most significant bit for all series of parallel data, and is calculated every time the parallel data is input. The shift amount data immediately before the calculation and the shift amount data immediately before the calculation thereof are compared, and one of the shift amount data immediately before and the calculated shift amount data is placed in the higher order every time the parallel data is input according to the comparison result. Notify the device,
The shift amount data is calculated by detecting a bit position which becomes “1” first from the most significant bit in the parallel data and continuing “from the most significant bit to the bit position of the parallel data”. A sorting method characterized in that the number of bits of "0" is counted as shift amount data.

(2) In the comparison of the shift amount data, a selection signal designating the smaller one of the shift amount data is output as the comparison result, and the shift amount data selected by the selection signal is detected in the maximum value range. The sorting method described in (1) is characterized in that the value is notified.

(3) In the comparison of the shift amount data, a selection signal designating a larger one of the shift amount data is output as the comparison result, and the shift amount data selected by the selection signal is detected as a range of the minimum value. The sorting method according to (1) or (2), characterized in that the value is notified.

(4) Each time the parallel data is input according to the comparison result of the shift amount data, one of the immediately preceding shift amount data and the calculated shift amount data is held, and the held content is described above. The sorting method according to any one of (1) to (3), characterized in that the held contents are latched at a timing to notify the host device and notified to the host device.

(5) The sorting method according to (4), wherein the held contents are cleared when the shift amount data is calculated.

[0039]

As described above, according to the present invention, the shift amount data is calculated by counting the number of consecutive "0" bits from the most significant bit for all series of parallel data.
Each time parallel data is input, the calculated shift amount data is compared with the shift amount data immediately before the calculation, and according to the comparison result, the shift amount data immediately before is calculated each time the parallel data is input. By notifying one of the shift amount data and the shift amount data to the upper device, it is possible to shorten the notification time to the main processor and the data comparison time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a sorting circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the sorting circuit according to the embodiment of the present invention.

[Explanation of symbols]

1 sort circuit 2 main processor 11 Shift amount calculation circuit 12 Shift amount selection circuit 13 Shift amount temporary holding circuit 14 Comparison circuit 15 Shift amount latch circuit 16 shift amount timing generation circuit a parallel data b Shift amount data c Shift amount temporary holding data d Select signal e Shift amount selection data f Latch data for shift amount g Shift amount clear pulse signal h Shift amount latch pulse signal

Claims (7)

[Claims] 1. A calculation means for calculating the shift amount data by counting the number of consecutive "0" bits from the most significant bit for all the series of parallel data, and immediately before each input of the parallel data. Comparing means for comparing the shift amount data and the shift amount data calculated by the calculating means, and the shift amount data immediately before and the calculating means each time the parallel data is input according to the comparison result of the comparing means. And a notifying unit that notifies one of the shift amount data calculated in step 1 to a higher-level device. 2. The calculating means detects, for the parallel data, a bit position which is first “1” when viewed from the most significant bit, and the consecutive bits from the most significant bit to the bit position of the parallel data. 2. The sorting circuit according to claim 1, wherein the number of bits of "0" is counted as shift amount data. 3. The comparing means outputs a selection signal designating the smaller one of the shift amount data as the comparison result, and the notifying means outputs the shift amount data selected by the selection signal in a range of a maximum value. The sorting circuit according to claim 1 or 2, wherein notification is made as a detection value. 4. The comparing means outputs a selection signal designating a larger one of the shift amount data as the comparison result, and the notifying means outputs the shift amount data selected by the selection signal in a range of a minimum value. The sorting circuit according to any one of claims 1 to 3, wherein notification is made as a detection value. 5. Holding means for holding one of the immediately preceding shift amount data and the shift amount data calculated by the calculating means each time the parallel data is input according to the comparison result of the comparing means, Means for notifying the notifying means of the timing at which the contents held by the holding means should be notified to the upper device, and the notifying means latches the shift amount data held in the holding device at the timing and notifies the upper device. The sorting circuit according to any one of claims 1 to 4, wherein notification is made. 6. The sorting circuit according to claim 5, further comprising means for clearing the contents held by the holding means when the shift amount data is calculated by the calculating means. 7. A shift amount data is calculated by counting the number of consecutive "0" bits from the most significant bit for all series of parallel data, and the shift amount data is calculated every time the parallel data is input. The shift amount data is compared with the shift amount data immediately before the calculation, and every time the parallel data is input according to the comparison result, one of the immediately preceding shift amount data and the calculated shift amount data is set to a higher-level device. A sorting method characterized by being notified to.