CN116263865A - Signal average value calculating device and method thereof - Google Patents
Signal average value calculating device and method thereof Download PDFInfo
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Abstract
The present disclosure provides a signal average value calculating apparatus and method thereof, which receives input data using a first shift register, stores the input data into the first shift register in an effective level state of an input indication signal, and shifts stored high-order data to low-order bit by bit according to an effective edge of a clock signal, and outputs the high-order data as first output data; and then the adder is utilized to circularly accumulate the first output data and the generated addition output data until the pulse count value of the clock signal reaches the target data bit width, and the second output data synchronously output by the second shift register is the signal average value of the input data, so that the hardware cost can be effectively reduced while the average value operation is realized through multiple accumulation operations, the effect of fully utilizing hardware resources is achieved, and the power consumption is reduced.
Description
Technical Field
The disclosure relates to the technical field of signal processing, in particular to a signal average value calculation device and a signal average value calculation method.
Background
Discrete signal monitoring, especially temperature monitoring, usually requires multiple measurements to average to reduce errors and improve accuracy, while most of current temperature sensor chips support the function of internal integration of multiple measurements to average, and the average cardinality is typically the power of 2 to N. The data averaging based on the nth power of 2 may be reduced to the operation of truncating the lower N bits after the accumulated summation of the nth power of 2 data. How to implement the accumulation operation is therefore the core of the data averaging operation based on the power of 2. In general, the accumulation operation can be implemented in two ways, one is implemented in a way that the addition is completed by a plurality of multi-bit full adders after all the added data are ready; the other is that the data are generated sequentially, and the accumulation operation is completed sequentially by multiplexing the same multi-bit full adder.
As shown in FIG. 1, all the added Data data_in1 to data_in2 N After all the data are ready, the data averaging operation based on the power of N of 2 can be realized by the operation mode of cutting off the lower N bits after the addition of the plurality of multi-bit adders 101. In another manner shown in fig. 2, an operation manner of cutting off the lower N bits after completing the accumulation operation in a pipeline-like manner is adopted, and a data averaging operation based on the power of N of 2 can also be implemented. Specifically, at the rising edge of each clock signal Clk, the input Data data_rdy is stored in the input register 201 and supplied to the input terminal of the multi-bit adder 202, and the multi-bit adder 202 performs the addition operation. On the next rising edge of the clock signal Clk, the counter 203 and the output register 204 detect the arrival of the input data data_rdy signal, the output register 204 completes updating, and at the same time, the counter 203 determines whether the count target 2 is reached N-1 If the count target 2 is not reached N-1 Counter 203 completes the add 1 operation and waits for the arrival of the next data_rdy signal; if the counting target 2 is reached N-1 The calculation completion signal cal_ok is output and the counter 203 is cleared, signaling the end of this operation, the signal schematic being shown in fig. 3.
The first method uses a plurality of multi-bit adders 101, and the second method also uses at least 1 multi-bit adder 202. For the application cases of relatively slow data generation rate, such as a temperature sensor chip, with relatively long data interval and sufficient data processing time, the hardware cost of the two implementations is relatively high.
Disclosure of Invention
In order to solve the above technical problems, the present disclosure provides a signal average value calculating device and a method thereof.
In one aspect, the present disclosure provides a signal average value calculation apparatus, including:
the shift control module is used for setting and outputting a shift enabling signal in response to the effective level of the input indication signal, counting the pulse of the clock signal, maintaining the current value of the clock signal when the count value reaches a preset value and clearing the shift enabling signal;
a first shift register for receiving input data according to a clock signal, storing the input data in the first shift register in an active level state of the input indication signal, shifting the stored high-order data to low-order bits bit by bit according to an active edge of the clock signal in an active level state of a shift enable signal, and outputting the high-order data as first output data;
an adder having a first input coupled to the first output data, a second input coupled to the second output data, and a first output providing the added output data;
a second shift register which writes the aforementioned addition output data bit by bit at the active edge of the clock signal, takes the accumulated addition output data as the aforementioned second output data in the active level state of the shift enable signal, and latches its output in the inactive level state of the shift enable signal,
the shift control module responds to the count value of the clock signal pulse reaching the preset value in the period of inputting the effective level of the indication signal, and the data synchronously output by the second shift register is the signal average value of the input data.
Further, the frequency of the clock signal is positively correlated with the signal frequency of the input indication signal and with the target data bit width of the output data.
Further, the shift control module includes:
the detection unit is used for determining a target data bit width according to the data bit width of input data and a preset target sampling number for taking an average value, and determining a target value for accumulation counting according to the target sampling number, wherein the target sampling number is an integer power of 2;
a first counter which sets and outputs a shift enable signal in response to an active level of an input instruction signal, counts clock signal pulses, and holds a current value thereof and clears the shift enable signal when a count value reaches the target data bit width;
and a second counter for counting the pulses of the input indication signal according to the clock signal, outputting a calculation completion flag signal when the count value reaches the target value, and resetting the second counter.
The preset value includes a target data bit width and a target value of accumulated count.
Further, the signal average value calculating apparatus further includes:
and a control unit for determining the frequency of the clock signal according to the frequency of the input indication signal, the data bit width of the input data, and the target sampling number.
Further, the first shift register includes:
the data signal input end is used for accessing the output data;
a shift enable input connected to the shift control module for accessing a shift enable signal;
the latch signal input end is used for accessing the output indication signal;
the clock signal input end is used for accessing a clock signal;
a one-bit signal output terminal for providing the first output data,
and, the first shift register latches the stored data and keeps its output state unchanged during a period in which both the shift enable signal and the input indication signal are inactive levels.
Further, the signal average value calculating apparatus further includes:
and the first carry register is connected with the adder, is used for maintaining the last bit data state of the adder and is provided to the adder on the next effective edge of the clock signal.
Further, the target data bit width is:
B1＝[log 2 (N+P-1)]+1 (2)
wherein B1 is the target data bit width, P is the data bit width of the input data, N is the index value of the target sampling number, and log 2 (N+P-1) is not an integer.
Further, the target data bit width is:
B1＝[log 2 (N+P-1)] (3)
wherein B1 is the target data bit width, P is the data bit width of the input data, N is the index value of the target sampling number, and log 2 (N+P-1) is an integer.
Further, the active level state of the input indication signal and/or the shift enable signal is a high level state, the inactive level state is a low level state, and the active edge of the clock signal is a rising edge.
Further, the first counter is an addition counter which sets and outputs a shift enable signal after a zero clearing operation in response to an active level of an input instruction signal, and counts up clock signal pulses, and maintains a current value thereof and clears the shift enable signal when a count value reaches the target data bit width,
alternatively, the aforementioned first counter is a down counter that sets and outputs the shift enable signal in response to the active level of the input instruction signal, and counts down the clock signal pulses, and holds its current value and clears the shift enable signal when the count value is reduced from the aforementioned target data bit width to zero.
On the other hand, the disclosure also provides a signal average value calculation method, which comprises the following steps:
setting and outputting a shift enable signal in response to an active level of an input indication signal, counting pulses of the clock signal, and maintaining a current value thereof and clearing the shift enable signal when the count value reaches a preset value;
receiving input data, storing the input data into a first shift register in an effective level state of an input indication signal, shifting stored high-order data into low-order data bit by bit according to an effective edge of a clock signal in an effective level state of a shift enable signal, and outputting the high-order data as first output data;
circularly accessing the second output data and the first output data, and generating addition output data after accumulation until the pulse count value of the input indication signal reaches a preset value;
writing the added output data into a second shift register bit by bit at the active edge of the clock signal, taking the added output data after accumulation as the second output data in the active level state of the shift enable signal, latching the output of the second shift register in the inactive level state of the shift enable signal,
the preset value characterizes the target data bit width of the output data of the signal average value calculation device, and the data synchronously output by the second shift register is the signal average value of the input data in response to the count value of the clock signal pulse reaching the preset value during the period of the effective level of the input indication signal.
Further, the frequency of the clock signal is positively correlated with the signal frequency of the input indication signal and with the target data bit width of the output data.
Further, before the step of setting and outputting the shift enable signal in response to the active level of the input indication signal, the signal average value calculating method further includes:
determining a target data bit width according to the data bit width of the input data and a preset target sampling number for averaging, determining a target value for accumulation counting according to the target sampling number,
wherein the target sampling number is an integer power of 2, and the preset value comprises a target data bit width and a target value of accumulated count.
Further, the step of setting and outputting the shift enable signal in response to the active level of the input indication signal, counting the pulses of the clock signal, and maintaining the current value thereof and clearing the shift enable signal when the counted value reaches a preset value, includes:
setting and outputting a shift enable signal by using a first counter in response to an active level of an input indication signal, counting clock signal pulses by using the first counter, and maintaining a current value thereof and clearing the shift enable signal when a count value reaches a target data bit width;
according to the clock signal, the second counter counts the pulse of the input indication signal, and outputs a calculation completion flag signal when the count value reaches the target value, and clears the second counter.
Further, before the step of setting and outputting the shift enable signal in response to the active level of the input indication signal, the signal average value calculating method further includes:
the frequency of the clock signal is determined according to the frequency of the input indication signal, the data bit width of the input data, and the target number of samples.
Further, the active level state of the input indication signal and/or the shift enable signal is a high level state, the inactive level state is a low level state, and the active edge of the clock signal is a rising edge.
The signal average value calculating device and the signal average value calculating method can respond to the effective level of an input indication signal by utilizing a shift control module, set and output a shift enabling signal, count the pulse of a clock signal, keep the current value of the clock signal when the count value reaches a preset value and clear the shift enabling signal; receiving input data through a first shift register, storing the input data into the first shift register in an effective level state of an input indication signal, shifting stored high-order data into low-order data bit by bit according to an effective edge of a clock signal in an effective level state of a shift enable signal, and outputting the high-order data as first output data; then the adder is utilized to circularly access the second output data and the first output data, and the added output data is generated after the addition until the count value reaches the preset value; meanwhile, the second shift register writes addition output data bit by bit along the effective edge of the clock signal, and takes the accumulated addition output data as the second output data in the effective level state of the shift enabling signal, and the shift control module responds to the count value of the clock signal pulse reaching a preset value in the period of inputting the effective level of the indicating signal, and the data synchronously output by the second shift register is the signal average value of the input data.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.
FIG. 1 is a schematic diagram showing a signal average value calculating device in the prior art;
FIG. 2 is a schematic diagram showing another signal average value calculating device in the prior art;
FIG. 3 is a schematic waveform diagram showing signals in the signal average value calculating apparatus shown in FIG. 2;
fig. 4 is a schematic diagram illustrating a structure of a signal average value calculating apparatus according to an embodiment of the present disclosure;
FIG. 5a is a schematic diagram showing the structure of a control unit in the signal average value calculating apparatus shown in FIG. 4;
fig. 5b and 5c are schematic diagrams respectively showing a circuit structure of a shift control module in the signal average value calculating device shown in fig. 4 and a working model thereof;
FIG. 6 is a schematic diagram showing waveforms of the respective input/output signals of the N+P bit cyclic shift register 302 in the apparatus shown in FIG. 4;
fig. 7 is a flowchart showing a method of calculating the signal average value by the signal average value calculating apparatus shown in fig. 4.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
The present disclosure is described in detail below with reference to the accompanying drawings.
Fig. 4 is a schematic structural diagram of a signal average value calculating device according to an embodiment of the present disclosure, fig. 5a is a schematic structural diagram of a control unit in the signal average value calculating device shown in fig. 4, and fig. 5b and fig. 5c are schematic circuit structures and operation models of a shift control module in the signal average value calculating device shown in fig. 4, respectively.
Referring to fig. 4 to 5c, an embodiment of the present disclosure provides a signal average value calculating apparatus 300, which includes:
a shift control module 310, wherein the shift control module 310 can set and output a shift enable signal Sen (e.g. switch to a high state) in response to the active level of the input indication signal data_rdy, and count the pulses of the clock signal clk, and maintain the current value thereof and clear the shift enable signal Sen (e.g. switch to a low state) when the count value reaches a preset value;
a first shift register 320 for receiving the input Data data_in according to the clock signal clk, storing the input Data data_rdy in the first shift register 320 in an active level state of the input indication signal data_rdy, and shifting the stored high-order Data to the low-order Data bit by bit according to an active edge (rising edge, next same) of the clock signal clk in an active level state of the shift enable signal Sen, and outputting the high-order Data as the first output Data;
an adder 330, the adder 330 having a first input b connected to the first output data, a second input a connected to the second output data, and a first output out providing the added output data;
a second shift register 350 for writing the addition output data bit by bit on the active edge of the clock signal clk, for latching the output of the addition output data after accumulation as the second output data in the active level state of the shift enable signal Sen, and in the inactive level state of the shift enable signal Sen,
the predetermined value characterizes the target Data bit width B1 of the output Data out_i, and the shift control module 310 responds to the count value of the clock signal clk pulse reaching the predetermined value during the period of inputting the active level of the indication signal data_rdy, and the Data out_i synchronously output by the second shift register 350 is the signal average value of the input Data data_in.
As can be seen, at 2 N The digital averaging operation for the base number can be realized by an accumulation operation and a bit cutting mode. The implementation of the accumulation operation in a multi-bit full adder cascade is relatively straightforward and easy to understand, but the hardware resources are not fully utilized. The embodiment of the disclosure redesigns the addition execution process of the averaging operation based on the idea of time division multiplexing, more fully utilizes hardware resources and reduces hardware overhead.
Further, in the present embodiment, the frequency of the clock signal clk is positively correlated with the signal frequency of the input indication signal data_rdy and with the target Data bit width B1 of the output Data out_i. Specifically, as shown in fig. 5a, for example, the signal average value calculating apparatus 300 further includes: a control unit 360 for controllingThe unit 360 is used for inputting the Data bit width P of the Data data_in, and the target sampling number 2 according to the frequency of the indication signal data_rdy N To determine the frequency of the clock signal clk:
fclk≥(N+P)*fs (1)
where fclk is the frequency of the clock signal clk, and fs is the frequency of the input indication signal data_rdy.
Further, in the present embodiment, the shift control module 310 is designed by means of nested accumulation counting, and its main function is to generate the shift enable signal Sen. Specifically, referring to fig. 5b, the shift control module 310 includes:
a detection unit 311, the detection unit 311 being configured to determine an average value of the target sample number 2 based on the Data bit width P of the input Data data_in and a predetermined average value N Determining the target data bit width B1 (according to the accumulated counter principle, in order to make the count value not smaller than N+P-1, 2 can be obtained B1 Gtoreq n=p-1) according to the target sample number 2 N Determining a target value 2 for the accumulated count N -1, the target number of samples being an integer power of 2;
a first counter 312, the first counter 312 setting and outputting a shift enable signal Sen in response to an active level of the input indication signal data_rdy, and counting clock signal clk pulses, and maintaining a current value thereof and clearing the shift enable signal Sen when a count value reaches a target Data bit width B1;
a second counter 313 for counting the pulses of the input indication signal data_rdy according to the clock signal clk and for reaching the target value 2 when the counted value thereof N -1, i.e. the second counter 313 has a data bit width of N, outputting a calculation completion flag signal cal_ok while clearing the second counter 313.
Wherein the predetermined value includes the target data bit width B1 and the accumulated count target value 2 N -1. As can be seen from the principle of the accumulation counter, in order to make the count value of the first counter 312 not smaller than N+P-1, 2 can be obtained B1 Not less than N+P-1, and thus, the aforementioned target dataThe bit width B1 is at least:
B1＝[log2(N+P-1)]+1 (2)
wherein B1 is a target Data bit width B1, P is a Data bit width of the input Data data_in, N is an exponent value of the target number of samples, and log2 (N+P-1) is not an integer.
In an alternative embodiment, the target data bit width B1 is at least:
B1＝[log2(N+P-1)] (3)
wherein B1 is a target Data bit width B1, P is a Data bit width of the input Data data_in, N is an exponent value of the target number of samples, and log2 (N+P-1) is an integer.
Specifically, the workflow of the shift control module 310 is understood in conjunction with fig. 4-5 c:
when the Data is ready, i.e. the input indication signal data_rdy (e.g. high level) arrives, the first counter 312 completes the zero clearing operation and sets the shift enable signal Sen, and when the rising edge of each working clock signal clk arrives, the first counter 312 determines whether the count value thereof reaches the target n+p-1, and if not, the first counter 312 completes the 1 adding operation; if the target is reached, the current value is maintained and the shift enable signal Sen is cleared, while the second counter 313 determines whether the count value reaches target 2 N -1, outputting a calculation completion flag signal cal_ok if the target is reached, while the second counter 313 is cleared, and completing the add 1 operation if the target is not reached.
Further, referring to fig. 4, in the present embodiment, the first shift register 320 includes:
data signal input terminal P IN The input Data data_in for accessing the P bits;
shift enable input S en The shift enable input S en The shift control module 310 is connected to the shift enable signal Sen;
latch signal input terminal I en For accessing the input indication signal data_rdy;
the clock signal input end clk is used for accessing the clock signal clk;
a one-bit signal output terminal Q for providing the first output data,
wherein, during the period that the shift enable signal Sen and the input indication signal data_rdy are both inactive levels, the first shift register 320 latches the storage Data and keeps the output terminal state thereof unchanged.
Specifically, the input Data data_in corresponding to the Data bit width P corresponds to the sampling base 2 in the process of detecting and calculating the signal average value N This requires the first shift register 320 to be an n+p bit cyclic shift register, and the specific workflow is as follows: when the input indication signal data_rdy is active (i.e., high state), the first shift register 320 of n+p bits stores the P-bit input Data data_in into an internal n+p-bit register, the lower P bits of the register store the P-bit input Data data_in, and the remaining upper N bits store the highest bits of the P-bit input Data data_in. When the shift enable signal Sen is active (i.e., in a high level state), the n+p-bit register shifts from low to high bit by bit according to an active edge (e.g., a rising edge) of the clock signal Clk, and the most significant register data is sent to the least significant register, and is output through the output terminal Q as the first output data. When the shift enable signal Sen and the input indication signal data_rdy are both inactive (i.e. low state), the internal n+p-bit register and the output terminal Q remain unchanged, and the waveform of the Data shift is shown in fig. 6.
Further, referring to fig. 4, in the present embodiment, the signal average value calculating apparatus 300 further includes: a first carry register 340, the first carry register 340 being coupled to the second input co of the adder 330 for maintaining the last bit data state of the adder 330 and being provided to the third input ci of the adder 330 at the next active edge of the clock signal clk.
In this embodiment, the second shift register 350 includes:
data signal input terminal I IN The first input data is used for accessing one bit;
shift enable input S en The shift enable input terminalS en The shift control module 310 is connected to the shift enable signal Sen;
the clock signal input end clk is used for accessing the clock signal clk;
a bit signal output terminal Q for providing the second output data.
Specifically, the second shift register 350 is also an n+p-bit cyclic shift register, which is shifted from low to high according to the active edge (rising edge) of the clock signal Clk when the shift enable signal Sen is active (i.e., high state), and one bit of the first input data is stored in the lowest data register, and the highest data is output through the output terminal Q to the second output data, similar to the first shift register 320. When the shift enable signal Sen is inactive, the states of the internal P-bit register and the output terminal Q remain unchanged.
Further, in the present embodiment, the active level state of the input indication signal data_rdy and/or the shift enable signal Sen is a high level state, the inactive level state is a low level state, and the active edge of the clock signal clk is a rising edge.
In an alternative embodiment, the active level states of the input indication signal data_rdy and the shift enable signal Sen may be low, the inactive level state thereof may be high, and the active edge of the clock signal clk may be a falling edge.
Further, in the present embodiment, the first counter 312 is an addition counter, the first counter 312 sets and outputs the shift enable signal Sen after the zero clearing operation in response to the active level of the input indication signal data_rdy, and counts up the clock signal clk pulse, and maintains its current value and clears the shift enable signal Sen when the count value reaches the target Data bit width B1,
alternatively, in an alternative embodiment, the first counter 312 may be a down counter, and the first counter 312 may set and output the shift enable signal Sen in response to the active level of the input indication signal data_rdy, and count down the clock signal clk pulse, and maintain its current value and clear the shift enable signal Sen when the count value is reduced from the target Data bit width B1 to zero.
In combination with the foregoing, for the signal average value calculation apparatus 300 provided in the embodiment of the present disclosure, it realizes 2 N The specific working principle of numerical averaging for cardinality is as follows:
when the Data is ready, i.e., the valid edge of the first clock signal Clk after the arrival of the input indication signal data_rdy, the first shift register 320 of n+p bits stores the input Data data_in of P bits into the internal n+p-bit register, the lower P bits of the register store the input Data data_in of P bits, and the remaining upper N bits store the highest bits of the input Data data_in of P bits, while the first counter 312 in the shift control module 310 completes the zero clearing operation and sets the shift enable signal Sen. On the next active edge of the (n+p) clock signals Clk, the first shift register 320 of n+p bits is shifted bit by bit cyclically, and the second shift register 350 of n+p bits is shifted bit by bit. At the active edge of the (n+p+1) -th clock signal Clk, the shift control module 310 resets the shift enable signal Sen, the first counter 312 inside thereof stops adding 1, and the second counter 313 completes the adding 1 operation. When the pulse number of the input indication signal data_rdy reaches 2 N And the shift calculation ends, i.e., the count value of the second counter 313 reaches the target value 2 N -1, immediately the second counter 313 is cleared, and a calculation completion flag signal cal_ok is outputted to indicate that the averaging operation is completed, and the Data out_i synchronously outputted from the second shift register 350 is the signal average value of the averaging operation for detecting the input Data data_in.
From the above, 2 N The core idea of the multi-bit data averaging operation is a plurality of accumulation operations, the operation bit number of each addition is completely consistent with the structure, and each addition operation is only related to the current storage result and the input data. While the multi-bit adder circuit structure in the prior art has a large hardware overhead and insufficient utilization of hardware resources, the signal average value calculating device 300 provided in the embodiment of the present disclosure operates by setting the working frequency of the appropriate clock signal clk based on the idea of time division multiplexingThe addition circuit with as few addition circuits as possible is assisted by the shift register, so that the multi-accumulation operation is completely realized, and the purposes of reducing hardware cost and fully utilizing hardware resources are achieved.
Fig. 7 is a flowchart showing a method of calculating the signal average value by the signal average value calculating apparatus shown in fig. 4.
The embodiment of the disclosure also provides a signal average value calculating method, which is based on the signal average value calculating device 300 provided in the foregoing embodiment, and by setting the working frequency of the appropriate clock signal clk, multiple accumulation operations in the prior art can be realized by using as few hardware resources as possible, and the operation of calculating the average value of the bit data is performed, so that the hardware cost is greatly reduced, and the energy consumption is reduced. Referring to fig. 7, the signal average value calculation method includes the steps of:
step S110: in response to the active level of the input indication signal, a shift enable signal is set and output, and pulses of the clock signal are counted, and when the count value reaches a preset value, the current value is maintained and the shift enable signal is cleared.
In step S110, in combination with the foregoing embodiment, the frequency of the clock signal clk is positively correlated with the signal frequency of the input indication signal data_rdy and is positively correlated with the target Data bit width B1 of the output Data out_i, and the predetermined value characterizes the target Data bit width B1 of the input Data data_in for signal sampling.
Further, before the step of setting and outputting the shift enable signal in response to the active level of the input indication signal, the signal average value calculating method further includes:
according to the frequency of the input indication signal data_rdy, the Data bit width P of the input Data data_in and the target sampling number 2 N The frequency of the clock signal clk is determined.
Further, before the step of setting and outputting the shift enable signal in response to the active level of the input indication signal, the signal average value calculating method further includes:
according to the Data bit width P of the input Data data_in and preset calculationAverage target sample number 2 N Determining the target data bit width B1 and based on the target sample number 2 N Determining a target value 2 for the accumulated count N -1，
Wherein the target sampling number is 2 N The predetermined value includes the target data bit width B1 and the target value 2 of the accumulated count N -1。
Further, the step of setting and outputting the shift enable signal in response to the active level of the input indication signal, counting pulses of the clock signal, and maintaining the current value thereof and clearing the shift enable signal when the counted value reaches a preset value, includes:
setting and outputting the shift enable signal Sen with a first counter 312 in response to the active level of the input indication signal data_rdy, and counting the clock signal clk pulse with the first counter 312, and maintaining the current value thereof and clearing the shift enable signal Sen when the count value thereof reaches the target Data bit width B1; and
counting the pulses of the input indication signal data_rdy by a second counter 313 according to the clock signal clk, and reaching the target value 2 when the count value thereof N At-1 (i.e., the data bit width of the second counter 313 is N), the calculation completion flag signal cal_ok is output while the second counter 313 is cleared.
Step S120: and in the effective level state of the shift enable signal, the stored high-order data is shifted to low-order bits bit by bit according to the effective edge of the clock signal, and the high-order data is output as first output data.
Step S130: and circularly accessing the second output data and the first output data, and generating addition output data after accumulation until the count value reaches a preset value.
Step S140: writing the added output data into a second shift register bit by bit at the effective edge of the clock signal, taking the added output data after accumulation as the second output data in the effective level state of the shift enable signal, and latching the output of the second shift register in the invalid level state of the shift enable signal.
During the period of the active level of the input indication signal data_rdy, the second output Data synchronously output by the second shift register 350 is the signal average value of the input Data data_in in response to the count value of the clock signal clk pulse reaching the preset value.
Further, in the present embodiment, the active level state of the input indication signal data_rdy and/or the shift enable signal Sen is a high level state, the inactive level state is a low level state, and the active edge of the clock signal clk is a rising edge.
The embodiments disclosed in the disclosure are based on the concept of time-sharing multiplexing, and by setting a suitable clock signal frequency, the addition circuit with as few operations as possible is assisted by the shift register to completely realize multiple accumulation operations.
It should be noted that in the description of the present disclosure, it should be understood that the terms "upper," "lower," "inner," and the like indicate an orientation or a positional relationship, and are merely for convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.
Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it is apparent that the above examples are merely illustrative of the present disclosure and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present disclosure.
Claims (16)
1. A signal average value calculation apparatus, comprising:
the shift control module is used for setting and outputting a shift enabling signal in response to the effective level of the input indication signal, counting the pulse of the clock signal, maintaining the current value of the clock signal when the count value reaches a preset value, and clearing the shift enabling signal;
a first shift register for receiving input data according to the clock signal and storing the input data in an active level state of the input indication signal, and shifting stored high-order data to low-order bits according to an active edge of the clock signal in an active level state of the shift enable signal and outputting the high-order data as first output data;
an adder having a first input coupled to the first output data, a second input coupled to the second output data, and a first output providing an added output data;
a second shift register writing the addition output data bit by bit at a valid edge of the clock signal, and in a valid level state of the shift enable signal, taking the accumulated addition output data as the second output data, and latching its output in an invalid level state of the shift enable signal,
the shift control module responds to the count value of the clock signal pulse reaching the preset value in the period of the effective level of the input indication signal, and the data synchronously output by the second shift register is the signal average value of the input data.
2. The signal average value calculation apparatus according to claim 1, wherein the frequency of the clock signal is positively correlated with the signal frequency of the input instruction signal and with the target data bit width of the output data.
3. The signal average value calculation apparatus according to claim 2, wherein the shift control module includes:
the detection unit is used for determining the target data bit width according to the data bit width of the input data and a preset target sampling number for calculating an average value, and determining a target value for accumulation counting according to the target sampling number, wherein the target sampling number is an integer power of 2;
a first counter which sets and outputs the shift enable signal in response to an active level of the input indication signal, counts the clock signal pulses, and holds a current value thereof and clears the shift enable signal when a count value reaches the target data bit width;
a second counter for counting the pulses of the input indication signal according to the clock signal, outputting a calculation completion flag signal when the count value reaches the target value, and simultaneously resetting the second counter,
wherein the preset value includes the target data bit width and the target value of the accumulated count.
4. The signal average value calculation apparatus according to claim 3, further comprising:
and the control unit is used for determining the frequency of the clock signal according to the frequency of the input indicating signal, the data bit width of the input data and the target sampling number.
5. The signal average value calculation apparatus according to claim 4, wherein the first shift register includes:
the data signal input end is used for accessing the output data;
the shift enabling input end is connected with the shift control module and used for accessing the shift enabling signal;
the latch signal input end is used for accessing the output indication signal;
the clock signal input end is used for accessing the clock signal;
a one-bit signal output for providing said first output data,
and, during the period that the shift enable signal and the input indication signal are both inactive levels, the first shift register latches its stored data and keeps its output state unchanged.
6. The signal average value calculation apparatus according to claim 5, further comprising:
and the first carry register is connected with the adder and used for maintaining the last bit data state of the adder and providing the last bit data state to the adder on the next effective edge of the clock signal.
7. The signal average value calculation apparatus according to claim 6, wherein the target data bit width is:
B1＝[log 2 (N+P-1)]+1 (2)
wherein B1 is the target data bit width, P is the data bit width of the input data, N is the exponent value of the target sample number, and log 2 (N+P-1) is notAn integer.
8. The signal average value calculation apparatus according to claim 6, wherein the target data bit width is:
B1＝[log 2 (N+P-1)] (3)
wherein B1 is the target data bit width, P is the data bit width of the input data, N is the exponent value of the target sample number, and log 2 (N+P-1) is an integer.
9. The signal average value calculation apparatus according to claim 6, wherein an active level state of the input instruction signal and/or the shift enable signal is a high level state, an inactive level state thereof is a low level state, and an active edge of the clock signal is a rising edge.
10. The signal average value calculation apparatus according to claim 3 wherein said first counter is an addition counter which sets and outputs said shift enable signal after a clear operation in response to an active level of said input indication signal, and counts up said clock signal pulses and holds its current value and clears said shift enable signal when a count value reaches said target data bit width,
alternatively, the first counter is a down counter that sets and outputs the shift enable signal in response to an active level of the input indication signal, and counts down the clock signal pulses and holds its current value and clears the shift enable signal when a count value is reduced from the target data bit width to zero.
11. A signal average value calculation method, comprising:
setting and outputting a shift enable signal in response to an active level of an input indication signal, counting pulses of a clock signal, and maintaining a current value of the count value and clearing the shift enable signal when the count value reaches a preset value;
receiving input data, storing the input data into a first shift register in an effective level state of the input indication signal, shifting stored high-order data into low-order data bit by bit according to an effective edge of the clock signal in an effective level state of the shift enable signal, and outputting the high-order data as first output data;
circularly accessing second output data and the first output data, and generating addition output data after accumulation until the pulse count value of the input indication signal reaches a preset value;
writing the addition output data into a second shift register bit by bit at the active edge of the clock signal, taking the accumulated addition output data as the second output data in the active level state of the shift enable signal, latching the output of the second shift register in the inactive level state of the shift enable signal,
the preset value characterizes a target data bit width of output data of the signal average value computing device according to any one of claims 1 to 10, and during the effective level of the input indication signal, the data synchronously output by the second shift register is the signal average value of the input data in response to the count value of the clock signal pulse reaching the preset value.
12. The signal average value calculation method according to claim 11, wherein the frequency of the clock signal is positively correlated with the signal frequency of the input indication signal and with the target data bit width of the output data.
13. The signal average value calculation method according to claim 11, characterized in that before the step of setting and outputting a shift enable signal in response to an active level of an input instruction signal, the signal average value calculation method further comprises:
determining the target data bit width according to the data bit width of the input data and a preset target sampling number for calculating an average value, determining a target value for accumulating and counting according to the target sampling number,
wherein the target sampling number is an integer power of 2, and the preset value includes the target data bit width and the target value of the accumulated count.
14. The signal average value calculating method according to claim 13, wherein the steps of setting and outputting a shift enable signal in response to an active level of the input indication signal, counting pulses of the clock signal, and maintaining a current value thereof and clearing the shift enable signal when the count value reaches a preset value, include:
setting and outputting the shift enable signal with a first counter in response to an active level of the input indication signal, counting the clock signal pulses with the first counter, and maintaining a current value thereof and clearing the shift enable signal when a count value reaches the target data bit width;
and counting the pulses of the input indication signal by using a second counter according to the clock signal, outputting a calculation completion flag signal when the count value reaches the target value, and resetting the second counter.
15. The signal average value calculation method according to claim 13, characterized in that before the step of setting and outputting a shift enable signal in response to an active level of an input instruction signal, the signal average value calculation method further comprises:
the frequency of the clock signal is determined according to the frequency of the input indication signal, the data bit width of the input data, and the target sample number.
16. The signal average value calculation method according to claim 15, wherein the active level state of the input instruction signal and/or the shift enable signal is a high level state, the inactive level state thereof is a low level state, and the active edge of the clock signal is a rising edge.
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