JP2003115556A - Printed wiring board and semiconductor manufacturing method using the same - Google Patents
Printed wiring board and semiconductor manufacturing method using the sameInfo
- Publication number
- JP2003115556A JP2003115556A JP2001309632A JP2001309632A JP2003115556A JP 2003115556 A JP2003115556 A JP 2003115556A JP 2001309632 A JP2001309632 A JP 2001309632A JP 2001309632 A JP2001309632 A JP 2001309632A JP 2003115556 A JP2003115556 A JP 2003115556A
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- pattern
- wiring board
- printed wiring
- common wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、プリント配線基板
およびこれを用いた半導体製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board and a semiconductor manufacturing method using the same.
【０００２】[0002]
【従来の技術】従来、プリント配線基板にＡｕ線ワイヤ
ボンディングする場合、必要配線パターンは、ボンディ
ングの信頼性確保のためにＡｕめっきを行う必要があ
る。2. Description of the Related Art Conventionally, when Au wire wire bonding is performed on a printed wiring board, a necessary wiring pattern needs to be plated with Au in order to secure reliability of bonding.
【０００３】Ａｕめっきを電解めっき法によって行う場
合、プリント配線基板には電気的に全て繋がった導通パ
ターン部を形成しなければならないため、各必要配線パ
ターンを共通配線パターンで接続している。導通パター
ン部の形成後に電気的に非導通にする必要がある場所に
ついては、導通パターン部のうち不必要な部分である共
通配線パターンをめっき後にパンチ孔で打ち抜くことが
行われている。また、共通配線パターンの長手方向を、
基板の切断方向に交差する方向（通常は切断方向に直交
する方向であって必要配線パターンに平行な方向）にし
て配置しておき、半導体チップの接続後にこれを切断す
ることも行われている。When the Au plating is performed by the electroplating method, it is necessary to form a conductive pattern portion that is electrically connected to the printed wiring board, so that the necessary wiring patterns are connected by a common wiring pattern. In places where it is necessary to make electrically non-conductive after forming the conductive pattern portion, a common wiring pattern, which is an unnecessary portion of the conductive pattern portion, is punched with a punch hole after plating. In addition, the longitudinal direction of the common wiring pattern,
It is also practiced to arrange them in a direction intersecting with the cutting direction of the substrate (usually a direction orthogonal to the cutting direction and parallel to the required wiring pattern), and then cutting the semiconductor chips after connecting them. .
【０００４】図４（Ａ）に従来のプリント配線基板の表
側の必要配線パターンおよび共通配線パターン、（Ｂ）
に同プリント配線基板の裏側の必要配線パターンおよび
共通配線パターンを示す。図中の破線は切断予定ライン
７０を示す。FIG. 4A shows a necessary wiring pattern and a common wiring pattern on the front side of a conventional printed wiring board, and FIG.
The necessary wiring pattern and the common wiring pattern on the back side of the same printed wiring board are shown in FIG. The broken line in the drawing indicates the planned cutting line 70.
【０００５】それぞれの必要配線パターン７１は、共通
配線パターン７２を介して接続され、全体として全て繋
がった導通パターン部が形成されている。共通配線パタ
ーン７２は切断予定ライン７０に直交して配置されてお
り、プリント配線基板７３を各切断予定ライン７０で切
断することによって、共通配線パターン７２を切断し、
必要配線パターン７１を他の必要配線パターン７１から
分離して、それぞれ非導通状態に形成することができ
る。The respective necessary wiring patterns 71 are connected via a common wiring pattern 72, and as a whole, a conductive pattern portion is formed. The common wiring pattern 72 is arranged orthogonal to the planned cutting line 70, and the common wiring pattern 72 is cut by cutting the printed wiring board 73 at each planned cutting line 70.
The required wiring pattern 71 can be separated from the other required wiring patterns 71 and formed in a non-conducting state.
【０００６】一方、電解めっきを用いずに無電解めっき
による方法を使用して、共通配線パターンを省略する場
合もある。On the other hand, the common wiring pattern may be omitted by using a method of electroless plating instead of electrolytic plating.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、近年の
半導体パッケージの極小化に伴う配線パターンの高密度
化によって導通パターン部が微細化され、パンチ孔で正
確に打ち抜くことができないという問題がある。また、
回路作成に必要な必要配線パターンの間に、共通配線パ
ターンを平行に配置することができないという問題もあ
る。However, there is a problem in that the conductive pattern portion is miniaturized due to the high density of the wiring pattern accompanying the miniaturization of the semiconductor package in recent years, and the punching cannot be performed accurately. Also,
There is also a problem that the common wiring patterns cannot be arranged in parallel between the necessary wiring patterns required for circuit creation.
【０００８】また、無電解めっきを用いた場合、このま
までは電解めっきに比べてボンディングの信頼性が劣る
ため、後工程でプラズマ処理等を行う必要があり、時間
と手間がかかり製造コストが上昇するという問題があ
る。Further, when the electroless plating is used, the reliability of the bonding is inferior to that of the electrolytic plating if it is left as it is. Therefore, it is necessary to perform the plasma treatment or the like in the subsequent step, which takes time and labor, and the manufacturing cost is increased. There is a problem.
【０００９】そこで本発明は、高密度の導通パターン部
が配線されるプリント基板において共通配線パターンを
簡単かつ確実に切断して、必要配線パターン同士の非導
通を達成するプリント配線基板およびこれを用いた半導
体製造方法を提供することを目的とする。In view of the above, the present invention provides a printed wiring board in which a common wiring pattern is simply and surely cut in a printed wiring board on which a high-density conductive pattern portion is wired to achieve non-conduction between necessary wiring patterns, and a printed wiring board using the same. Another object of the present invention is to provide a semiconductor manufacturing method.
【００１０】[0010]
【課題を解決するための手段】本発明のプリント配線基
板においては、少なくとも一部の共通配線パターンの幅
を、前記刃物の切断幅より小さく形成し、また、これを
用いた半導体製造方法は、プリント配線基板を共通配線
パターンの幅より幅広の刃物で直線状に切断し、共通配
線パターンを除去する工程とを有して半導体装置を製造
するものである。In the printed wiring board of the present invention, the width of at least a part of the common wiring pattern is formed smaller than the cutting width of the blade, and a semiconductor manufacturing method using the same is A semiconductor device is manufactured by including a step of linearly cutting a printed wiring board with a blade wider than the width of the common wiring pattern and removing the common wiring pattern.
【００１１】この発明によれば、高密度の導通パターン
部が配線されるプリント基板においても共通配線パター
ンを簡単かつ確実に切断して、必要配線パターン同士の
非導通を達成するプリント配線基板およびこれを用いた
半導体製造方法が得られる。According to the present invention, even in a printed circuit board on which a high-density conductive pattern portion is wired, the common wiring pattern is simply and surely cut to achieve non-conduction between necessary wiring patterns, and the same. A semiconductor manufacturing method using is obtained.
【００１２】[0012]
【発明の実施の形態】本発明の請求項１に記載の発明
は、実装される半導体チップを接続して回路を構成する
必要配線パターンと、それぞれの前記必要配線パターン
を電解めっき可能に接続する共通配線パターンとからな
る導通パターン部を備え、この導通パターン部とともに
刃物で切断され、それぞれの必要配線パターンを非導通
にした個別基板となるプリント配線基板において、少な
くとも一部の前記共通配線パターンの幅を、前記刃物の
切断幅より小さく形成し、かつ前記共通配線パターンの
長手方向を切断方向に一致させたことを特徴とするプリ
ント配線基板としたものであり、刃物で一度切断するこ
とによって共通配線パターンを削除して必要配線パター
ンをそれぞれ分離することができ、また、共通配線パタ
ーンを短く形成して無駄な配線を省くことができるとい
う作用を有する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is such that necessary wiring patterns for connecting a semiconductor chip to be mounted to form a circuit and respective necessary wiring patterns are connected by electrolytic plating. In a printed wiring board which is provided with a conductive pattern portion composed of a common wiring pattern and is cut with a cutting tool together with the conductive pattern portion to be a separate board in which each required wiring pattern is made non-conductive, at least a part of the common wiring pattern A width is formed to be smaller than the cutting width of the blade, and the longitudinal direction of the common wiring pattern is made to coincide with the cutting direction. Wiring patterns can be deleted to separate required wiring patterns, and common wiring patterns can be formed short. An effect that can be eliminated spoiled wiring.
【００１３】請求項２に記載の発明は、前記共通配線パ
ターンの幅を５０μｍ以上１００μｍ以下にすることを
特徴とする請求項１に記載のプリント配線基板であり、
５０μｍ以上にすることで電解めっき時に必要な電流を
流すことができ、１００μｍ以下にすることで刃物の厚
みを最小限の厚みにして、プリント配線基板の捨て部分
と発生する切りくずの量を少なくすることができる。The invention according to claim 2 is the printed wiring board according to claim 1, wherein the width of the common wiring pattern is 50 μm or more and 100 μm or less.
A thickness of 50 μm or more allows the necessary current to flow during electrolytic plating, and a thickness of 100 μm or less minimizes the thickness of the blade and reduces the amount of chips and scraps generated on the printed wiring board. can do.
【００１４】請求項３に記載の発明は、プリント配線基
板の両端の端子電極に電流を流して電解めっきを行い、
実装される半導体チップを接続して回路を構成する必要
配線パターンと、それぞれの前記必要配線パターンを接
続する共通配線パターンとからなる導通パターン部を形
成する工程と、前記半導体チップを実装して前記必要配
線パターンに接続する工程と、複数の前記半導体チップ
を樹脂でモールドする工程と、前記プリント配線基板
を、前記共通配線パターンの幅より幅広の刃物で直線状
に切断し、前記共通配線パターンを除去する工程とを有
して、半導体装置を製造することを特徴とする半導体製
造方法としたものであり、プリント配線基板を、前記共
通配線パターンの幅より幅広の刃物で直線状に切断する
ことにより、共通配線パターンを１度の切断で除去する
ことができ、それぞれの必要配線パターンが分離され
る。According to a third aspect of the present invention, a current is applied to the terminal electrodes at both ends of the printed wiring board to perform electrolytic plating,
A step of forming a conductive pattern portion including a necessary wiring pattern for connecting a semiconductor chip to be mounted to form a circuit and a common wiring pattern for connecting each of the necessary wiring patterns; A step of connecting to the necessary wiring pattern, a step of molding a plurality of the semiconductor chips with a resin, the printed wiring board is linearly cut with a blade wider than the width of the common wiring pattern, and the common wiring pattern is formed. A semiconductor manufacturing method characterized by manufacturing a semiconductor device having a step of removing the printed wiring board, and cutting the printed wiring board linearly with a blade wider than the width of the common wiring pattern. Thus, the common wiring pattern can be removed by cutting once, and each necessary wiring pattern is separated.
【００１５】以下、本発明の実施の形態について、図１
から図３を用いて説明する。The embodiment of the present invention will be described below with reference to FIG.
3 to FIG. 3 will be described.
【００１６】図１は本発明の一実施の形態にかかるプリ
ント配線基板の部分平面図、図２は同プリント配線基板
に半導体チップおよび樹脂を設けた状態の斜視図、図３
は同プリント配線基板を用いて製造した半導体装置の斜
視図を示す。FIG. 1 is a partial plan view of a printed wiring board according to an embodiment of the present invention, FIG. 2 is a perspective view showing a state in which a semiconductor chip and resin are provided on the printed wiring board, FIG.
Shows a perspective view of a semiconductor device manufactured using the same printed wiring board.
【００１７】図１においてプリント配線基板１は、たと
えば紙フェノールやガラスエポキシ等からなる板材に、
所定間隔おきに長孔２を貫通させて形成し、両面および
長孔２の内周面に無電解銅めっきを施して銅箔層を形成
し、マスキングによる露光処理、エッチング処理、レジ
スト除去等の工程を経て、銅箔にニッケルおよび金を電
解めっきして必要配線パターン３およびこれを接続する
共通配線パターン４からなる導通パターン部５を形成し
ている。In FIG. 1, the printed wiring board 1 is a plate material made of, for example, paper phenol or glass epoxy,
It is formed by penetrating the long holes 2 at predetermined intervals, and electroless copper plating is applied to both surfaces and the inner peripheral surface of the long holes 2 to form a copper foil layer, and exposure treatment by masking, etching treatment, resist removal, etc. Through the steps, a copper foil is electrolytically plated with nickel and gold to form a conductive pattern portion 5 including a required wiring pattern 3 and a common wiring pattern 4 connecting the wiring pattern 3 and the required wiring pattern 3.
【００１８】必要配線パターン３は長孔２を介して表裏
両面に渡って接続されており、図１には裏面側のパター
ンを示している。The required wiring pattern 3 is connected to both the front and back sides through the long hole 2, and the pattern on the back side is shown in FIG.
【００１９】プリント配線基板１は、長孔２の長手方向
に直交する向きに切断予定ライン６を配置し、この切断
予定ライン６に沿って切断することにより多数の個別基
板７を形成することができる。In the printed wiring board 1, a planned cutting line 6 is arranged in a direction orthogonal to the longitudinal direction of the slot 2, and a large number of individual boards 7 can be formed by cutting along the planned cutting line 6. it can.
【００２０】必要配線パターン３は、隣接する個別基板
７ａの必要配線パターン３ａに長孔２の長手方向に平行
な接続部８を介して接続されている。共通配線パターン
４は、切断予定ライン６に沿って直線状に設けられ、各
接続部８を接続している。共通配線パターン４の幅Ｂ１
（例えば８０μｍ程度）は、図示しない刃物の切断幅Ｂ
２（例えば２００μｍ程度）の半分より小さく形成され
ている。The required wiring pattern 3 is connected to the required wiring pattern 3a of the adjacent individual substrate 7a via a connecting portion 8 parallel to the longitudinal direction of the elongated hole 2. The common wiring pattern 4 is provided in a straight line along the planned cutting line 6 and connects the connecting portions 8. Width B1 of common wiring pattern 4
(For example, about 80 μm) is the cutting width B of a blade not shown.
It is formed to be smaller than half of 2 (for example, about 200 μm).
【００２１】プリント配線基板１を切断予定ライン６に
沿って切断した場合、直線状の共通配線パターン４は刃
物によって切削されて無くなり、それぞれの必要配線パ
ターン３は、他の必要配線パターン３，３ａから分離し
て非導通になる。When the printed wiring board 1 is cut along the line 6 to be cut, the linear common wiring pattern 4 is cut by a blade and disappears, and each necessary wiring pattern 3 is replaced with another necessary wiring pattern 3, 3a. To become non-conductive.
【００２２】切断後の個別基板７には共通配線パターン
４が残らないので、パターンが接近することによるショ
ートの可能性も小さくなり製品の品質を向上させること
ができる。Since the common wiring pattern 4 does not remain on the individual substrate 7 after cutting, the possibility of short circuit due to the approach of the patterns is reduced and the quality of the product can be improved.
【００２３】次に、プリント配線基板１を用いた半導体
製造方法について説明する。Next, a semiconductor manufacturing method using the printed wiring board 1 will be described.
【００２４】（パターン形成工程）まず、前記手順によ
ってプリント配線基板１に導通パターン部５を形成す
る。(Pattern forming step) First, the conductive pattern portion 5 is formed on the printed wiring board 1 by the procedure described above.
【００２５】（半導体チップ実装工程）プリント配線基
板１に半導体チップ９を実装し、ワイヤボンディングに
より必要配線パターン３に接続する。(Semiconductor Chip Mounting Step) The semiconductor chip 9 is mounted on the printed wiring board 1 and connected to the required wiring pattern 3 by wire bonding.
【００２６】（樹脂モールド工程）プリント配線基板１
の表裏両面を図示しない金型で押さえ込んで樹脂１０を
注入し、固化させる。これにより、樹脂１０は、プリン
ト配線基板１上に配列された半導体チップ９を長孔２の
長手方向に沿って１列毎にまとめてモールドされる。(Resin molding process) Printed wiring board 1
Both the front and back sides are pressed by a mold not shown, and the resin 10 is injected and solidified. As a result, the resin 10 is molded together with the semiconductor chips 9 arranged on the printed wiring board 1 in a row along the longitudinal direction of the elongated holes 2.
【００２７】（切断工程）プリント配線基板１を、共通
配線パターン４の幅より幅広の刃物で切断予定ライン６
に沿って直線状に切断する。このとき、樹脂１０も切断
予定ライン６に沿って切断され、それぞれが１つずつの
半導体チップ９を覆った個別樹脂モールド１１が形成さ
れる。(Cutting Step) The printed wiring board 1 is to be cut with a blade wider than the width of the common wiring pattern 4 to be cut line 6
Cut straight along. At this time, the resin 10 is also cut along the planned cutting line 6, and the individual resin molds 11 each of which covers one semiconductor chip 9 are formed.
【００２８】かかる方法によって、半導体装置１２を製
造することができる。共通配線パターン４が接続部８と
ともに除去されるので、完成した半導体装置１２には無
駄なパターンが残らず、パターン剥離等の問題も少なく
なるので、製品の品質を向上させることができる。The semiconductor device 12 can be manufactured by such a method. Since the common wiring pattern 4 is removed together with the connection portion 8, no wasteful pattern is left in the completed semiconductor device 12, and problems such as pattern peeling are reduced, so that product quality can be improved.
【００２９】[0029]
【発明の効果】以上のように本発明によれば、少なくと
も一部の共通配線パターンの幅を、刃物の切断幅より小
さく形成しているので、刃物で一度だけ切断することに
よって、共通配線パターンを削除して必要配線パターン
をそれぞれ分離することができ、高密度の導通パターン
部が配線されるプリント基板においても共通配線パター
ンを簡単かつ確実に切断して、必要配線パターン同士の
非導通を達成することができる。また、共通配線パター
ンを短く形成して無駄な配線を省くことができ、切断後
に共通配線パターンを残さないので、パターン剥離やシ
ョート等が起きにくくなり、歩留まりおよび製品品質を
向上させる。As described above, according to the present invention, since the width of at least a part of the common wiring pattern is formed smaller than the cutting width of the cutting tool, the common wiring pattern is cut only once by the cutting tool. The necessary wiring patterns can be separated from each other by removing the common wiring pattern, and the common wiring patterns can be easily and surely cut even in a printed circuit board on which a high-density conductive pattern portion is wired to achieve non-conduction between the required wiring patterns. can do. Further, the common wiring pattern can be formed short to eliminate wasteful wiring, and since the common wiring pattern is not left after cutting, pattern peeling, short circuit, etc. are less likely to occur and yield and product quality are improved.
【００３０】また、共通配線パターンの幅を５０μｍ以
上１００μｍ以下にすると、めっき時に必要な電流を確
実に確保できるとともに、プリント配線基板の廃棄部分
を少なくすることができる。Further, when the width of the common wiring pattern is 50 μm or more and 100 μm or less, the current required for plating can be reliably secured and the discarded portion of the printed wiring board can be reduced.
【００３１】また、プリント配線基板を、共通配線パタ
ーンの幅より幅広の刃物で直線状に切断し、共通配線パ
ターンを除去する工程を有して半導体装置を製造するの
で、共通配線パターンを１度の切断で除去することがで
き、それぞれの必要配線パターンを短時間で簡単かつ確
実に分離することができる。Further, since the semiconductor device is manufactured with a step of linearly cutting the printed wiring board with a blade wider than the width of the common wiring pattern and removing the common wiring pattern, the common wiring pattern is once formed. Can be removed by cutting, and each required wiring pattern can be easily and surely separated in a short time.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の一実施の形態にかかるプリント配線基
板の部分平面図FIG. 1 is a partial plan view of a printed wiring board according to an embodiment of the present invention.
【図２】同プリント配線基板に半導体チップおよび樹脂
を設けた状態の斜視図FIG. 2 is a perspective view of the same printed wiring board on which a semiconductor chip and a resin are provided.
【図３】同プリント配線基板を用いて製造した半導体装
置の斜視図FIG. 3 is a perspective view of a semiconductor device manufactured using the same printed wiring board.
【図４】（Ａ）は従来例にかかるプリント配線基板の表
側の必要配線パターンおよび共通配線パターンを示す図
（Ｂ）は同プリント配線基板の裏側の必要配線パターン
および共通配線パターンを示す図FIG. 4A shows a necessary wiring pattern and a common wiring pattern on the front side of a printed wiring board according to a conventional example. FIG. 4B shows a necessary wiring pattern and a common wiring pattern on the back side of the printed wiring board.
１ プリント配線基板 ２ 長孔 ３，３ａ 必要配線パターン ４ 共通配線パターン ５ 導通パターン部 ６ 切断予定ライン ７，７ａ 個別基板 ８ 接続部 ９ 半導体チップ １０ 樹脂 １１ 個別樹脂モールド １２ 半導体装置 1 printed wiring board 2 long holes 3,3a Required wiring pattern 4 Common wiring pattern 5 Conduction pattern part 6 planned cutting line 7,7a Individual substrate 8 connections 9 Semiconductor chips 10 resin 11 Individual resin mold 12 Semiconductor device
Claims (3)
を構成する必要配線パターンと、それぞれの前記必要配
線パターンを電解めっき可能に接続する共通配線パター
ンとからなる導通パターン部を備え、この導通パターン
部とともに刃物で切断され、それぞれの必要配線パター
ンを非導通にした個別基板となるプリント配線基板にお
いて、 少なくとも一部の前記共通配線パターンの幅を、前記刃
物の切断幅より小さく形成し、かつ前記共通配線パター
ンの長手方向を切断方向に一致させたことを特徴とする
プリント配線基板。1. A conductive pattern portion comprising a necessary wiring pattern for connecting a semiconductor chip to be mounted to form a circuit and a common wiring pattern for connecting each of the necessary wiring patterns so that they can be electrolytically plated, and the conduction pattern portion is provided. In a printed wiring board, which is an individual board in which each required wiring pattern is made non-conductive by cutting with a cutting tool together with a pattern portion, at least a part of the common wiring pattern has a width smaller than a cutting width of the cutting tool, and A printed wiring board, wherein a longitudinal direction of the common wiring pattern coincides with a cutting direction.
上１００μｍ以下にしたことを特徴とする請求項１に記
載のプリント配線基板。2. The printed wiring board according to claim 1, wherein the width of the common wiring pattern is 50 μm or more and 100 μm or less.
流を流して電解めっきを行い、実装される半導体チップ
を接続して回路を構成する必要配線パターンと、それぞ
れの前記必要配線パターンを接続する共通配線パターン
とからなる導通パターン部を形成する工程と、 前記半導体チップを実装して前記必要配線パターンに接
続する工程と、 複数の前記半導体チップを樹脂でモールドする工程と、 前記プリント配線基板を、前記共通配線パターンの幅よ
り幅広の刃物で直線状に切断し、前記共通配線パターン
を除去する工程とを有して、半導体装置を製造すること
を特徴とする半導体製造方法。3. A necessary wiring pattern for forming a circuit by connecting a semiconductor chip to be mounted is connected to each of the necessary wiring patterns by applying a current to the terminal electrodes on both ends of the printed wiring board for electrolytic plating. A step of forming a conductive pattern portion including a common wiring pattern; a step of mounting the semiconductor chip and connecting to the required wiring pattern; a step of molding a plurality of the semiconductor chips with a resin; And a step of linearly cutting with a blade wider than the width of the common wiring pattern to remove the common wiring pattern, to manufacture a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001309632A JP2003115556A (en) | 2001-10-05 | 2001-10-05 | Printed wiring board and semiconductor manufacturing method using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001309632A JP2003115556A (en) | 2001-10-05 | 2001-10-05 | Printed wiring board and semiconductor manufacturing method using the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003115556A true JP2003115556A (en) | 2003-04-18 |
Family
ID=19128750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001309632A Pending JP2003115556A (en) | 2001-10-05 | 2001-10-05 | Printed wiring board and semiconductor manufacturing method using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003115556A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007027244A (en) * | 2005-07-13 | 2007-02-01 | Matsushita Electric Ind Co Ltd | Manufacturing method of resistor |
-
2001
- 2001-10-05 JP JP2001309632A patent/JP2003115556A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007027244A (en) * | 2005-07-13 | 2007-02-01 | Matsushita Electric Ind Co Ltd | Manufacturing method of resistor |
| JP4654805B2 (en) * | 2005-07-13 | 2011-03-23 | パナソニック株式会社 | Resistor manufacturing method |
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