JPH11163009A - Resin-sealed semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent disconnection of a wiring on a wiring board abutted against a mold abutment part of a metal mold at the time of tightening the metal mold in resin sealing. SOLUTION: A conductive material 4 is buried in advance under a wiring pattern 2 at a part (a part where a mold abutment track 9 is formed) corresponding to a mold abutment part of a metal mold on a wiring board. A bump 6 of a chip 5 is connected onto the wiring pattern 2 and the wiring board is mounted inside a transfer molding metal mold. Then, resin sealing is carried out. Although the wiring pattern 2 at the part where the mold abutment track 9 is formed is cut in a stepped state by tightening the mold at the time of resin sealing, electrical connection of the wiring pattern 2 inside and outside a resin-sealed part 7 is secured by the conductive material 4 buried under the wiring pattern 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a resin-sealed semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device in which a semiconductor chip is mounted on a wiring board and sealed with a resin, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor device, a semiconductor chip (hereinafter, referred to as a chip) is mounted on a lead frame, a wiring board, or the like.
It is manufactured by electrically connecting the electrode of the chip and the inner lead of the lead frame or the wiring portion of the wiring board and sealing it with a resin or the like. In recent years, as electronic devices have become smaller and lighter, semiconductor devices have also been required to be smaller and thinner.
As with electronic components such as chip resistors and chip capacitors, there is an increasing demand for providing them as leadless chip-type products. In order to manufacture this type of product, the substrate material is made of ceramic or epoxy resin, etc., and has wiring with a thickness of several tens of μm on the front and back surfaces, and the wiring on the front and back surfaces is connected via through holes. A method of connecting a chip directly to a wiring portion on the wiring board via a metal bump (hereinafter, referred to as a bump) using a wiring board that has been formed, sandwiching the periphery of the chip with a transfer molding die, and injecting and sealing a resin. Is adopted.

At the time of transfer molding, in order to prevent the resin from leaking from the resin flow paths of runners, gates and cavities formed between the transfer molding die and the insulating substrate, the mold clamping pressure around the resin flow path is reduced. Need to secure. The mold clamping pressure is determined by a ratio of a force for sandwiching the upper and lower molds, that is, a mold clamping force, and an area of the upper and lower molds that touch the mold. In general, it is common to seal many chips at once to increase production efficiency.However, if the entire mold is clamped, the area per mold increases and the clamping pressure per unit area decreases. The mold is configured so that it hits only around the flow path. However, if the mold clamping pressure is increased so that only the area around the resin flow path is brought into contact with the mold, only the area around the resin flow path of the insulating substrate is easily deformed.

[0004] This problem will be described with reference to FIG. FIG. 10 is a plan view of a conventional resin-encapsulated semiconductor device, and FIG.
It is sectional drawing in the A 'line. As shown in FIG. 10, the wiring pattern 2 is formed on the front and back surfaces of the insulating substrate 1.
The wiring pattern on the back surface is connected via a through hole 3. The chip 5 is connected on the wiring pattern by the bump 6 and is sealed by the sealing resin portion 7. Solder plating 8 is applied to the wiring pattern outside the sealing resin portion 7 so that the wiring pattern can be connected to an external circuit via an external electrode 10 provided on the back surface of the substrate. As described above, since the mold clamping pressure is applied in a small area, the wiring pattern 2 connecting the inside and the outside of the resin sealing portion 7 is deformed by the mold contact, causing a disconnection, and disconnection at the trace 9 of the mold contact. become.
As a conventional example for the purpose of preventing disconnection of a wiring pattern by a mold, there is one proposed in JP-A-3-1560. FIGS. 11 and 12 are views for explaining a manufacturing process of the semiconductor device according to the conventional example.

As shown in FIG. 11A, in this conventional example, a plurality of wiring board portions 21 are supported by support bars 29 between two outer frames 33 arranged substantially in parallel. As shown in FIG. 11C, the wiring board portion 21 has wiring patterns 23 on the front and back surfaces of the board, and both are connected by through holes 28. Wiring board unit 21
A concave portion 22 for accommodating a semiconductor element is formed at the center of. As shown in FIGS. 11 (b) and 11 (c), a resin material is formed on the outer frame 33, on the transfer molding gate and the runner part 30, and on the mold peripheral part 31 excluding the cut-off part 32 which becomes an air vent. A protective film 34 is applied. As a result, the pressure of the mold is dispersed and the disconnection of the wiring pattern 23 is prevented, and the step between the wiring pattern 23 and the substrate is reduced to prevent the flow of the sealing resin (27).

Next, as shown in FIG. 11D, a semiconductor element 25 is fixed to the concave portion 22 of the wiring board section 21 using an adhesive 24, and the semiconductor element 25 and the wiring board section 21 are connected by wires 26. The wiring pattern 23 is connected. Next, as shown in FIG. 12E, the wiring board 21 supported by the outer frame 33 is sandwiched between the upper mold 35 and the lower mold 36, and is subjected to transfer molding using the sealing resin 27. The semiconductor element 25 is sealed with a resin. Thereafter, as shown in FIG. 12 (f), the transfer molding gate and the runner portion 3 are formed.
By removing 0 and the outer frame 33, the manufacturing process of the semiconductor device is completed. FIG. 12G is a plan view of the manufactured semiconductor device.

[0007]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Application Laid-Open No. 3-1 has been described.
In the conventional example of Japanese Patent Publication No. 560, it is assumed that the surface of the wiring substrate portion contacts the bottom surface of the upper die except for the portion accommodated in the cavity portion of the die, the gate portion, and the air vent portion. As described above, when the wiring board portion comes into contact with the bottom surface of the upper mold in a large area, the clamping pressure is dispersed. Step breakage due to mold pressure can be prevented. However, if the part of the surface of the wiring board that contacts the mold when the mold is clamped is limited to the periphery of the cavity in order to further increase the productivity, the measures of the conventional example are insufficient and the step break shown in FIG. Cannot be prevented. That is, in the measures for applying the protective film on the wiring substrate, if the area of the die contact portion of the mold is reduced in order to improve productivity, the yield will be significantly reduced.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the conventional semiconductor device. Even in a limited case, it is an object of the present invention to prevent disconnection of the wiring and to prevent a decrease in the yield even if the productivity is increased.

[0009]

In a resin-sealed semiconductor device according to the present invention, a semiconductor chip is mounted on a wiring substrate formed by wiring on the surface of an insulating substrate, and the semiconductor chip is resin-sealed. Wherein at least a portion of the wiring on the wiring substrate that abuts on the mold contact portion of the transfer molding die is at least partially embedded in a portion lower than the surface of the insulating substrate. And

Further, in the method of manufacturing a resin-encapsulated semiconductor device according to the present invention, a mother board is provided in which a plurality of wiring boards each having a surface provided with wiring on an insulating substrate are connected, and a semiconductor chip is mounted on each wiring board. Mounting the mother board in a mold of a transfer molding apparatus in which molten resin is supplied to each wiring board from a sub-runner branched from the main runner, and after clamping the mold, the semiconductor mounted on each wiring board A step of collectively sealing the elements with a resin, and a step of cutting and separating the individual wiring boards from the mother board, wherein at least one of the wirings on the wiring board is in contact with a transfer molding die. The portion that is in contact with the portion is at least partially embedded in a portion lower than the surface of the insulating substrate.

[Operation] In the wiring board used in the semiconductor device of the present invention, at least a part of the wiring that abuts on the contact part of the transfer molding die is at least partially embedded in a part lower than the surface of the insulating substrate. Is formed,
More specifically, a concave portion having a predetermined depth wider than the mold contact mark is formed at the contact portion of the mold contact portion of the insulating substrate, and a conductive material is embedded in the concave portion. A through hole having a width wider than the trace of the mold contact is formed at a contact portion of the mold contact portion of the insulating substrate, and a conductive material is embedded in the through hole. Has a configuration in which the wiring surface is embedded in the substrate so as to coincide with the substrate surface. According to the configuration, even if a step at which the trace of the mold contact is pushed down and a step occurs, the conductive material layer embedded outside the step exists, so that step disconnection can be prevented. . Also,
When the wiring board is used, since the wiring portion and the substrate portion having a larger area than the wiring portion are flush with each other, the mold clamping pressure applied to the wiring portion is reduced, the deformation of the wiring is suppressed, and the wiring Step breakage is prevented.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 1 is a plan view for explaining a first embodiment of the present invention and a sectional view taken along line AA 'of FIG. 2. FIG. It is sectional drawing which shows the state at the time. In FIG. 1, the same reference numerals are given to the same parts as those in the conventional example in FIG. 10, and thus the duplicated description will be omitted. However, in the present embodiment, as shown in FIG. A concave portion is formed in the insulating substrate 1 below the wiring pattern 2 around the resin stopper 7 with a width wider than the die contact mark 9 and wider than the width of the wiring pattern.
Embedded in The material of the insulating substrate 1 is ceramic, epoxy resin, or the like, and the thickness is 0.1 to 0.2.
mm. FIG. 1 shows a completed state of the semiconductor device. During the manufacturing, the semiconductor device is supported by a support bar provided between two outer frames arranged substantially in parallel as in the conventional example shown in FIGS. May be used, or a plurality of sets of wiring patterns may be arranged on one insulating substrate.

A concave portion having a depth of 0.05 to 0.1 mm from the surface of the insulating substrate 1 is provided at a position where the wiring pattern contacts the mold. Fill a conductive material with a thickness equal to the depth of the recess,
The height of the surface of the insulating substrate and the height of the surface of the conductive material are matched. The conductive material 4 is formed using a good conductive material such as copper. Then, the wiring pattern 2 is formed by plating or the like. Alternatively, after a metal film such as a copper layer is formed on the entire surface of the insulating substrate provided with the concave portion by plating or vapor deposition, copper or the like is further grown only on the concave portion to flatten the surface, and then the wiring pattern is formed. May be masked to selectively remove portions other than the wiring pattern. The thickness of the wiring pattern on the insulating substrate is 30 to 50 μm. In addition, Au,
A noble metal such as Ag is plated with a thickness of 3 to 10 μm.

Next, referring to FIG. 2, the operation of the present embodiment at the time of resin sealing will be described. As shown in FIG. 2, when the chip 5 is housed in a cavity 18 formed by an upper mold 11 and a lower mold 12 for transfer molding, and the mold is clamped, the insulating substrate 1 that hits the mold contact portion 13 is formed. The upper wiring pattern 2 is deformed to be in a stepped state, but the electrical connection of the wiring pattern inside and outside the cavity is maintained by the conductive material 4 wider than the mold contact mark arranged below the wiring pattern 2.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIG. FIG.
FIG. 3A is a plan view of a semiconductor device for explaining a second embodiment, and FIG. 3B is a cross-sectional view taken along line AA ′. FIG. 4 is a sectional view showing a state of the semiconductor device according to the present embodiment when the mold is clamped during transfer molding. As shown in FIG. 3, in the present embodiment, the insulating substrate 1 is penetrated under the wiring pattern 2 around the encapsulation resin portion 7 with a width wider than the trace 9 of the mold and wider than the width of the wiring pattern. The conductive material 4 is embedded in the opening. The lower surface of the conductive material 4 protrudes, and is subjected to solder plating 8 to form an external electrode 10. In the present embodiment, the protrusions on the lower surface of the conductive material 4 used as the external electrodes 10 at the time of mounting can be added during the manufacturing process as described later.

As shown in FIG. 4, at the time of mold clamping, a portion of the lower mold 12 which is in contact with the conductive material 4 embedded in the through hole of the insulating substrate 1 has an outer shape smaller than the through hole and a depth of 0.0.
A recess 20 of 5 to 0.1 mm is provided. At the time of transfer molding, the contact portion 13 of the upper mold 11 and the lower mold 1
The conductive material 4 of the substrate sandwiched between the two concave portions 20 undergoes plastic deformation, and a protrusion having the same shape as the concave portion 20 of the lower mold is formed on the back surface side of the insulating substrate 1. After transfer molding, exterior plating is performed, and solder plating 8 is applied to the protrusions.

In this embodiment, the wiring pattern 2 and the through-hole 3 existing on the insulating substrate before being cut and separated into individual semiconductor devices are used as connection terminals for an electrical characteristic test before being cut and separated. It does not need to be used during implementation. Therefore, since the semiconductor device can be separated into individual semiconductor devices from the side surface in the immediate vicinity of the sealing resin portion 7, a smaller semiconductor device can be manufactured.

[Third Embodiment] Next, a third embodiment of the present invention will be described with reference to FIG. FIG.
FIGS. 5A and 5B are views for explaining the third embodiment. FIG. 5A is a sectional view of a semiconductor device manufactured according to the present embodiment, and FIG. It is. In the present embodiment, the structure is such that the wiring pattern 2 is embedded in the insulating substrate 1. That is, the wiring pattern 2
Is the same as the surface height of the insulating substrate 1.
In this embodiment, the wiring pattern on the back surface of the substrate is embedded in the substrate, but the back surface of the substrate may have a shape in which a normal wiring pattern protrudes. This wiring board can be manufactured, for example, as follows. A required number of prepregs are pressed and cured on the front surface or on the front surface and the rear surface of the wiring board manufactured by the usual method. Thereafter, the resin film on the wiring pattern is removed by using a polishing technique such as a CMP method.

In this embodiment, the conductive material is not buried under the wiring pattern at the portion where the trace 9 per mold is formed, but the entire wiring pattern 2 is buried in the substrate. In the region where the trace 9 per mold is formed, the surface of the substrate is exposed to the area occupied by the wiring pattern, and the area of the portion is much larger. Therefore, the pressure from the contact portion of the upper mold at the time of mold clamping is dispersed in the wide substrate portion, and the deformation of the wiring pattern is reduced. That is, even if the mold is clamped at the same pressure, the step of the wiring pattern generated at the trace 9 of the mold becomes small, and the disconnection is suppressed.

[0020]

Next, an embodiment of the present invention will be described with reference to FIGS.
This will be described in detail with reference to FIG. FIG. 6A is a plan view illustrating a state in which a wiring board is mounted on a resin sealing mold for explaining one embodiment of the present invention, and FIG.
It is sectional drawing in the -A 'line. 7 is an enlarged plan view of the enlargement target portion 100 of FIG. 6, and FIG. 8 is an enlarged plan view of the enlargement target portion 200 of FIG. It is sectional drawing (however, FIG. 6 shows the state before mold clamping, and FIG. 8 shows the state at the time of mold clamping). The solid lines in the plan views of each figure show the lower mold 12 and the insulating substrate 1, and the broken lines show the upper mold 11. The insulating substrate 1 of the present embodiment, which is enlarged in FIG. 7, is a glass epoxy resin substrate having a thickness of 0.15 mm, a size of 50 mm × 50 mm, and 27 × 6 = 162 sets of wiring patterns on the surface. Two. The formation of the wiring pattern 2 and the conductive material 4 is performed as follows. A concave portion having a depth of 0.05 mm is formed in advance on the insulating substrate at the wiring pattern portion corresponding to the die contact portion of the cavity of the transfer molding die. After the activation treatment, a copper layer having a thickness of 5 μm is formed on the entire surface by electroless plating. Subsequently, a copper layer is deposited by electroplating using a portion excluding the concave portion until the surface becomes flat. Thereafter, a wiring pattern 2 is formed by forming a mask having a pattern opposite to the wiring pattern and growing a copper layer by 40 μm by selective electric field plating. Further, a silver plating having a thickness of 10 μm is swirled only on the surface portion of the circuit pattern to be connected to the chip electrode and the bump, and the electroless plated copper layer other than the wiring pattern portion is removed by etching.

In this embodiment, in consideration of productivity, transfer molding is performed on six insulating substrates at a time as shown in FIG. While a tablet-shaped sealing resin (not shown) is melted in the pot 14 and pushed down by a plunger (not shown), a runner 15 which is a resin flow path,
The resin is injected into the cavity 18 surrounding the chip 5 through the sub-runner 16 and the gate 17. Air vent 19, 1
9 'allows air in the resin flow path during resin injection to escape. The mold contact portion 13 is formed on the periphery of the sub-runner 16, the gate 17, the cavity 18, and the air vents 19 and 19 'of the upper mold which come into contact with the surface of the insulating substrate 1 (see FIG. 9 (1b)). The height of the mold contact part 13 is 0.1 mm
It is. The depth of the air vent 19 near the cavity 18 is 20 μm, and the depth of the air vent 19 ′ is 50 μm.
m.

Next, a method of manufacturing the semiconductor device of this embodiment will be described with reference to FIG. 9, an imaginary line for cutting the insulating substrate is indicated by 300. The electrodes of the chip are connected to desired wiring patterns on the insulating substrate via bumps made of Au, AuPd or solder [FIG.
a), (2a)]. In the case of Au or AuPd bumps, they are connected by thermocompression or thermocompression combined with ultrasonic waves, and in the case of solder bumps, they are connected by reflow. Next, the insulating substrate is sandwiched and clamped between the upper mold 11 and the lower mold 12 heated to 175 ° C. [FIGS. 9 (1b) and (2b)]. Upper mold 1
When the mold 1 and the lower mold 12 are clamped, the wiring pattern 2 of the insulating substrate 1 that hits the mold contact portion 13 is deformed and cut off, but is embedded under the wiring pattern 2 in an area wider than the width of the mold contact portion 13. The electrically conductive material 4 keeps the electrical connection inside and outside the cavity of the wiring pattern.

Next, the chip 5 is resin-sealed by transfer molding [FIGS. 9 (1c) and (2c)], the sub-runner (not shown), and the resin of the gate 17 are removed to improve the mountability of the semiconductor device. For this purpose, solder plating 8 is applied to the wiring pattern. Next, the insulating substrate is cut with a dicing blade (not shown) and separated into individual semiconductor devices [FIG.
d), (2d)].

[0024]

As described above, in the semiconductor device according to the present invention, at least a part of the wiring on the wiring substrate at the portion corresponding to the contact portion of the transfer molding die is formed in a portion lower than the substrate surface. With this configuration, even if the mold contact portion of the mold is limited to a part of the periphery of the cavity of the mold, the wiring does not break due to the mold clamping. Therefore, according to the present invention, it is possible to produce a resin-encapsulated semiconductor device with high productivity and high yield.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device for describing a first embodiment of the present invention, and a cross-sectional view taken along line AA ′ of the semiconductor device.

FIG. 2 is a cross-sectional view illustrating a mold-clamped state for explaining the first embodiment of the present invention.

FIG. 3 is a plan view of a semiconductor device for explaining a second embodiment of the present invention and a cross-sectional view taken along line AA 'of FIG.

FIG. 4 is a cross-sectional view showing a mold-clamped state for explaining a second embodiment of the present invention.

FIG. 5 is a view for explaining a third embodiment of the present invention;
Sectional drawing of the semiconductor device of a manufacturing process order.

FIG. 6 is a plan view and a cross-sectional view of an upper mold and a lower mold in a state where a wiring board is mounted, for explaining one embodiment of the present invention.

FIG. 7 is an enlarged plan view of a portion 100 to be enlarged in FIG.

8 is an enlarged plan view of a portion 200 to be enlarged in FIG. 7 and a cross-sectional view taken along line AA 'thereof.

9A and 9B are a plan view and a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 10 is a plan view and a cross-sectional view of a conventional example.

11A and 11B are a perspective view and a sectional view in the order of steps for explaining another conventional manufacturing method.

12A and 12B are a cross-sectional view and a plan view in a step that follows the step of FIG. 11 for explaining a manufacturing method of another conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Wiring pattern 3 Through hole 4 Conductive material 5 Chip 6 Bump 7 Sealing resin part 8 Solder plating 9 Trace per mold 10 External electrode 11 Upper mold 12 Lower mold 13 Mold contact part 14 Pot 15 Main runner DESCRIPTION OF SYMBOLS 16 Subrunner 17 Gate 18 Cavity 19, 19 'Air vent 20 Depression 21 Wiring board part 22 Depression 23 Wiring pattern 24 Adhesive 25 Semiconductor element 26 Wire 27 Sealing resin 28 Through hole 29 Support bar 30 Transfer molding gate and runner part 31 Gold Peripheral part of mold cavity 32 Separation part 33 Outer frame 34 Protective film (resin) 35 Upper die 36 Lower die 100 Enlargement target part 200 Enlargement target part 300 Insulating substrate cutting virtual line

Claims (7)

[Claims] 1. A resin-encapsulated semiconductor device in which a semiconductor chip is mounted on a wiring board formed by wiring on the surface of an insulating substrate, and the semiconductor chip is resin-sealed. A resin-encapsulated semiconductor device, wherein a portion of the transfer molding die that abuts on a contact portion is at least partially embedded in a portion lower than the surface of the insulating substrate. 2. A concave portion having a width greater than the width of the mold contact portion and having a predetermined depth is formed in a portion of the insulating substrate in contact with the mold contact portion, and a conductive material is embedded in the concave portion. The resin-sealed semiconductor device according to claim 1, wherein: 3. A through hole having a width larger than the width of the mold contact portion is formed in a portion of the insulating substrate in contact with the mold contact portion, and a conductive material is embedded in the through hole. The resin-encapsulated semiconductor device according to claim 1. 4. The resin-encapsulated semiconductor device according to claim 1, wherein at least wiring on the surface side of the insulating substrate is embedded in the substrate so that the wiring surface matches the substrate surface. . 5. A step of preparing a mother board in which a plurality of wiring boards formed by applying wiring on the surface of an insulating substrate and mounting a semiconductor chip on each wiring board, and a step of mounting a semiconductor chip on a sub-runner branched from a main runner. Mounting the mother board in a mold of a transfer molding apparatus in which the molten resin is supplied to each wiring board, clamping the mold, and then collectively sealing the semiconductor elements mounted on each wiring board with a resin; Cutting and separating individual wiring boards from the board, wherein at least a portion of the wiring on the wiring board that abuts on the mold contact portion of the transfer molding die is insulated. A method for manufacturing a resin-encapsulated semiconductor device, wherein at least a part of the semiconductor device is formed so as to be buried at a portion lower than a surface of a conductive substrate. 6. The method for manufacturing a resin-sealed semiconductor device according to claim 7, wherein the semiconductor elements on the plurality of mother substrates are collectively resin-sealed by the same mold. 7. A through hole buried in a conductive material is formed in a portion of the insulating substrate where a contact portion of a mold for transfer molding of a wiring pattern abuts, and
6. A concave portion having a smaller area than the through hole is formed in a portion of the lower mold corresponding to the through hole.
The manufacturing method of the resin-sealed semiconductor device according to the above.