JP2003114864A - データ転送制御回路 - Google Patents

データ転送制御回路

Info

Publication number
JP2003114864A
JP2003114864A JP2001308691A JP2001308691A JP2003114864A JP 2003114864 A JP2003114864 A JP 2003114864A JP 2001308691 A JP2001308691 A JP 2001308691A JP 2001308691 A JP2001308691 A JP 2001308691A JP 2003114864 A JP2003114864 A JP 2003114864A
Authority
JP
Japan
Prior art keywords
data transfer
queue
control circuit
transfer
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001308691A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003114864A5 (enExample
Inventor
Minenobu Naruse
峰信 成瀬
Shinichi Yoshioka
真一 吉岡
Norio Nakagawa
典夫 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Priority to JP2001308691A priority Critical patent/JP2003114864A/ja
Priority to US10/255,024 priority patent/US6944686B2/en
Publication of JP2003114864A publication Critical patent/JP2003114864A/ja
Publication of JP2003114864A5 publication Critical patent/JP2003114864A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP2001308691A 2001-10-04 2001-10-04 データ転送制御回路 Pending JP2003114864A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001308691A JP2003114864A (ja) 2001-10-04 2001-10-04 データ転送制御回路
US10/255,024 US6944686B2 (en) 2001-10-04 2002-09-26 Data transfer control circuit with terminal sharing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001308691A JP2003114864A (ja) 2001-10-04 2001-10-04 データ転送制御回路

Publications (2)

Publication Number Publication Date
JP2003114864A true JP2003114864A (ja) 2003-04-18
JP2003114864A5 JP2003114864A5 (enExample) 2005-06-16

Family

ID=19127961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001308691A Pending JP2003114864A (ja) 2001-10-04 2001-10-04 データ転送制御回路

Country Status (2)

Country Link
US (1) US6944686B2 (enExample)
JP (1) JP2003114864A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006350782A (ja) * 2005-06-17 2006-12-28 Fujitsu Ltd プロセッサ及びシステム
JP2010049718A (ja) * 2009-12-03 2010-03-04 Hitachi Ltd 半導体装置
JP2012198904A (ja) * 2012-04-25 2012-10-18 Renesas Electronics Corp 半導体装置
US9798679B2 (en) 2003-05-06 2017-10-24 Renesas Electronics Corporation Information processing device and processor

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7120765B2 (en) * 2002-10-30 2006-10-10 Intel Corporation Memory transaction ordering
US6874054B2 (en) * 2002-12-19 2005-03-29 Emulex Design & Manufacturing Corporation Direct memory access controller system with message-based programming
US7685320B1 (en) * 2003-04-11 2010-03-23 Zilker Labs, Inc. Autonomous sequencing and fault spreading
US7793005B1 (en) * 2003-04-11 2010-09-07 Zilker Labs, Inc. Power management system using a multi-master multi-slave bus and multi-function point-of-load regulators
JP2006065697A (ja) * 2004-08-27 2006-03-09 Hitachi Ltd 記憶デバイス制御装置
US8041851B2 (en) * 2005-11-30 2011-10-18 International Business Machines Corporation Generic DMA memory space mapping
US7707324B1 (en) * 2006-06-28 2010-04-27 Marvell International Ltd. DMA controller executing multiple transactions at non-contiguous system locations
US7433977B2 (en) * 2006-11-28 2008-10-07 Telefonaktiebolaget Lm Ericsson (Publ) DMAC to handle transfers of unknown lengths
US7512723B2 (en) * 2006-12-29 2009-03-31 Freescale Semiconductor, Inc. Queued interface devices, multi-core peripheral systems, and methods for sharing a peripheral in a multi-core system
US8120205B2 (en) * 2008-07-18 2012-02-21 Zilker Labs, Inc. Adding and dropping phases in current sharing
US8120203B2 (en) * 2008-07-18 2012-02-21 Intersil Americas Inc. Intelligent management of current sharing group
US8239597B2 (en) * 2008-07-18 2012-08-07 Intersil Americas Inc. Device-to-device communication bus for distributed power management
US8237423B2 (en) * 2008-07-18 2012-08-07 Intersil Americas Inc. Active droop current sharing
KR101202738B1 (ko) * 2008-12-22 2012-11-20 한국전자통신연구원 멀티 채널 데이터 전송 장치
GB2497525A (en) * 2011-12-12 2013-06-19 St Microelectronics Ltd Controlling shared memory data flow
US8862794B2 (en) * 2012-08-21 2014-10-14 Lsi Corporation Non-disruptive selective traffic blocking in a SAS domain
US9704355B2 (en) 2014-10-29 2017-07-11 Clover Network, Inc. Secure point of sale terminal and associated methods
US11620246B1 (en) * 2022-05-24 2023-04-04 Ambiq Micro, Inc. Enhanced peripheral processing system to optimize power consumption

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4270167A (en) * 1978-06-30 1981-05-26 Intel Corporation Apparatus and method for cooperative and concurrent coprocessing of digital information
US5781799A (en) * 1995-09-29 1998-07-14 Cirrus Logic, Inc. DMA controller arrangement having plurality of DMA controllers and buffer pool having plurality of buffers accessible to each of the channels of the controllers
US5828901A (en) * 1995-12-21 1998-10-27 Cirrus Logic, Inc. Method and apparatus for placing multiple frames of data in a buffer in a direct memory access transfer
US6049842A (en) * 1997-05-01 2000-04-11 International Business Machines Corporation Efficient data transfer mechanism for input/output devices

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9798679B2 (en) 2003-05-06 2017-10-24 Renesas Electronics Corporation Information processing device and processor
US10289569B2 (en) 2003-05-06 2019-05-14 Renesas Electronics Corporation Information processing device and processor
US10983924B2 (en) 2003-05-06 2021-04-20 Renesas Electronics Corporation Information processing device and processor
JP2006350782A (ja) * 2005-06-17 2006-12-28 Fujitsu Ltd プロセッサ及びシステム
JP2010049718A (ja) * 2009-12-03 2010-03-04 Hitachi Ltd 半導体装置
JP2012198904A (ja) * 2012-04-25 2012-10-18 Renesas Electronics Corp 半導体装置

Also Published As

Publication number Publication date
US6944686B2 (en) 2005-09-13
US20030070011A1 (en) 2003-04-10

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