JP2003098999A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the constitution of the peripheral circuits in a pixel part and to reduce the frame area of a panel as a result. SOLUTION: The device is provided with a pixel electrode 80, a plurality of drain signal lines 61 which supply digital video signals D0 to D2 , a plurality of capacitor elements C0 to C2 capacitances of which have been weighted respectively corresponding to the bits of the signals D0 to D2 , a refresh transistor RT which is used to initialize the voltage of the electrode 80 to a voltage Vsc and charge-transfer transistors TT0 to TT2 which supply the charges accumulated in the capacitors C0 to C2 to the electrode 80. Displaying is conducted by supplying analog video signals corresponding to the signals D0 to D2 to the electrode 80.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a DA for converting a digital video signal into an analog video signal.
The present invention relates to a display device having a conversion function.

[0002]

2. Description of the Related Art In recent years, portable display devices such as portable televisions and mobile phones have been demanded as market needs. In response to such demands, research and development have been actively conducted in order to meet the demand for downsizing, weight reduction, and power saving of display devices.

FIG. 15 shows a circuit configuration diagram of one display pixel of a conventional liquid crystal display device. In an actual liquid crystal display device,
A plurality of the display pixels are arranged in a matrix in rows and columns to form a pixel area of the display panel.

A gate signal line 51 and a drain signal line 61 are formed so as to intersect with each other on an insulating substrate (not shown), and a pixel selection thin film transistor connected to both signal lines 51, 61 near the intersection. 72 are provided. Hereinafter, the thin film transistor is abbreviated as TFT. Pixel selection TFT
The source 11 s of 72 is connected to the pixel electrode 80 of the liquid crystal 21.

Further, an auxiliary capacitance 85 for holding the voltage of the pixel electrode 80 for one field period is provided,
One terminal 86 of the auxiliary capacitance 85 is connected to the pixel selection TFT 7
The second electrode 11 is connected to the second source 11 s, and the other electrode 87 is applied with a common potential for each display pixel.

Here, a scanning signal (H
Level) is applied, the pixel selection TFT 72 is turned on, the analog video signal is transmitted from the drain signal line 61 to the pixel electrode 80, and is held in the auxiliary capacitance 85. The video signal voltage applied to the pixel electrode 80 is applied to the liquid crystal 21, and the liquid crystal 21 is oriented according to the voltage, whereby a liquid crystal display can be obtained. Therefore,
Liquid crystal display can be performed regardless of moving images and still images.

By the way, the analog video signal input to the drain signal line 61 is obtained by digital-analog converting the input digital video signal by a DA converter. Conventionally, in a liquid crystal display device in which a DA converter is built in a display panel, the DA converter is arranged in a driver circuit in the peripheral portion of the pixel.

[0008]

However, in the conventional liquid crystal display device, since the DA converter is arranged in the driver circuit arranged in the frame of the display panel, the peripheral circuit of the pixel portion becomes complicated, and There is a problem that the frame area of the display panel increases. Particularly, when the gradation voltage is input from the outside, the number of wirings of the gradation voltage signal increases in proportion to the square of the number of gradations.

Further, since the DA converter is arranged corresponding to each column of pixels, there is a limit to the width in which the DA converter can be arranged. The DA converter that can be arranged in that width is limited to 4 bits. Therefore, the conventional liquid crystal display device has a limit in the number of gradations.

[0010]

The display device of the present invention has been made in view of the above-mentioned problems. In a display device having a plurality of pixels, a pixel electrode and a digital video signal are provided for each pixel. A plurality of capacitive elements for accumulating charges according to each bit, and a charge transfer transistor for supplying the electric charges accumulated by the plurality of capacitive elements to the pixel electrode according to a timing signal. Is.

According to this structure, the digital video signal can be converted from digital to analog in the pixel portion for display, so that the peripheral circuit of the pixel portion can be simplified and the frame area of the display panel can be reduced. It can be made smaller.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a display device according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of the display device according to the first embodiment.
In the figure, only one pixel portion is shown for simplicity, but in an actual display device, a plurality of this pixel portion are arranged in rows and columns in a matrix.

A gate signal line 51 is arranged in one direction on an insulating substrate (not shown). A scanning signal G1 is supplied to the gate signal line 51 from a gate driver (not shown). Three drain signal lines 61 are arranged in a direction intersecting the gate signal line G1. Data corresponding to each bit of the digital video signal is externally input to the drain signal line 61. The least significant bit is output to the drain signal line D0 and the most significant bit is output to the drain signal line D2.
In the present embodiment, the number of bits of the digital video signal is 3 bits, but by increasing the number of bits of this digital video signal, it is possible to display with more gradation. On the contrary, by reducing the number of bits of the digital video signal, it is possible to simplify the circuit arranged in the pixel for low gradation display.

The pixel selection transistors GT0 to GT2 are connected to each drain signal line 61. Each of the pixel selection transistors GT0 to GT2 is composed of an N-channel type TFT (Thin Film Transistor). The gate scanning signal G1 is commonly supplied to each gate of the pixel selection transistors GT0 to GT2, and the charge corresponding to each bit of the digital video signal written through the pixel selection transistors GT0 to GT2 is stored in each source thereof. Capacitance elements C0 to C2 for connection are connected.

The capacitance values of the capacitance elements C0 to C2 are weighted according to each bit of the digital video signal. That is, when the capacitance value of the capacitive element C0 corresponding to the least significant bit is C, the capacitive element C1 corresponding to the next bit is
Is 2C, and the capacitive element C2 for the most significant bit is 4C.
Each has a capacitance value of. In order to weight the capacitance values as described above, the facing area of the capacitance electrodes or the distance between the capacitance electrodes may be changed for each capacitance element.

The charge transfer transistors TT0 to TT2 are composed of the pixel electrode 80 of the liquid crystal 21 and the pixel selection transistors GT0 to GT0.
It is connected to GT2. That is, the sources of the charge transfer transistors TT0 to TT2 are commonly connected to the pixel electrode 80. A counter electrode drive signal COM is applied to the counter electrode 30 (also referred to as a common electrode).

Each of the charge transfer transistors TT0 to TT2 is composed of an N-channel type TFT. The strobe signal line 11 is commonly connected to the gates of these charge transfer transistors TT0 to TT2, and the strobe signal STB is commonly supplied. The charge transfer transistors TT0 to TT2 respond to the strobe signal STB rising to a high level, and the above-mentioned capacitive elements C0 to C2.
The charges accumulated in the pixel electrode 80 are supplied to the pixel electrode 80. As a result, a voltage according to the digital video signals D0 to D2, that is, a voltage obtained by digital-analog conversion is applied to the pixel electrode 80.

The refresh transistor RT is a transistor for initializing the voltage of the pixel electrode 80 to a predetermined voltage Vsc, the drain thereof is the pixel electrode 80, and the source thereof is the initialization voltage line 12 to which the voltage Vsc is supplied. , Their gates are respectively connected to the refresh signal line 10 which supplies the refresh signal RFH. That is, the refresh transistor RT turns on in response to the refresh signal RFH rising to a high level,
The voltage of the pixel electrode 80 is initialized to the voltage Vsc.

Here, after the voltage of the pixel electrode 80 is initialized by the refresh transistor RT, the charge transfer transistors TT0 to TT2 are turned on, and the pixel electrode 80 is turned on.
Is supplied with the electric charges accumulated in the capacitive elements C0 to C2. Accordingly, the digital video signals D0 to D2 are applied to the pixel electrode 80.
The voltage according to is always supplied accurately.

The voltage Vpix of the pixel electrode 80 at this time is obtained. When the amplitude voltage of the digital video signals D0 to D2 is VD and the capacitance of the liquid crystal 21 is CLC, the following formula is established.

[0021]

[Equation 1]

From this equation, Vpix is expressed by the following equation.

[0023]

[Equation 2]

Next, the overall structure of the above-described liquid crystal display device will be described with reference to FIGS.

Generally, liquid crystal display devices are classified into a dot sequential type and a line sequential type. The dot-sequential type liquid crystal display device writes video signals to each pixel one after another in response to a sampling pulse. On the other hand, a line-sequential type liquid crystal display device holds a video signal for one horizontal period according to a sampling pulse,
The held video signal is output to each drain signal line according to the transfer pulse.

FIG. 2 is a circuit diagram showing an example in which the present invention is applied to a dot-sequential type liquid crystal display device. Pixels GS12, GS21, GS similar to the pixel GS11 shown in FIG.
22, ... Are arranged in rows and columns. The refresh signal RFH1, the strobe signal STB1, and the scanning signal G are applied to the pixels GS11, GS12, ... In the first row.
1. The voltage Vsc for initialization is supplied. The refresh signal RFH2, the strobe signal STB2, and the scanning signal G are applied to the pixels GS21, GS22, ... In the second row.
2. The voltage Vsc for initialization is supplied.

The digital video signals D0 to D2 are supplied to the three signal lines 60. A sampling transistor SPT for sampling the digital video signals D0 to D2 on the signal line 60 for each column and supplying the sampled signal to the drain signal line 61.
1, SPT2 ... The sampling pulse from the shift register 20 is supplied to the gates of the sampling transistors SPT1, SPT2.

The shift register 20 uses the horizontal clock CKH.
In accordance with the above, a sampling pulse is created by sequentially shifting the horizontal start signal STH. In response to the rising edge of this sampling pulse, the sampling transistor SPT
1, SPT2 ... Turn on sequentially and digital video signal D0
.About.D2 are sampled and supplied to the drain signal line 61.

FIG. 3 is a circuit diagram showing an example in which the present invention is applied to a line-sequential type liquid crystal display device. The configuration of the pixel region is exactly the same as that of the dot-sequential type, and therefore its description is omitted. The digital video signals D0 to D2 have three signal lines 60
Are sequentially supplied. A first latch circuit 25 for latching the digital video signals D0 to D2 is provided for each column.

The latch circuit 25 samples the digital video signals D0 to D2 on the signal line 60 in accordance with the sampling pulse and holds them for one horizontal period. The sampling pulse is created by the shift register 20. That is, the shift register 20 creates sampling pulses by sequentially shifting the horizontal start signal according to the horizontal clock CKH.

The digital video signals D0 to D2 held in the first latch circuit 25 are latched in the second latch circuit 26 on the basis of the transfer pulse TP generated after the end of one horizontal period, and then are drained to the drain signal line 61. It is output at the same time.

Next, the operation timing of the liquid crystal display device having the above configuration will be described. FIG. 4 shows a timing chart of the liquid crystal display device. Consider a case where display is performed for the pixel GS11 illustrated in FIG. First, the scanning signal G1, the refresh signal RFH1, and the strobe signal STB1 are low, and the pixel selection transistors GT0 to GT2, the refresh transistor RT, and the charge transfer transistor TT.
0 to TT2 are all off. From this state, the scanning signal G
1 rises high for one horizontal period.

Then, the pixel selection transistors GT0 to GT
T2 is turned on, and charges corresponding to each bit of the digital video signals D0 to D2 are stored in the capacitive elements C0 to C2. The timing at which the digital video signals D0 to D2 change depends on whether it is a dot-sequential type or a line-sequential type, as described above. In the dot-sequential type, the timing is synchronized with the timing at which the sampling pulse is generated, so that the timing is sequentially shifted for each pixel arranged in the row direction. On the other hand, in the line-sequential type, it is constant in each pixel because it is synchronized with the transfer pulse.

Next, when the refresh signal RFH1 rises to high, the refresh transistor RT is turned on, and the electric charge previously accumulated in the pixel electrode 80 is discharged,
It is initialized to the voltage Vsc.

Next, the scanning signal G1 falls and the pixel selection transistors GT0 to GT2 are turned off. This allows
Since both the pixel selection transistors GT0 to GT2 and the charge transfer transistors TT0 to TT2 are turned off, the capacitance element C0
~ C2 is temporarily electrically isolated. Next, when the refresh signal RFH falls to low, the refresh transistor RT turns off. As a result, the pixel electrode 80 is electrically isolated.

After that, the strobe signal STB1 rises to high, and the charge transfer transistors TT0 to TT2 are turned on. Then, the charges accumulated in the capacitive elements C0 to C2 are
Pixel electrode 8 through charge transfer transistors TT0-TT2
Supplied to zero. Thereby, the pixel electrode 80 of the liquid crystal 21
A voltage corresponding to the digital video signals D0 to D2, that is, a voltage Vpix that has been digital-analog converted is applied to the display unit, and gradation display according to the digital video signals D0 to D2 can be performed.

The first embodiment described above relates to a liquid crystal display device which is a voltage-controlled display device. However, as in a fifth embodiment described later, a current such as an electroluminescence display device is used. Can be changed to a control display device. In this case, by replacing the liquid crystal 21 with an EL element and an EL driving transistor, the electroluminescence device can be constructed as it is. This also applies to the second, third and fourth embodiments described below.

Next, a display device according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a circuit diagram of the liquid crystal display device according to the second embodiment. In the figure, only one pixel portion is shown for simplicity,
In an actual display device, a plurality of pixel portions are arranged in rows and columns in a matrix. In the present embodiment, a signal changeover switch SW is provided on the three drain signal lines 61 to switch and supply either the digital video signals D0 to D2 or the analog video signal A0. Hereinafter, a state in which the signal selection switch SW selects the analog video signal A0 will be referred to as an analog mode, and a state in which the signal selection switch SW selects the digital video signals D0 to D2 will be referred to as a digital mode. Other circuit configurations are similar to those of the display device of FIG.

Next, the operation timing of the liquid crystal display device having the above configuration will be described. In the digital mode, as in the first embodiment, the digital video signals D0 to D2 are output to the drain signal line 61. The operation is exactly the same as that of the first embodiment. The timing diagram is also shown in Figure 4.
Is the same as.

On the other hand, in the analog mode, the analog video signal A0 is changed to 3 by switching the signal changeover switch SW.
It is commonly output to the drain signal line 61 of the book. Next, the operation in the analog mode will be described with reference to the timing chart of FIG.

In this case, the refresh signal RFH is always low, the strobe signal is always high, the refresh transistor RT is always off, and the charge transfer transistor T.
T0 to TT2 are always on. When the scanning signal G1 rises to high for one horizontal period, the pixel selection transistor GT
0 to GT2 are turned on, and a voltage corresponding to the analog video signal A0 is supplied to the pixel electrode 80 of the liquid crystal 21. That is, in the analog mode, the display pixel is changed so as to function similarly to the display pixel of the conventional example shown in FIG. Here, the capacitance elements C0 to C2 function as auxiliary capacitances 85, and the pixel selection transistors GT0 to GT2 are the transistors 72.
Work as.

Next, a display device according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a circuit diagram of the liquid crystal display device according to the third embodiment. In the figure, only two pixel portions are shown for simplicity.
In an actual display device, a plurality of pixel portions are arranged in rows and columns in a matrix.

The display device according to the present embodiment is obtained by simplifying the layout of the display device according to the first embodiment. As described above, the charge transfer transistor TT0
˜TT2 may be turned on for a certain period after the pixel selection transistors GT0 to GT2 are turned off. Therefore, the gates of the charge transfer transistors TT0 to TT2 are connected to the gate signal line 52 of the next row to supply the scanning signal G2.

As a result, the charge transfer transistor TT0
Since the strobe signal 11 for controlling ~ TT2 can be deleted, the pixels can be miniaturized accordingly. In this embodiment, the charge transfer transistors TT0 to TT0 to
Since TT2 is turned on for one horizontal period (the period when the scanning signal G2 is high) and turned off thereafter, the capacitance elements C0 to
C2 does not fully function as a storage capacitor. Therefore, in order to stably hold the voltage of the pixel electrode 80 for one field period, it is necessary to additionally provide the auxiliary capacitance 85.

Next, the operation timing of the liquid crystal display device having the above configuration will be described. FIG. 8 shows an operation timing chart of the liquid crystal display device. First, the scanning signal G1, the refresh signal RFH, and the strobe signal are low, and the pixel selection transistors GT0 to GT2, the refresh transistor RT, and the charge transfer transistors TT0 to TT2 are all off. From this state, the scanning signal G1 rises to high for one horizontal period.

Then, the pixel selection transistors GT0 to GT
T2 is turned on, and charges corresponding to each bit of the digital video signals D0 to D2 are stored in the capacitive elements C0 to C2. Then
When the refresh signal RFH rises to high, the refresh transistor RT turns on and the pixel electrode 80
The electric charge stored in is discharged and initialized to the voltage Vsc. Next, when the refresh signal RFH falls to low, the refresh transistor RT turns off. Then, after the end of one horizontal period, the scanning signal G2 rises to high during the next horizontal period after a horizontal blanking period. Then,
The charge transfer transistors TT0 to TT2 are turned on to turn on the capacitive element C.
The charge accumulated in 0 to C2 is the charge transfer transistor TT.
It is supplied to the pixel electrode 80 through 0 to TT2. As a result, the digital video signal D0 is applied to the pixel electrode 80 of the liquid crystal 21.
A voltage corresponding to D2, that is, a digital-analog converted voltage Vpix is applied, and a digital video signal D0
It is possible to perform gradation display according to D2.

In addition to the above configuration, it is possible to provide a signal changeover switch SW for switching and supplying either the digital video signals D0 to D2 or the analog video signal A0 to the three drain signal lines 61. In this case, as shown in FIG. 9, in the analog mode, the transistor 40 for disconnecting the gates of the charge transfer transistors TT0 to TT2 from the gate signal line 52 and the charge transfer transistor TT0.
A transistor 41 for connecting the separated gates of ˜TT2 to the gate signal line 51 may be provided.

As a result, the charge transfer transistor TT0
The scanning signal G2 of the next row is supplied to the gates of the -TT2 in the digital mode, and the scanning signal G1 of the row is supplied in the analog mode. Therefore, in the digital mode, the digital video signals D0 to D2 are similar to the above.
It is possible to perform gradation display in accordance with the above, and it is possible to perform gradation display in accordance with the analog video signal A0 in the analog mode.

Even when the signal changeover switch SW is provided to switch between the digital mode and the analog mode, the transistors 40 and 41 are not necessarily required. For example, when two rows are simultaneously selected in the analog mode, that is, the scanning signals G1 and G2 are selected.
This is the case where the gate driver is configured such that the two lines become high simultaneously.

Next, a display device according to a fourth embodiment of the present invention will be described with reference to the drawings. Figure 10
It is a circuit diagram of a liquid crystal display device according to a fourth embodiment. In the figure, only one pixel portion is shown for simplicity, but in an actual display device, a plurality of this pixel portion are arranged in rows and columns in a matrix.

The display device according to the present embodiment is obtained by simplifying the layout of the display device according to the first embodiment. The refresh transistor RT is a liquid crystal pixel electrode 8
0 is initialized to the voltage Vsc, but this initialization is performed before the charges accumulated in the capacitive elements C0 to C2 are supplied to the pixel electrode 80 through the charge transfer transistors TT0 to TT2. Therefore, the refresh transistor RT may be turned on before the charge transfer transistors TT0 to TT2 are turned on. Therefore, in the present embodiment, the gate of the refresh transistor RT is connected to the gate signal line 51 of the pixel GS11. Other configurations are similar to those of the first embodiment. As a result, the refresh signal line 10 for supplying the refresh signal RFH can be deleted, and the pixel area can be reduced accordingly.

Next, the operation timing of the liquid crystal display device having the above configuration will be described. FIG. 11 shows a timing chart of the liquid crystal display device. First, the scanning signal G1 and the strobe signal are low, and the pixel selection transistors GT0 ...
GT2, the refresh transistor RT, and the charge transfer transistors TT0 to TT2 are all off. From this state, the scanning signal G1 rises to high for one horizontal period.

Then, the pixel selection transistors GT0 to GT
T2 is turned on, and charges corresponding to each bit of the digital video signals D0 to D2 are stored in the capacitive elements C0 to C2. at the same time,
The refresh transistor RT is turned on, the electric charge previously accumulated in the pixel electrode 80 is discharged, and it is initialized to the voltage Vsc.

When one horizontal period ends, the scanning signal G1 falls to low, and the pixel selection transistors GT0 to GT2 and the refresh transistor RT are turned off. After that, when the strobe signal STB rises, the charge transfer transistors TT0 to TT2 are turned on and the charges accumulated in the capacitance elements C0 to C2 are supplied to the pixel electrode 80 through the charge transfer transistors TT0 to TT2. As a result, the pixel electrode 80 of the liquid crystal 21 has a voltage corresponding to the digital video signals D0 to D2, that is, a voltage V which is digital-analog converted.
By applying pix, it is possible to perform gradation display according to the digital video signals D0 to D2.

In the fourth embodiment, as in the third embodiment, the gates of the charge transfer transistors TT0 to TT2 are connected to the gate signal line 52 of the next row, and the scanning signal G
2 may be supplied. The structure of such a liquid crystal display device is shown in FIG. As a result, the strobe signal line 11 can be deleted in addition to the refresh signal line 10, so that the pixel area can be further miniaturized.

Next, the operation timing of the liquid crystal display device having the above configuration will be described. FIG. 13 shows a timing chart of the liquid crystal display device. First, the scanning signal G1 and the strobe signal are low, and the pixel selection transistors GT0 ...
GT2, the refresh transistor RT, and the charge transfer transistors TT0 to TT2 are all off. From this state, the scanning signal G1 rises to high for one horizontal period.

Then, the pixel selection transistors GT0 to GT
T2 is turned on, and charges corresponding to each bit of the digital video signals D0 to D2 are stored in the capacitive elements C0 to C2. at the same time,
The refresh transistor RT is turned on, the electric charge previously accumulated in the pixel electrode 80 is discharged, and it is initialized to the voltage Vsc.

Next, when the scanning signal G1 falls to low, the pixel selection transistors GT0 to GT2 and the refresh transistor RT are turned off. Then, after the end of one horizontal period, the scanning signal G2 rises to high during the next horizontal period after a horizontal blanking period. Then, the charge transfer transistors TT0 to TT2 are turned on and the charges accumulated in the capacitive elements C0 to C2 are supplied to the pixel electrode 80 through the charge transfer transistors TT0 to TT2. As a result, the pixel electrode 80 of the liquid crystal 21 has a voltage corresponding to the digital video signals D0 to D2, that is, a voltage V which is digital-analog converted.
By applying pix, it is possible to perform gradation display according to the digital video signals D0 to D2.

Next, a display device according to a fifth embodiment of the present invention will be described with reference to the drawings. Figure 14
It is a circuit diagram of a display concerning a 5th embodiment. In the figure, only one pixel portion is shown for simplification, but in an actual display device, a plurality of pixel portions are arranged in a matrix. Further, the same components as those in FIG. 1 for explaining the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

The present embodiment is an example in which the present invention is applied to an electroluminescence display device. The source 44 connected in common to the charge transfer transistors TT0 to TT2 is EL
It is connected to the gate of the drive transistor 45. EL
The drive transistor 45 is an N-channel TFT. E
The source of the L drive transistor 45 is supplied with the power supply voltage VDD, and the drain thereof is connected to the EL element 46. The EL element 46 is a light emitting element that emits light with a brightness according to the magnitude of the current flowing through the element.

At the gate of the EL drive transistor 45,
A refresh transistor 47 for initializing the gate voltage of the EL drive transistor 46 to the voltage Vsc is connected. Other configurations are similar to those of the first embodiment.

The operation timing of the liquid crystal display device having the above configuration will be described with reference to FIG. Scan signal G1, refresh signal RFH1 and strobe signal S
TB1 is low, and the pixel selection transistors GT0 to GT0
T2, the refresh transistor RT, and the charge transfer transistors TT0 to TT2 are all off. From this state, the scanning signal G1 rises to high for one horizontal period.

Then, the pixel selection transistors GT0 to GT
T2 is turned on, and charges corresponding to each bit of the digital video signals D0 to D2 are stored in the capacitive elements C0 to C2. Then
When the refresh signal RFH rises to a high level, the refresh transistor RT is turned on, the electric charge previously accumulated in the gate of the EL drive transistor 45 is discharged, and the voltage Vsc is initialized.

Next, when the refresh signal RFH falls to low, the refresh transistor RT turns off. After that, the strobe signal STB rises to high, and the charge transfer transistors TT0 to TT2 are turned on. Then, the charges accumulated in the capacitance elements C0 to C2 are supplied to the gate of the EL drive transistor 45 through the charge transfer transistors TT0 to TT2.

As a result, the gate of the EL drive transistor 45 has a voltage corresponding to the digital video signals D0 to D2,
That is, the voltage Vpix that has been digital-analog converted
Is applied. Since the conductivity of the EL drive transistor 45 changes according to the voltage Vpix, the current flowing through the EL drive transistor 45 changes according to the voltage Vpix, and the current flowing through the EL element 46 also changes. Therefore, E
The L element 46 emits light with a brightness according to the digital video signals D0 to D2. That is, gradation display can be performed.

The configurations of the second, third and fourth embodiments described above can be applied to the electroluminescence display device. That is, as in the second embodiment, a signal changeover switch SW may be provided to the three drain signal lines 61 to switch and supply either the digital video signals D0 to D2 or the analog video signal A0.

Further, as in the third embodiment, in order to simplify the layout and reduce the pixel area, the gates of the charge transfer transistors TT0 to TT2 are connected to the gate signal line 52 of the next row, and the scanning signal is supplied. G2 may be supplied. Further, as in the fourth embodiment, in order to simplify the layout and reduce the pixel area, the gate of the refresh transistor RT is connected to the gate signal line 51 of the pixel GS11.
You may connect to.

The above-described disclosure of the embodiment does not limit the scope of the claims of the present application and the scope of equivalents thereof, and various modifications can be made without departing from the spirit of the present invention. The invention described in the claims includes all such modifications.

For example, in the first to fifth embodiments, the 3-bit digital video signals D0 to D2 are digital-to-analog converted, but the number of bits is not limited to 3 and may be 2 or more. It is also within the scope of the present invention to change the configuration in which the digital video signals D0 to D2 are converted from digital to analog. In this case, the number of drain signal lines 61, the number of pixel selection transistors, the charge transfer transistors, and the number of capacitors may be changed according to the number of bits.

[0070]

According to the display device of the present invention, since the digital video signal is converted into the analog video signal in the pixel section, the configuration of the peripheral circuit of the pixel section is simplified, and the area of the frame is reduced. It can be reduced.

Further, unlike the case where the DA converter is arranged in the driver circuit, there is no limitation in the area where the DA converter is arranged, so that it is possible to cope with an increase in the number of bits of the digital video signal and multi-gradation display.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a dot-sequential type liquid crystal display device according to a first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a line-sequential liquid crystal display device according to a first embodiment of the present invention.

FIG. 4 is a timing diagram showing an operation of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 6 is a timing chart showing an operation in an analog mode according to the second embodiment of the present invention.

FIG. 7 is a circuit diagram of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 8 is a timing diagram showing an operation of the liquid crystal display device according to the third embodiment of the present invention.

FIG. 9 is another circuit diagram of the liquid crystal display device according to the third embodiment of the present invention.

FIG. 10 is a circuit diagram of a liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 11 is a timing chart showing an operation of the liquid crystal display device according to the fourth embodiment of the present invention.

FIG. 12 is another circuit diagram of the liquid crystal display device according to the fourth embodiment of the present invention.

FIG. 13 is another timing chart showing the operation of the liquid crystal display device according to the fourth embodiment of the present invention.

FIG. 14 is a circuit diagram of an electroluminescence display device according to a fifth embodiment of the present invention.

FIG. 15 is a circuit diagram of a liquid crystal display device according to a conventional example.

[Explanation of symbols]

GT0-GT2 Pixel selection transistor TT0 to TT2 Charge transfer transistor RT refresh transistor C0 to C2 capacitive element 10 Refresh signal line 11 Strobe signal line 12 Initialization voltage line 12 20 shift register 21 liquid crystal 25 First Latch Circuit 26 Second Latch Circuit 30 counter electrode 51 gate signal line 61 Drain signal line SW signal changeover switch

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 623 G09G 3/20 623F 624 624B 3/36 3/36 H05B 33/14 H05B 33/14 A F-term (reference) 2H092 GA59 JA24 NA25 PA06 3K007 AB17 AB18 EB00 GA04 5C006 AA01 AA16 AF42 AF83 BB16 BC03 BC06 BC12 BC20 BF31 EB05 FA41 5C080 AA06 AA10 BB05 DD03 DD22 EE04 A10A22 A22 A22 A22 A22 A22 A22 A22 A22 A22 A22 A22 A22 A22 A22 A22 A22 A4

Claims (13)

[Claims] 1. A display device having a plurality of pixels,
For each of the pixels, a pixel electrode, a plurality of capacitive elements that store charges corresponding to each bit of a digital video signal, and charges stored by the plurality of capacitive elements are supplied to the pixel electrodes according to a timing signal. A charge transfer transistor,
A display device comprising: 2. The display device according to claim 1, further comprising a refresh transistor that initializes a voltage of the pixel electrode before the charge transfer transistor supplies the charge to the pixel electrode. 3. The display device according to claim 1, further comprising a plurality of pixel selection transistors that supply each bit signal of a digital video signal to each capacitance element according to a scanning signal. 4. A plurality of drain signal lines for supplying a digital video signal are provided, and the pixel selection transistor supplies a digital video signal of each bit from the drain signal line to each of the capacitive elements according to a scanning signal. The display device according to claim 3, wherein: 5. The display device according to claim 4, further comprising a signal changeover switch for switching between and supplying either a digital video signal or an analog video signal to the drain signal line. 6. A display device having a plurality of pixels,
Pixel electrodes, a plurality of drain signal lines for supplying digital video signals, a plurality of capacitive elements whose capacitance values are weighted corresponding to the bits of the digital video signals, and the pixels according to a first timing signal. A refresh transistor for initializing the electrode voltage to a predetermined level,
A charge transfer transistor for supplying charges accumulated in the plurality of capacitive elements to the pixel electrode according to a second timing signal, and supplying an analog video signal according to the digital video signal to the pixel electrode. A display device which is characterized by performing display. 7. The refresh transistor responds to a first timing signal before the charge transfer transistor supplies the charge accumulated in the plurality of capacitive elements to the display element in response to a second timing signal. 7. The display device according to claim 6, wherein the voltage of the pixel electrode is initialized to a predetermined level. 8. The display device according to claim 6, further comprising a signal changeover switch that switches and supplies either a digital video signal or an analog video signal to the drain signal line. 9. A display device having a plurality of pixels,
For each of the pixels, an EL element, an EL drive transistor that controls a current flowing through the EL element, a plurality of capacitive elements that store electric charges according to each bit of a digital video signal, and a plurality of capacitive elements A display device, comprising: a charge transfer transistor that supplies a charge to a control gate of the EL drive transistor according to a timing signal. 10. The display device according to claim 9, further comprising a refresh transistor for initializing the voltage of the gate before the charge transfer transistor supplies the charge to the gate of the EL drive transistor. 11. A plurality of pixel selection transistors for supplying each bit signal of a digital video signal to each of the capacitance elements in accordance with a scanning signal.
Display device according to. 12. A plurality of drain signal lines for supplying a digital video signal are provided, and the pixel selection transistor supplies each bit signal from the drain signal line to each of the capacitive elements according to a scanning signal. Claim 1
1. The display device according to 1. 13. The signal changeover switch according to claim 12, wherein the drain signal line is provided with a signal changeover switch for changing over and supplying either a digital video signal or an analog video signal.
Display device described.