JP2002099254A - External driving circuit of planar display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size and the cost of an external driving circuit of a planar display device, in which a pixel section and a peripheral driving circuit are integrally formed on a same substrate, by simplifying the peripheral circuit of positive/negative DACICs. SOLUTION: A VCC/2 potential to be supplied to a positive DACIC 111 and a negative DACIC 112 and a Vcom potential to be supplied to an opposing electrode 3 are supplied from a common Vcom signal generating circuit 114.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external drive circuit for a flat display device such as a liquid crystal display device, and more particularly, to an external drive circuit for a liquid crystal display device in which a pixel portion and a peripheral drive circuit are integrally formed on the same substrate. Circuit.

[0002]

2. Description of the Related Art In recent years, a flat display device represented by a liquid crystal display device has been adopted as a display device of various devices because of its low power consumption in addition to being thin and lightweight. In particular, p-Si (polysilicon) as a driving element
In the case of using a TFT, since a pixel portion and a peripheral driver circuit can be formed integrally on a glass substrate, a compact external shape and a lighter weight are realized despite high definition.

On the other hand, in a liquid crystal display device, if the video signal applied to the liquid crystal layer is always unipolar, a problem such as deterioration of the liquid crystal layer occurs. Therefore, the polarity of the video signal to be written into the pixel is inverted at the frame period. That is, a so-called polarity inversion drive is performed. For this reason, two types of D / A converters for converting a positive or negative digital video signal supplied from an external circuit into an analog video signal are prepared for a positive signal and a negative signal. These D / A converters,
The control IC, the Vcom circuit, and the like are arranged on a drive circuit board as an external drive circuit. The digital video signal output from the control IC is converted into an analog video signal by a D / A converter, and then supplied to a display panel through a flexible wiring board or the like.

[0004]

By the way, different power supply voltages are applied to the D / A converter for positive signal (hereinafter referred to as positive DACIC) and the D / A converter for negative signal (hereinafter referred to as negative DACIC). Supplied.

Here, the power supply voltage of an external drive circuit for supplying a video signal to a liquid crystal panel will be briefly described. FIG.
1 is a circuit configuration diagram of a positive and negative DACIC and its peripheral circuits. In FIG. 5, the power supply voltage of the positive DACIC 11 is V
Assuming CC, the GND voltage becomes VCC / 2. When the power supply voltage of the negative DACIC 12 is VCC / 2, GND
The voltage becomes 0V. Therefore, each analog video signal output (Vsi
g) is a signal having a symmetrical amplitude with VCC / 2 as the central potential (Vsig / C). Also, positive / negative DACIC
The gray scale display potential of the video signal output from is determined by the resistance division ratio of the VREF circuit (video signal gradation reference voltage generation circuit) 13 and the resistance division ratio inside the positive / negative DACIC, and the resistance value is Vsig / C. Is a symmetrical value with respect to. Therefore, in the VREF circuit 13, the resistance R
1 = R4 and R2 = R3.

On the other hand, two types of power supply voltages, VCC and VCC / 2, are required to drive the positive / negative DACIC. Of these, VCC is supplied from a power supply circuit (not shown), and VCC / 2 is generated by a VCC / 2 power supply generation circuit 14 and supplied to the positive / negative DACIC. The Vcom signal supplied to the counter electrode is generated by the Vcom circuit 15, and its value is usually about 0.2 V lower than VCC / 2, though it depends on the characteristic variation of the liquid crystal panel.

As described above, in the conventional external drive circuit, the peripheral circuit of the positive / negative DACIC has the VCC /
Two linear regulator circuits, ie, a two-power generation circuit 14 and a Vcom circuit 15, are required, and further downsizing is achieved.
It was difficult to reduce the cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide a flat panel display device in which the peripheral circuits of the positive / negative DACIC are simplified, and the size and cost of the external drive circuit are reduced.

[0009]

In order to achieve the above object, according to the first aspect of the present invention, there is provided a control circuit for controlling at least the timing of a digital video signal and a logic signal inputted from the outside, and an output from the control circuit. Digital video signal converted to analog video signal
And a second D / A conversion circuit, and a power supply circuit for supplying a power supply voltage input from the outside to the control circuit and the first and second D / A conversion circuits, and a plurality of scanning lines and signals arranged in a matrix. A first substrate including a line, a switch element disposed at each intersection of the scanning line and the signal line, and a pixel electrode connected to the switch element; and a second substrate including a counter electrode facing the pixel electrode; An external drive circuit that supplies the analog video signal and the logic signal to a flat display device including a light modulation layer held between the substrates and a drive circuit for each of the scanning line and the signal line. An intermediate potential generation circuit for generating an intermediate potential of a power supply voltage supplied to the 1D / A conversion circuit and the second D / A conversion circuit, and a counter electrode potential for generating a counter electrode potential supplied to the counter electrode Characterized in that in common and formed circuit.

According to a second aspect of the present invention, in the first aspect, the first D / A conversion circuit and the second D / A conversion circuit each include a video signal gradation reference voltage generation circuit for controlling a gradation display potential of a video signal. The first D / A conversion circuit and the second D / A
The potential difference between the center potential of the analog video signal output from the conversion circuit and the counter electrode potential is calculated by dividing the potential division ratio of the video signal gradation reference voltage generation circuit by the first D / A conversion circuit and the second D / A conversion circuit. Is set to an optimum value.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a case where an external drive circuit of a flat display device according to the present invention is applied to an external drive circuit of a liquid crystal display device having an active matrix type liquid crystal panel using p-Si TFTs will be described. I do.

FIG. 3 is a block diagram showing the overall configuration of the liquid crystal display device according to this embodiment. The liquid crystal display device 100 includes a liquid crystal panel 1 built in a peripheral drive circuit.
01, a drive circuit board 102 for supplying an analog video signal to the liquid crystal panel 101, and an FPC 106 for electrically connecting these components.

The drive circuit board 102 includes a control IC 103, a positive DACIC 111, a negative DACIC 112, a VREF circuit 113, a Vcom signal generation circuit 114, and a power supply circuit 115 as external drive circuits. The FPC 107 connects the drive circuit board 102 to, for example, a processor of a PC (personal computer).

FIG. 4 is a circuit diagram of the liquid crystal panel 101 and its peripheral driving circuit. The liquid crystal panel 101 includes a pixel portion 110, and a scanning line driving circuit 104 and a signal line driving circuit 105 for driving the pixel portion 110.

The pixel section 110 includes a plurality of pixels 1 arranged in a matrix. Each pixel 1
Is composed of a pixel electrode 2, a counter electrode 3, and a liquid crystal layer 4 held between these electrodes. Writing of a video signal to each pixel electrode 2 is controlled by a TFT 5 as a switch element. The gate of each TFT 5 is commonly connected to the scanning lines G1, G2,... Gn for each row, and the drain is connected to the signal lines D1, D2,. The source is connected to the pixel electrode 2. Also, all pixels 1
Are commonly connected to a Vcom signal generation circuit 114 described later. In FIG. 4, the auxiliary capacitance and the auxiliary capacitance line are omitted.

The scanning line drive circuit 104 is constituted by a circuit including a shift register (not shown), a level shifter, and a buffer. The scanning line driving circuit 104 outputs a row selection signal to each of the scanning lines G1, G2,... Gn based on a vertical start signal STV and a vertical clock signal CKV supplied as logic signals from the control IC 103.

The signal line driving circuit 105 includes a driving circuit board 1
02 to the signal line D1,
Dm, and a sample-hold circuit (not shown) for supplying Dm, and a shift register (not shown) for controlling the operation timing of the sample-hold circuit. The signal line drive circuit 105 includes a control I
The horizontal start signal STH and the horizontal clock signal CKH are supplied as logic signals from C103,
Analog video signals are supplied from the ACIC 111 and the negative DACIC 112.

The TFT 5, the pixel electrode 2, the scanning line driving circuit 104, and the signal line driving circuit 105 are integrally formed on an insulating substrate 16 as shown in FIG. Further, the scanning line driving circuit 104 and the signal line driving circuit 105 are constituted by p-Si TFTs.

Embodiment 1 FIG. 1 is a circuit configuration diagram of a positive and negative DACIC and its peripheral circuits in Embodiment 1, and the same parts as those in FIG. 3 are denoted by the same reference numerals.

In the first embodiment, the Vcom signal output from the Vcom signal generation circuit 114 is supplied to the counter electrode (3) (not shown) and the positive DACIC 11
1 and the negative power supply voltage of the DACIC 112. Here, since the potential of the Vcom signal is VCC / 2, it is necessary to adjust the potential difference. Therefore, the resistance values of the resistors R1 to R4 of the VREF circuit 113 are set, and the center potential (Vsig / C) of the video signal is set.
And the potential difference between the Vcom signal and the Vcom signal are optimized. The first embodiment is used particularly when the potential of the Vcom signal is not individually adjusted.

Embodiment 2 FIG. 2 is a circuit configuration diagram of a positive and negative DACIC and its peripheral circuits in Embodiment 2, and the same parts as those in FIG. 1 are denoted by the same reference numerals.

In the second embodiment, as in the first embodiment, V
The Vcom signal output from the com signal generation circuit 114 is supplied to a counter electrode (3) (not shown).
VCC / of positive DACIC111 and negative DACIC112
It is also supplied as two power supply voltages.

The difference from the first embodiment is that the potential of the Vcom signal can be adjusted individually. For this,
The VREF circuit 113 is wired so as not to be supplied with the Vcom signal. In addition, the positive DACIC 111 and the negative D
Since a difference occurs in the power supply voltage supplied to the ACIC 112, the potential of the positive DACIC 111 is reduced by lowering the potential of VCC by an element that causes a voltage drop of 1 V or less as a potential control circuit, for example, a Schottky barrier diode 116.
And the power supply voltage supplied to the negative DACIC 112 is controlled to be substantially the same.

In the circuit configuration of each of the above-described embodiments, the two linear circuits having close potentials, that is, the VCC / 2 power generation circuit 14 and the Vcom circuit 15 shown in FIG. The number of regulator circuits can be reduced to one.

[0025]

As described above, according to the flat panel display according to the present invention, the VCC / 2 power generation circuit and the Vc
By sharing the same om circuit, the number of linear regulator circuits conventionally required two can be reduced to one, so that the size and cost of the external drive circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of positive and negative DACICs and peripheral circuits according to a first embodiment.

FIG. 2 is a circuit configuration diagram of positive and negative DACICs and peripheral circuits according to a second embodiment.

FIG. 3 is a block diagram showing the overall configuration of the liquid crystal display device according to the embodiment.

FIG. 4 is a circuit configuration diagram of a liquid crystal panel and its peripheral driving circuit.

FIG. 5 is a circuit configuration diagram of positive and negative DACICs and peripheral circuits thereof.

[Explanation of symbols]

100: liquid crystal display device, 101: liquid crystal panel, 103:
Control IC 104, scanning line driving circuit 105
Signal line drive circuit, 111: positive DACIC, 112: negative D
ACIC, 113 VREF circuit, 114 Vcom signal generation circuit, 115 power supply circuit, 116 Schottky barrier diode

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA16 NA31 NA53 NA80 NC03 NC18 NC22 NC25 NC34 NC90 ND38 ND49 ND54 NE10 5C006 AA16 AF78 AF83 BB16 BF25 BF43 FA41 FA51 5C080 AA10 BB05 DD22 DD27 FF03 FF11 JJ03 JJ06

Claims (2)

[Claims] 1. A control circuit for controlling at least timing of a digital video signal and a logic signal input from the outside, and first and second converters for converting a digital video signal output from the control circuit into an analog video signal.
A plurality of scanning lines and signal lines arranged in a matrix, comprising: a D / A conversion circuit; and a power supply circuit for supplying a power supply voltage input from the outside to the control circuit and the first and second D / A conversion circuits. A first element including a switch element disposed at each intersection of the scanning line and the signal line, and a pixel electrode connected to the switch element;
For a flat display device including a substrate, a second substrate including a counter electrode facing the pixel electrode, a light modulation layer held between the substrates, and respective driving circuits for the scanning lines and the signal lines. An external drive circuit that supplies the analog video signal and the logic signal, wherein an intermediate potential generation circuit that generates an intermediate potential of a power supply voltage supplied to the first D / A conversion circuit and the second D / A conversion circuit; An external drive circuit for a flat panel display device, wherein a common electrode potential generation circuit for generating a common electrode potential supplied to an electrode is used in common. 2. The first D / A conversion circuit and the second D / A conversion circuit.
The conversion circuit includes a video signal gradation reference voltage generation circuit that controls a gradation display potential of the video signal. The conversion circuit includes a central potential of an analog video signal output from the first D / A conversion circuit and the second D / A conversion circuit. The potential difference between the common electrode potential and the potential division ratio of the video signal gray scale reference voltage generation circuit is determined by dividing the potential difference between the first potential and the first potential.
2. The external drive circuit according to claim 1, wherein the resistance division ratio of the D / A conversion circuit and the second D / A conversion circuit is set to an optimum value.