KR100459624B1 - Display device - Google Patents

Abstract

Provided is a display device in which a wiring area of a display pixel is reduced to enable multi-gradation display by miniaturization of a pixel and multi-bit of a holding circuit. The wiring area is reduced by sharing the power supply line LVDD for supplying the power supply voltage to the holding circuit 110 and the storage capacitor line SCL to which one electrode of the storage capacitor 85 is connected. The storage capacitor line SCL is disposed in parallel with the gate signal line 51 in the display pixel. The power supply lines of the inverter circuits INV1 and INV2 constituting the holding circuit 110 extend in a direction crossing the storage capacitor line SCL, and are connected to the storage capacitor line SCL. The level of the common storage capacitor line SCL is fixed at a power supply voltage (for example, 5V).

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly to a display device suitable for use in a portable display device.

In recent years, portable display devices, for example, portable televisions, mobile phones, and the like, have been demanded in response to market demand. In response to these demands, research and development have been actively conducted to cope with the miniaturization, light weight, and power consumption of display devices.

5 is a circuit configuration diagram of one display pixel of the liquid crystal display according to the prior art. On the insulating substrate (not shown), the gate signal line 51 and the drain signal line 61 are formed to cross each other, and the pixel select thin film transistor 72 connected to both signal lines 51 and 61 near the intersection. Is installed. Hereinafter, the thin film transistor is abbreviated as TFT. The source 11s of the pixel selection TFT 72 is connected to the display electrode 80 of the liquid crystal 21.

In addition, a storage capacitor 85 for maintaining the voltage of the display electrode 80 for one field period is provided, and one terminal 86 of the storage capacitor 85 is a source of the pixel selection TFT 72. 11 s) and a potential common to each display pixel is applied to the other electrode 87.

Here, when the scan signal (H level) is applied to the gate signal line 51, the pixel select TFT 72 is turned on, and the analog image signal is transmitted from the drain signal line 61 to the display electrode 80. It is held at the auxiliary dose 85. A video signal voltage applied to the display electrode 80 is applied to the liquid crystal 21, and the liquid crystal 21 is oriented according to the voltage to obtain a liquid crystal display.

Therefore, liquid crystal display can be performed irrespective of moving images and still images. In the case of displaying a still image on such a liquid crystal display device, for example, an image of a battery is displayed as a residual amount display of a battery for driving the cellular phone on a part of the liquid crystal display unit of the cellular phone.

However, in the liquid crystal display of the above-described configuration, even when displaying a still image, the pixel selection TFT 72 is turned on with the scanning signal and the video signal is rewritten to each display pixel as in the case of displaying a moving image. Needs to be.

Therefore, the driver circuit for generating drive signals, such as scan signals and video signals, and the external LSI for generating various signals for controlling the operation timing of the driver circuit always operate, and therefore have always consumed large power. For this reason, there existed a drawback that the usable time becomes short for the mobile telephone etc. which have a limited power supply.

In contrast, a liquid crystal display device having a static memory in each display pixel is disclosed in Japanese Patent Laid-Open No. Hei 8-194205. Referring to a part of Japanese Patent Application Laid-Open No. Hei 8-194205, this liquid crystal display device uses a memory of a form in which two-stage inverters INV1 and INV2 are fed back, that is, a static type memory, as shown in FIG. 6. By using it, power consumption is reduced.

Here, according to the binary digital video signal held in the static memory, the switch element 24 controls the resistance value between the reference line Vref and the display electrode 80 to adjust the bias state of the liquid crystal 21. On the other hand, the AC signal Vcom is input to the common electrode. Ideally, the apparatus is not required to rewrite into the memory unless there is a change in the display image such as a still image.

As described above, the conventional liquid crystal display device is suitable for displaying a full-color moving picture corresponding to an analog video signal. On the other hand, a liquid crystal display device having a static memory for holding a digital video signal is suitable for displaying a low gray level still image and reducing power consumption.

However, since both liquid crystal display devices differ in video signal sources, both display devices cannot be realized at the same time.

Accordingly, the present applicant has proposed a display device that can select two types of displays, an analog display and a digital display. Hereinafter, the outline of this display device will be described with reference to FIG. 7. 7 is a circuit diagram showing the configuration of one display pixel of the display device.

In the vicinity of the intersection of the gate signal line 51 and the drain signal line 61 disposed on an insulating substrate (not shown), a circuit selection circuit 40 consisting of a P-channel TFT 41 and an N-channel 42 is formed. Is installed. Both drains of the TFTs 41 and 42 are connected to the drain signal line 61, and these gates are connected to the circuit select signal line 88. One of the TFTs 41 and 42 is turned on in accordance with the selection signal from the circuit selection signal line 88. In addition, the circuit selection circuit 43 is provided in pairs with the circuit selection circuit 40.

In addition, adjacent to the circuit selection circuit 40, a pixel selection circuit 70 composed of the N-channel TFT 71 and the N-channel TFT 72 is disposed. The TFTs 71 and 72 are turned on in accordance with the scanning signal from the gate signal line 51.

In the display pixel, a storage capacitor 85 is provided to hold an analog video signal for one field period. One electrode 86 of the storage capacitor 85 is connected to the source 71s of the TFT 71. The other electrode 87 is connected to the storage capacitor line SCL common to all the display pixels, and a fixed bias voltage is supplied.

Between the storage capacitor 85 and the liquid crystal 21, a P-channel TFT 44 of the circuit selection circuit 43 is provided, and the on / off state is simultaneously with the TFT 41 of the circuit selection circuit 43. It is configured to be. In addition, the holding circuit 110 and the signal selecting circuit 120 are provided between the pixel selection TFT 72 and the display electrode 80 of the liquid crystal 21.

The holding circuit 110 consists of the 1st and 2nd inverter circuits INV1 and INV2 which comprise a positive feedback loop. In the digital display mode, when the potential of the circuit selection signal line 88 becomes "H" and the scanning signal of the gate signal line 51 becomes "H", the video signal input from the drain line 61 is a sustain circuit. Is written at 110.

The signal selection circuit 120 is a circuit for selecting a signal in accordance with a digital video signal held by the holding circuit 110 and is composed of two N-channel TFTs 121 and 122. Since complementary output signals from the holding circuit 110 are applied to the gates of the TFTs 121 and 122, respectively, the TFTs 121 and 122 are complementarily turned on / off. When the TFT 122 is turned on, the signal A (black signal) is selected. When the TFT 121 is turned on, the signal B (white signal) is selected, and the TFT 45 of the circuit selection circuit 43 is selected. By this, it is supplied to the display electrode 80 which applies a voltage to the liquid crystal 21.

Therefore, according to the configuration of the above-described display device, it is possible to switch between the conventional analog display mode and the digital display mode (low power consumption, still image correspondence).

However, since wiring of the power supply line LVDD supplying the power supply voltage to the holding circuit 110 and the ground line LVSS supplying the ground voltage is performed, the wiring area becomes large and the pixel circuit cannot be miniaturized. Therefore, increasing the number of bits of the holding circuit 110 causes the circuit to be enlarged, making it difficult to advance the high precision and the multi-gradation of pixels.

1 is a circuit diagram of a liquid crystal display device according to a first embodiment of the present invention.

2 is a circuit diagram of a liquid crystal display according to a second exemplary embodiment of the present invention.

3 is a circuit diagram of a liquid crystal display according to a third exemplary embodiment of the present invention.

4 is a timing diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is another circuit configuration diagram of a liquid crystal display device according to the prior art.

6 is another circuit configuration diagram of a liquid crystal display device according to a conventional example.

7 is a circuit configuration diagram of a display device in which analog display and digital display can be selected.

<Explanation of symbols for main parts of drawing>

21: liquid crystal

40: circuit selection circuit

43: circuit selection circuit

51: gate signal line

60: drain driver

61: drain signal line

70: pixel selection circuit

85: auxiliary capacity

110: holding circuit

120: signal selection circuit

The present invention has been made in view of the above-mentioned problems. First, in a display device that can switch between an analog display mode and a digital display mode, a power supply line LVDD and a storage capacitor 85 for supplying a power supply voltage to the holding circuit 110 are provided. The storage capacitor line SCL to which one of the electrodes is connected is shared (see FIG. 1). As a result, since the wiring area is reduced, the multi-gradation display by the miniaturization of the pixel and the multi-bit of the holding circuit 110 becomes possible.

Secondly, in the display device which can switch between an analog display mode and a digital display mode, the ground line LVSS which supplies a ground voltage to the holding circuit 110, and the storage capacitor line SCL which connected one electrode of the storage capacitor 85 are shared. One (see Fig. 2). As a result, the wiring area is similarly reduced, and the multi-gradation display by the miniaturization of the pixel and the multi-bit of the holding circuit 110 becomes possible.

Third, in the display device which can switch between an analog display mode and a digital display mode, the ground signal LVSS which supplies a ground voltage to the holding circuit 110 is scanned from the gate signal line 51b corresponding to the holding circuit 110, and a scanning signal. Is connected to the gate signal line 51a at the front end on the basis of the order in which is applied (see FIG. 3).

The present invention relates to gate signal lines a, b,... The scanning signal (a pulse of &quot; H &quot; level) is sequentially applied to each horizontal period, and the respective gate signal lines a, b,... Note that the signal returns to the &quot; L &quot; level (ground voltage) after the end of the one-horizon period in which the scan signal is applied, and the front end of the sustain circuit 110 belonging to an arbitrary display pixel is terminated. By connecting to the gate signal line, the display pixel to which the holding circuit 110 belongs is selected by the scanning signal, and the ground voltage is always supplied to the holding circuit when the digital video signal can be written. As a result, the dedicated ground line LVSS can be reduced, whereby the wiring area can be reduced, thereby enabling multi-gradation display by miniaturization of the pixel and multi-bit of the holding circuit 110.

<Example>

Next, a display device according to an embodiment of the present invention will be described with reference to the drawings. 1 shows a circuit configuration of the display device according to the first embodiment. Although one display pixel is shown in FIG. 1 for simplicity of explanation, in the actual display device, many display pixels of such a structure are arrange | positioned in matrix form. In addition, in FIG. 1, the same code | symbol is attached | subjected about the same part as FIG. 7, and the description is abbreviate | omitted.

In Fig. 1, in accordance with the selection signal SW from the circuit selection signal line 88, the circuit selection circuits 40 and 43 switch, so that the first display circuit (for analog display) and the sustain circuit (having the auxiliary capacitance 85) One of the second display circuit (for digital display) including the 110 and the signal selection circuit 120 is selected.

In this embodiment, the wiring area is reduced by sharing the power supply line LVDD for supplying the power supply voltage to the holding circuit 110 and the storage capacitor line SCL to which one electrode of the storage capacitor 85 is connected. The storage capacitor line SCL is disposed in parallel with the gate signal line 51 in the display pixel. The power supply lines of the inverter circuits INV1 and INV2 constituting the holding circuit 110 extend in a direction crossing the storage capacitor line SCL, and are connected to the storage capacitor line SCL. The level of the common storage capacitor line SCL is fixed at a power supply voltage (for example, 5V).

2 shows a circuit configuration of the display device according to the second embodiment. Although one display pixel is shown in FIG. 2 for simplicity of explanation, in the actual display device, many display pixels of such a structure are arrange | positioned in matrix form. In addition, in FIG. 2, the same code | symbol is attached | subjected about the same part as FIG. 7, and the description is abbreviate | omitted.

In Fig. 2, in accordance with the selection signal SW from the circuit selection signal line 88, the circuit selection circuits 40 and 43 switch, so that the first display circuit (for analog display) and the sustain circuit (having the auxiliary capacitance 85) One of the second display circuit (for digital display) including the 110 and the signal selection circuit 120 is selected. This point is the same as in the first embodiment.

In this embodiment, the wiring area is reduced by sharing the ground line LVSS for supplying the ground voltage to the holding circuit 110 and the storage capacitor line SCL to which one electrode of the storage capacitor 85 is connected. The storage capacitor line SCL is disposed in parallel with the gate signal line 51 in the display pixel. The ground lines LVSS of the inverter circuits INV1 and INV2 constituting the holding circuit 110 extend in a direction crossing the storage capacitor line SCL and are connected to the storage capacitor line SCL. The level of the common storage capacitor line SCL is fixed to ground voltage (eg 0V).

The level of the ground line LVSS is not limited to 0 V, but may be a wiring having a lower potential than the power supply line LVDD.

3 shows a circuit configuration of the display device according to the third embodiment. In FIG. 3, two adjacent display pixels 200 and 201 are shown for simplicity of explanation. However, in the actual display device, a plurality of display pixels having such a configuration are arranged in a matrix. 3, the same code | symbol is attached | subjected about the same part as FIG. 7, and the description is abbreviate | omitted.

In response to the selection signal SW from the circuit selection signal line 88, the circuit selection circuits 40 and 43 switch so that each display pixel 200, 201 has a first display circuit having an auxiliary capacitor 85 (analog). One of the second display circuit (for digital display) including the display) and the holding circuit 110 and the signal selection circuit 120 is selected.

In the present embodiment, the ground line LVSSb for supplying the ground voltage to the inverter circuits INV1 and INV2 of the sustain circuit 110b in the display pixel 201 has a gate preceding the gate signal line 51b corresponding to the sustain circuit 110b. It is connected to the signal line 51a. Similarly, the ground line LVSSa for supplying the ground voltage to the inverter circuits INV1 and INV2 of the sustain circuit 110a in the display pixel 200 has the gate signal line (the front end of the gate signal line 51a corresponding to the sustain circuit 110b). Not shown).

Next, the driving method of the display device according to the third embodiment will be described with reference to FIGS. 3 and 4. 4 is a timing diagram when the digital display mode is selected. The same driving method is also applied to the display devices according to the first and second embodiments.

(1) analog display mode

When the circuit selection signal line 88 is set to "L", the TFTs 41 and 44 of the circuit selection circuits 40 and 43 are turned on. The sampling transistor SP (not shown) is turned on in accordance with the sampling signal based on the horizontal start signal STH, and the analog video signal is supplied to the drain signal line 61. Further, the scan signal is supplied to the gate signal line 51 based on the vertical start signal STV.

When the pixel select TFT 72 is turned on in response to the scan signal, the analog image signal is transmitted from the drain signal line 61 to the display electrode 80 and held in the storage capacitor 85. A video signal voltage applied to the display electrode 80 is applied to the liquid crystal 21, and the liquid crystal 21 is oriented according to the voltage to obtain a liquid crystal display. In this analog display mode, it is suitable for displaying full-color moving images.

(2) digital display mode

When the potential of the circuit selection signal line 88 is set to "H", the TFTs 41 and 44 of the circuit selection circuits 40 and 43 are turned off, and the TFTs 42 and 45 are turned on. As a result, the holding circuit 110 is operable.

Further, start signals STV and STH are respectively input to the gate driver and the drain driver (not shown) from the driver scan LSI (not shown) mounted on the externally mounted circuit board. Accordingly, the sampling signal is generated sequentially. In accordance with each sampling signal, sampling transistors SP1, SP2, ... connected to the respective drain signal lines 61 are provided. SPn is turned on in order, and the digital video signal is sampled and supplied to each drain signal line 61.

Here, the gate signal line 51 to which the first row, that is, the scanning signal G1 is applied, will be described. Display pixels P11, P12, ... connected to gate signal line 51 by scanning signal G1; Each TFT of P1n (not shown) is turned on for one horizontal scanning period.

When attention is paid to the display pixels P11 in the first row and the first column, the digital video signal S11 (drain signal D1) sampled by the sampling signal SP1 is input to the drain signal line 61. Then, when the scan signal G1 becomes "H" and the TFT 72 is turned on, the digital video signal S11 is written into the holding circuit 110.

When the display pixels P12 in the first row and the second column are focused, the digital video signal S12 (drain signal D2) sampled by the sampling signal SP2 is input to the drain signal line 61. The same applies to the following.

The signal held by this holding circuit 110 is input to the signal selection circuit 120, and the signal selection circuit 120 selects the signal A or the signal B, and the selected signal is transmitted to the display electrode 80. Is applied, and the voltage is applied to the liquid crystal 21. In this way, by sequentially scanning from the gate signal line 51 to the gate signal line 51 of the last row, writing of one screen (one field period) is completed.

Here, when the scan signal Gn + 1 ("H") is supplied to the gate signal line 51b connected to the pixel selection TFT 72 of the display pixel 201 of FIG. 3, the drain signal line 61 is supplied to the sustain circuit 110b. ) Is inputted into the digital video signal.

At this time, the level of the gate signal line 51a connected to the pixel selection TFT 72 of the adjacent display pixel 200 is set to "L" (ground voltage). Therefore, the ground voltage is supplied to the inverter circuits INV1 and INV2 of the holding circuit 110b, and the holding circuit 110b operates normally.

In the present embodiment, the ground line LVS S for supplying the ground voltage to the sustain circuit 110b is connected to the gate signal line 51a one preceding the gate signal line 51b corresponding to the sustain circuit 110b. It is obvious that the connection to two or more front gate signal lines (not shown) can achieve the same effect, so that it is included in the scope of the present patent.

Thereafter, display (display of the still image) is performed based on the data held in the holding circuit 110. The power supply voltage for driving this sustain circuit is supplied to the sustain circuit 110, the counter electrode voltage V _C0M (signal A) is applied to the counter electrode, and the liquid crystal display panel 100 is normally white (NW). To signal A, a voltage V _C0M having the same potential as that of the counter electrode 32 is applied, and to the signal B, a display voltage for black display is applied. By doing so, one screen can be maintained and displayed as a still image.

At this time, when &quot; H (high) &quot; is input to the holding signal 110 as a digital video signal to the drain signal line 61, the &quot; L &quot; Since the first TFT 121 is turned off and "H" is input to the other second TFT 122, the second TFT 122 is turned on. Accordingly, the signal B is selected, and the voltage of the signal B is applied to the liquid crystal. That is, since the signal B is applied and the liquid crystal is oriented by the electric field, the display can be observed by the black display in the display panel of NW.

When "L" is input to the holding circuit 110 as a digital video signal to the drain signal line 61, since "H" is input to the first TFT 121 in the signal selection circuit 120, the first TFT is used. Since 121 is turned on and "L" is input to the other second TFT 122, the second TFT 122 is turned off. Then, signal A is selected and the voltage of signal A is applied to liquid crystal. That is, since the same voltage as that of the counter electrode 32 is applied, no electric field is generated, and the liquid crystal is not aligned, the display can be observed by the white display in the display panel of NW.

In this way, it is possible to display as a still image by writing and retaining one screen, but since the driving of each driver and the LSI for driver scanning is stopped, the power consumption can be reduced by that much.

In the above-described first, second, and third embodiments, the holding circuit 110 is configured to input a digital video signal of 1 bit, but the present invention is not limited thereto. According to the present invention, since the wiring area can be reduced and the pixel circuit can be miniaturized, it is useful to apply to a holding circuit of a multi-bit configuration in which a plurality of digital video signals are written and held. Thereby, multi-gradation display can be performed with high precision.

According to the display device of the present invention, firstly, in a display device which can switch between an analog display mode and a digital display mode, since a power supply line and a storage capacitor line supplying a power voltage to a holding circuit holding a digital video signal are shared, The wiring area is reduced, and the multi-gradation display by the miniaturization of the pixel and the multi-bit of the holding circuit can be realized.

Secondly, since the ground line for supplying the ground voltage to the sustain circuit and the storage capacitor line to which one of the storage capacitors are connected are shared, the wiring area is similarly reduced, resulting in miniaturization of pixels and multiple bits of the sustain circuit 110. Multi-gradation display is enabled.

Third, since the ground line for supplying the ground voltage to the sustain circuit is connected to the gate signal line in the preceding stage based on the order in which the scan signal is applied from the gate signal line corresponding to the sustain circuit, the dedicated ground line necessary for the conventional circuit can be reduced. As a result, the wiring area can be reduced, and the multi-gradation display can be realized by miniaturization of the pixel and multi-bit of the holding circuit 110.

Claims (6)

A plurality of gate signal lines arranged in one direction on the substrate, A display device comprising a plurality of drain signal lines arranged in a direction crossing the gate line, the display pixel being selected by a scan signal from the gate signal line and supplied with an image signal from the drain signal line in a matrix form. , A display electrode disposed in the display pixel; A first display circuit having a storage capacitor for sequentially holding video signals which are sequentially input, and for sequentially supplying the video signals to the display electrodes; A second display circuit disposed in correspondence with the display pixel to hold an image signal, the second display circuit supplying a voltage according to the signal held by the retention circuit to the display electrode; A circuit selection circuit for selecting the first and second display circuits according to a circuit selection signal, A display device characterized by using a high potential power supply line for supplying a power supply voltage to said sustain circuit and a storage capacitor line to which one electrode of said storage capacitor is connected. The method of claim 1, The holding circuit includes a positive feedback two-stage inverter circuit, and the power supply line on the high potential side of the two-stage inverter circuit is connected to the storage capacitor line. A plurality of gate signal lines arranged in one direction on the substrate, A display device comprising a plurality of drain signal lines arranged in a direction crossing the gate line, the display pixel being selected by a scan signal from the gate signal line and supplied with an image signal from the drain signal line in a matrix form. , A display electrode disposed in the display pixel; A first display circuit having a storage capacitor for sequentially holding video signals which are sequentially input, and for sequentially supplying the video signals to the display electrodes; A second display circuit disposed in correspondence with the display pixel to hold an image signal, the second display circuit supplying a voltage according to the signal held by the retention circuit to the display electrode; A circuit selection circuit for selecting the first and second display circuits according to a circuit selection signal, A display device characterized by using a low potential side power supply line for supplying a ground voltage to said sustain circuit and a storage capacitor line to which one electrode of said storage capacitor is connected. The method of claim 3, The holding circuit includes a positive feedback two-stage inverter circuit, and the power supply line on the low potential side of the two-stage inverter circuit is connected to the storage capacitor line. A plurality of gate signal lines arranged in one direction on the substrate and sequentially applied with a scan signal, a plurality of drain signal lines arranged in a direction crossing the gate line, and a scan signal provided for each display pixel and applied to the gate signal line And a pixel selection transistor for selecting a display pixel according to the display pixel, and a holding circuit disposed in the display pixel and holding a video signal input from the drain signal line, and performing display according to the video signal held in the holding circuit. And a low potential power supply line for supplying a ground voltage to said sustain circuit is connected to a gate signal line at a preceding stage in the order of applying a scan signal from a gate signal line corresponding to the sustain circuit. The method of claim 5, The holding circuit includes a positive feedback two-stage inverter circuit, and the front end of the power supply line on the low potential side of the two-stage inverter circuit based on the order in which the scan signal is applied from the gate signal line corresponding to the holding circuit. And a gate signal line.