JP5023740B2 - Electro-optical device, data signal supply circuit, supply method, and electronic apparatus - Google Patents

Description

  The present invention relates to a technique for minimizing the influence of display quality against changes in switching characteristics of a transistor due to environmental temperature, aging, and the like.

  In recent years, a projector that forms an image using an electro-optical device such as a liquid crystal device and enlarges and projects this reduced image using an optical system is becoming widespread. This projector does not have a function of creating an image by itself, and is supplied with image data (or an image signal) from a host device such as a personal computer or a TV tuner. This image data designates the gradation (brightness) of the pixels arranged in a matrix for each pixel, and is supplied in the form of vertical and horizontal scanning of the pixel arrangement.

Therefore, in the image formation in the electro-optical device, first, the scanning lines are sequentially selected one by one, and secondly, when one scanning line is selected, one (or a plurality of columns) data lines are selected. In general, a dot-sequential (block-sequential) driving method is used, in which a sampling signal for sequentially selecting data is output, and thirdly, a data signal supplied via an image signal line is sampled on a data line according to the sampling signal It is.
When the image is formed, if the sampling signal is not output properly, it may cause display disturbance. Therefore, an enable signal that regulates the output of the sampling signal is supplied to the display panel and monitored. A technique for adjusting the phase of the enable signal supplied to the display panel according to the delay state of the enable signal has been proposed (see Patent Document 1).
JP 2003-157063 A

Incidentally, it is a switching element such as a TFT that samples the data signal supplied to the image signal line in accordance with the sampling signal. In this type of switching element, the switching characteristics vary with environmental temperature and aging. Therefore, even if the sampling signal is properly output by the above technique, if the characteristics of the switching element that samples the data signal on the data line change due to the environmental temperature or the like, the target voltage is correctly sampled on the data line. Display quality will deteriorate.
The present invention has been made in view of the above-described circumstances. The object of the present invention is to affect the display quality even if the characteristics of a switching element that samples a data signal on a data line change due to an environmental temperature or the like. It is an object of the present invention to provide an electro-optical device, a data signal supply circuit, a supply method, and an electronic apparatus that are reduced in number.

In order to achieve the above object, a data signal supply circuit of an electro-optical device according to the present invention is provided in each of an image signal line to which a data signal having a voltage corresponding to a gradation is supplied and a plurality of columns of data lines, A plurality of sampling switching elements for sampling the data signals supplied to the image signal lines respectively on the data lines, and corresponding to the intersections of the plurality of rows of scanning lines and the plurality of columns of data lines, and the scanning lines are selected. A data signal supply circuit of an electro-optical device having a plurality of pixels having gradation according to the voltage of the data signal sampled on the data line, the dummy data line and the image signal line A monitoring switching element for sampling the data signal supplied to the dummy data line, the voltage of the data signal supplied to the image signal line, and the dummy data line. Determining a difference voltage between the sampled voltage to the line, characterized by comprising a correction circuit for correcting, based voltage of the data signal supplied to the image signal line to the voltage difference. According to the present invention, even if the characteristics of the sampling switching element change, the shortage due to the characteristic change is added as a difference voltage to the data signal in advance, so that the influence of the characteristic change can be canceled.

In the present invention, sampling by the monitoring switching element may be executed in a vertical scanning period or a horizontal blanking period. In the present invention, the voltage of the data signal sampled on the dummy data line by the monitoring switching element is not less than two values, and the correction circuit is a low-pass that smoothes the voltage sampled on the dummy data line. A difference between the average voltage of the data signal supplied to the image signal line and the output voltage of the low-pass filter may be obtained as the difference voltage.
Further, in the present invention, the voltage of the data signal is determined by the gradation and polarity of the pixel, and the correction circuit has a lookup table in which the difference voltage is stored in advance according to the gradation and polarity of the pixel. The difference voltage corresponding to the gradation and polarity of the pixel is read from the lookup table, the voltage of the data signal is corrected based on the read difference voltage, and the predetermined gradation and polarity stored in the lookup table The difference voltage may be updated to the difference voltage obtained when the data signal having the predetermined gradation and the predetermined polarity is supplied to the image signal line.
In addition, in the present invention, when there are a plurality of m image signal lines, there are m dummy data lines, m monitoring switching elements, and each of the m monitoring switching elements. Samples the data signals supplied to the m image signal lines to the m dummy data lines, and the correction circuit supplies the data signal supplied to one of the m image signal lines. The voltage of the data signal to be supplied to the one image signal line may be corrected based on the difference voltage between the voltage of the data signal and the voltage obtained by sampling the data signal supplied to the one image signal line. .

  The present invention can be conceptualized not only as a data signal supply circuit of an electro-optical device, but also as a supply method, an electro-optical device, and an electronic apparatus having the electro-optical device. Here, in the case of a concept as an electro-optical device, it may be configured to include a dummy capacitor having one end connected to the dummy data line and the other end connected to a power supply line having a predetermined potential. It is desirable that the time constant of the integration circuit with the dummy data line, the dummy capacitance, and the monitoring switching element is the same as the time constant of the integration circuit with the data line, the parasitic capacitance and the sampling switching element switching element.

  Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment>
FIG. 1 is a block diagram illustrating a configuration of the electro-optical device according to the present embodiment.
As shown in this figure, the electro-optical device 10 includes a control circuit 50 and a liquid crystal display panel 100.
Among these, the liquid crystal display panel 100 is of a peripheral circuit built-in type in which the scanning line driving circuit 130 and the data line driving circuit 140 are built around the display area 100a. In the display area 100a, 1080 scanning lines 112 are provided so as to extend in the row (X) direction, and 1920 data lines 114 are provided so as to extend in the column (Y) direction. The scanning lines 112 are provided so as to be electrically insulated from each other, and the pixels 110 are arranged corresponding to the intersections of the scanning lines 112 of 1080 rows and the data lines 114 of 1920 columns, respectively. Therefore, in this embodiment, the pixels 110 are arranged in a matrix of 1080 vertical rows × 1920 horizontal columns.
In the present embodiment, dummy data lines 115 are provided outside the array region of the pixels 110.

  For convenience of description, the configuration of the pixel 110 will be described with reference to FIG. FIG. 2 shows a total of 4 pixels of 2 × 2 corresponding to the intersection of the i row and the (i + 1) row adjacent to it and the j column and the j column and the (j + 1) column adjacent to the right one column. The structure of is shown. Note that i and (i + 1) are symbols for generally indicating the row in which the pixels 110 are arranged, and are integers of 1 to 1080 in this example. Further, j and (j + 1) are symbols for generally indicating a column in which the pixels 110 are arranged, and in this example, are integers of 1 or more and 1920 or less.

As shown in FIG. 2, each pixel 110 includes an n-channel thin film transistor (hereinafter referred to as “TFT”) 116 and a liquid crystal capacitor 120.
Here, since each pixel 110 has the same configuration, the pixel 110 located in the i-th row and j-th column will be described as a representative example. On the other hand, the source electrode is connected to the data line 114 in the j-th column, and the drain electrode is connected to the pixel electrode 118 which is one end of the liquid crystal capacitor 120. The other end of the liquid crystal capacitor 120 is connected to the counter electrode 108. The counter electrode 108 is common to all the pixels 110, and in this embodiment, a constant voltage LCcom is applied in time.

The liquid crystal display panel 100 has a configuration in which a pair of substrates of an element substrate and a counter substrate are bonded together with a certain gap therebetween, and liquid crystal is sealed in the gap, although not particularly illustrated. Among these, the scanning line 112, the data line 114, the TFT 116, and the pixel electrode 118 are formed on the element substrate together with the scanning line driving circuit 130 and the data line driving circuit 140, while the counter electrode 108 is formed on the counter substrate. These electrode forming surfaces are bonded together with a certain gap so as to face each other. Therefore, in this embodiment, the liquid crystal capacitor 120 is configured by sandwiching the liquid crystal 105 between the pixel electrode 118 and the counter electrode 108.
In this embodiment, if the effective voltage value held in the liquid crystal capacitor 120 is close to zero, the transmittance of light passing through the liquid crystal capacitor is maximized to display white, while the effective voltage value increases. The normally white mode in which the transmittance decreases and finally the black display with the minimum transmittance is set.

In this configuration, a selection voltage is applied to the scanning line 112 to turn on the TFT 116, and the voltage corresponding to the gradation (brightness) is applied to the pixel electrode 118 via the data line 114 and the on-state TFT 116. Is supplied to the liquid crystal capacitor 120 corresponding to the intersection of the scanning line 112 to which the selection voltage is applied and the data line 114 to which the data signal is supplied.
Note that when the scanning line 112 becomes a non-selection voltage, the TFT 116 is turned off (non-conducting). However, in the liquid crystal capacitor 120, the voltage written when the TFT 116 is turned on is held by its capacitance. The

The scanning line driving circuit 130 selects the scanning lines 112 in the first, second, third,..., 1080th row in this order, respectively, and outputs scanning signals G1, G2, G3,. , To supply. Here, the scanning line driving circuit 130 sets the scanning signal to the selected scanning line to the voltage Vdd corresponding to the H level, and the scanning signals to the other scanning lines to the non-selection voltage (ground potential Gnd corresponding to the L level. ).
Although the configuration of the scanning line driving circuit 130 is not particularly described in detail, simply speaking, for example, as shown in FIG. 5, the start pulse Dy supplied at the beginning of the vertical scanning period (F) is changed to the clock signal Cly. Each time the logic level transitions (falling and rising), shift transfer is performed in order, and this shift signal is output as a scanning signal.

The data line driving circuit 140 includes a sampling signal output circuit 142 and n-channel TFTs 144 provided corresponding to the data lines 114, respectively. The sampling signal output circuit 142 outputs sampling signals S1, S2, S3,..., S1920 that sequentially become H level exclusively over the horizontal scanning period in which the scanning line 112 of each row is selected.
The configuration of the sampling signal output circuit 142 is not particularly described in detail, but simply speaking, for example, as shown in FIG. 6, the start pulse Dx supplied at the beginning of the horizontal scanning period (H) is converted into a clock signal. In this configuration, every time the logic level of Clx transitions, shift transfer is performed in order, and this shift signal is output as a sampling signal.
The TFT 144 functions as a sampling switching element, and its source electrode is connected to an image signal line 148 to which a data signal Vid described later is supplied, its drain electrode is connected to the data line 114, and its gate electrode. Is supplied with a sampling signal. Specifically, for example, in the TFT 144 in the j-th column, the drain electrode is connected to the data line 114 in the j-th column, and the sampling signal Sj is supplied to the gate electrode. Therefore, when the sampling signal Sj becomes H level, the TFT 144 in the j-th column is turned on, and the data signal Vid supplied to the image signal line 148 is sampled on the data line 114 in the j-th column. Yes.

Returning to FIG. 1 again, the TFT 145 functions as a switching element for monitoring and is an n-channel type like the TFT 144. Its source electrode is connected to the image signal line 148 and its drain electrode is a dummy. A signal De described later is supplied to the gate electrode connected to the data line 115. Note that the TFT 145 is the TFT 144.
Designed to have the same characteristics as
Here, one end of the dummy capacitor 130 is connected to the drain electrode of the TFT 145, that is, the dummy data line 115, and the other end of the dummy capacitor 130 is grounded to a constant potential, for example, the potential Gnd. Yes.
Here, the TFT 145, the dummy data line 115, and the dummy capacitor 130 are for simulating a wiring route from the TFT 144 to the data line 114 having a parasitic capacitance. Therefore, the time constant due to the TFT 145 (on-resistance), the wiring resistance of the dummy data line 115 and the capacity of the dummy capacitor 130 is the TFT 144 (on-resistance), the wiring resistance of the data line 114 and the parasitic capacitance of the data line 114. It is designed to be the same as the determined time constant. Therefore, the voltage of the signal Mb sampled on the dummy data line 115 when the TFT 145 is turned on may be equated with the voltage sampled on the data line 114 when the TFT 144 is turned on.

  The control circuit 50 controls the scanning line driving circuit 130 and the data line driving circuit 140 and supplies the data signal Vid to the image signal line 148 in accordance with these controls.

FIG. 3 is a block diagram showing a configuration of the control circuit 50.
As shown in this figure, image data Vd is supplied to the control circuit 50 from an upper circuit (not shown) in synchronization with the vertical synchronizing signal Vs, the horizontal synchronizing signal Hs and the clock signal Clk. Here, the image data Vd is digital data that designates the gradation of the pixels 110 of vertical 1080 rows × horizontal 1920 columns by, for example, 8 bits, and as shown in FIG. 4, the vertical is defined by the vertical synchronization signal Vs. Over the scanning period (F), pixels of 1 row 1 column to 1 row 1920 column, 2 rows 1 column to 2 rows 1920 column, 3 rows 1 column to 3 rows 1920 columns, ... 1080 rows 1 columns to 1080 rows 1920 columns In order. At the time of this supply, image data Vd for one row is supplied in the horizontal scanning period (H) defined by the horizontal synchronizing signal Hs, and further, 1 of the clock signal Clk is supplied.
Image data Vd for one pixel is supplied in a cycle.

In FIG. 4, the vertical blanking period Fb is defined as 1080 rows 1 in a certain vertical scanning period.
This is a period from when the image data Vd of the pixels of 920 columns is supplied until the image data Vd of the pixels of 1 row and 1 column is supplied in the next vertical scanning period.
The horizontal blanking period Hb is a period from when image data Vd of 1920 columns of pixels is supplied in a certain horizontal scanning period until image data Vd of one column of pixels is supplied in the next horizontal scanning period. A period.
In the present embodiment, the 8-bit image data Vd specifies “0” in decimal notation to specify black with the lowest gradation, specifies a gradation that becomes brighter as the numerical value increases, and “255” indicates the highest gradation. White color shall be specified. As described above, since the normally white mode is set in the present embodiment, when the white color specified by the gradation value “255” is set, the effective value of the voltage held in the liquid crystal capacitor 120 is close to zero. In the case of black specified by the gradation value “0”, the effective value of the voltage held in the liquid crystal capacitor 120 may be set to the maximum value.

The scanning control circuit 52 outputs start pulses Dx and Dy and clock signals Clx and Cly in synchronization with the vertical synchronizing signal Vs, horizontal synchronizing signal Hs and clock signal Clk, and becomes H level in the vertical blanking period Fb. The signal De and the polarity designation signal Pol for designating the polarity of the write voltage to the pixel 110 are output.
More specifically, when the image data Vd is supplied as shown in FIG.
2 shows a scanning line 112 of the first row in the horizontal scanning period (H) in which the image data Vd of the first row is supplied.
Similarly, the second, third, fourth,..., 1080th scanning lines in the horizontal scanning period (H) during which the second, third, fourth,... 1080th image data Vd is supplied. The scan line drive circuit 13 outputs the start pulse Dy and the clock signal Cly so that 112 is selected.
Control 0.
Further, the scanning control circuit 52 similarly applies the sampling signal S1 to the H level when the image data Vd of the first column is supplied in the horizontal scanning period (H) in which a certain scanning line 112 is selected. The start pulse Dx and the clock signal Clx are set so that the sampling signals S2, S3, S4,..., S1920 are at the H level when the image data Vd in the 2, 3, 4,. The sampling signal output circuit 142 is output and controlled.

The polarity designation signal Pol is a signal for designating the writing polarity of the voltage to the liquid crystal capacitor 120. For example, the polarity designation signal Pol designates the positive polarity when the level is H and the negative polarity when the level is the L level. Here, the positive polarity means a voltage higher than the reference voltage Vc (FIG. 6) set slightly higher than the applied voltage LCcom to the counter electrode 108, and the negative polarity means the reference voltage Vc. Is the lower voltage.
In this embodiment, the writing polarity is based on the voltage Vc. However, the voltage is based on the ground potential Gnd corresponding to the L level of the logic level unless otherwise specified.

Incidentally, the applied voltage LCcom to the counter electrode 108 is set to a lower side than the reference voltage Vc. This is due to the parasitic capacitance between the gate and drain electrodes in the n-channel TFT 116. This is because a push-down occurs in which the potential of the drain (pixel electrode 118) decreases when the state changes from on to off. If the voltage LCcom is matched with the reference voltage Vc, the effective voltage value of the liquid crystal capacitor 120 by negative polarity writing is slightly larger than the effective voltage value by positive polarity writing due to pushdown (TFT 116). Is n channel). For this reason, the voltage LCcom is set to an appropriate value that offsets the influence of pushdown by offsetting it to the lower side than the reference voltage Vc.
In addition, regarding the polarity of writing to the pixels arranged in a matrix, there are various modes such as for each scanning line, for each data line, for each pixel, and for each surface (frame). In the embodiment, for convenience of explanation, polarity inversion is performed for each frame. Therefore, in this embodiment, the logic level of the polarity designation signal Pol is constant in the same vertical scanning period (F) as shown in FIG.
Since a liquid crystal deteriorates when a direct current component is applied to the liquid crystal capacitor 120, the logic level of the polarity designation signal Pol is inverted every vertical scanning period (F) as shown in FIG.

The data signal conversion circuit 54 converts the digital image data Vd into an analog data signal Vda.
It is to convert to. More specifically, the data signal conversion circuit 54 converts the voltage into a data signal Vda having a voltage corresponding to the gradation value designated by the image data Vd and having the polarity designated by the polarity designation signal Pol, and adding the addition signal. 68 to one input.
A voltage ΔV described later is supplied to the other input terminal of the adder circuit 68. The adding circuit 68 corrects the data signal Vda from the data signal converting circuit 54 by adding only the voltage ΔV.
If the signal De is at the L level, the double throw switch 70 selects the signal supplied to one input terminal, that is, the data signal corrected by the adder circuit 68, in the position of the solid line in the figure. If the signal De is at the H level, it is in the position of the broken line in the figure, and the signal supplied to the other input terminal, that is, the monitor signal Ma by the monitor signal generation circuit 58 is selected and selected by either This signal is supplied to the image signal line 148 of the liquid crystal display panel 100 as a data signal Vid.

The buffer circuit 60 is a buffer circuit having a voltage amplification factor “1” for amplifying the voltage of the signal Mb appearing on the dummy data line 115. The low-pass filter (LPF) 62 is a kind of integration circuit, and smoothes the output waveform from the buffer circuit 60 and supplies it to the subtraction input terminal (−) of the subtraction circuit 64.
The monitor signal generation circuit 58 subtracts a monitor signal Ma having a voltage opposite to the writing polarity designated by the polarity designation signal Pol and corresponding to a predetermined gradation value, for example, a gradation value “128”. Are supplied to the addition input terminal (+) and the other input terminal of the switch 70, respectively.
The subtraction circuit 64 outputs a difference voltage Δ obtained by subtracting the voltage of the output signal of the LPF 62 supplied to the subtraction input terminal (−) from the voltage of the monitor signal Ma supplied to the addition input terminal (+). . The latch circuit (L) 66 is an analog latch circuit that holds and outputs the difference voltage output by the subtraction circuit 64 in a certain vertical blanking period over the next vertical scanning period.

Next, the operation of the electro-optical device 10 according to this embodiment will be described. The electro-optical device 10 corrects a data signal Vda having a voltage according to a gradation value designated by the image data Vd and having a polarity designated by the polarity designation signal Pol with a differential voltage ΔV. . Therefore, first, after pointing out a problem when correction is not performed with the difference voltage ΔV, a case where correction is performed with the difference voltage ΔV will be described.

First, as shown in FIG. 4, image data Vd specifying the gradation of the pixels in the first row is supplied in the order of 1 column to 1080 columns. When positive polarity writing is designated by the polarity designation signal Pol in the vertical scanning period in which the image data Vd is supplied, the image data Vd is converted into a positive data signal Vda by the data signal conversion circuit 54. .
The scanning control circuit 52 controls the scanning line driving circuit 130 so that the scanning signal G1 becomes H level over the horizontal scanning period (H) in which the image data Vd of the first row is supplied, and supplies the image data Vd. The sampling signal output circuit 142 is controlled so that the sampling signals S1, S2, S3, S4,.

A data signal Vda (Vi) obtained by converting the image data Vd corresponding to the pixel in the first column in the first row.
When d) is output to the image signal line 148, the sampling signal S1 becomes H level. As a result, the TFT 144 in the first column is turned on, and the data signal Vid is sampled on the data line 114 in the first column. Similarly, when the data signal Vda (Vid) corresponding to the pixels in the 2nd, 3rd, 4th,..., 1920th column in the first row is output to the image signal line 148, the sampling signal S2, When S3, S4,..., S1920 becomes H level, 2, 3, 4,.
The data signal Vid corresponding to the pixels in the first row, the second column, the first row, the third column, the first row, the fourth column,...
On the other hand, if the scanning signal G1 is at the H level, the TFT in the pixel 110 located in the first row
Since all of 116 are turned on, the voltage of the data signal Vid sampled on the data line 114 is applied to the pixel electrode 118. For this reason, the positive voltage corresponding to the gradation specified by the image data Vd is written in the liquid crystal capacitor 120 in the pixels of the first row and 1, 2, 3, 4,..., 1920 columns. Will be retained.

Next, image data Vd for specifying the gradation of the pixels in the second row is supplied in the order of 1 column to 1080 columns. When the image data Vd of the second row is supplied, the same operation as that of the first row is performed, so that the liquid crystal capacitance in the pixels of the second row and 1, 2, 3, 4,. In 120, a positive voltage corresponding to the gradation designated by the image data Vd is written and held.
Thereafter, the same operation is repeated until the image data Vd in the 1080th row is supplied. Thereby, the positive voltage corresponding to the gradation specified by the image data Vd is written and held in the liquid crystal capacitors 120 in all the pixels.
Note that the same voltage writing operation is performed in the next vertical scanning period. However, in this embodiment, since the polarity inversion is performed for each frame as described above, the writing polarity is inverted to be negative. For this reason, in the next vertical scanning period, the negative voltage corresponding to the gradation specified by the image data Vd is written and held in the liquid crystal capacitors 120 of all the pixels.

FIG. 6 is a diagram showing an example of the voltage waveform of the data signal Vid in the horizontal scanning period (H) in which the i-th scanning line 112 is selected. If the data signal Vid is positive writing, FIG. From the voltage Vb (+) by the amount specified by the image data Vd in the range from the voltage Vb (+) corresponding to black (lowest gradation) to the voltage Vw (+) corresponding to white (highest gradation). The voltage is low (indicated by ↓ in the figure), and in the case of negative polarity writing, it is specified by the image data Vd in the range from the voltage Vb (-) corresponding to black to the voltage Vw (-) corresponding to white. Therefore, the voltage becomes higher than the voltage Vb (−) (indicated by ↑ in the figure). Here, the positive voltage Vb (+) and the negative voltage Vb (−) are symmetrical with each other about the voltage Vc. The same applies to the voltages Vw (+) and Vw (-).
In addition, the vertical scale indicating the voltage in the data signal Vid in FIG. 6 is enlarged as compared with other voltage waveforms.

By the way, the characteristics of the TFT 144 change due to environmental temperature, aging, and the like. For example, switching characteristics deteriorate due to secular change, and on-resistance increases. For this reason, even if a data signal having a voltage corresponding to the gradation value is correctly supplied to the image signal line 148, if the characteristics of the TFT 144 are changed, the voltage sampled on the data line 114 is Thus, the voltage of the data signal Vid supplied to 148 is deviated. Here, the fact that the voltage corresponding to the gradation value is not correctly sampled on the data line 114 means that the target gradation cannot be obtained for the pixel. This means that the display quality is deteriorated. Directly connected to
Therefore, in the present embodiment, the voltage of the data signal is increased in advance by the amount that the voltage sampled on the data line 114 deviates due to the characteristic change of the TFT 144. With this configuration, an effect that a data signal having a voltage corresponding to the gradation value is correctly sampled on the data line 114 can be expected regardless of a change in characteristics of the TFT 144.

Therefore, an operation of correcting the data signal Vda converted by the data signal conversion circuit 54 with the differential voltage ΔV will be described.
As described above, in the vertical blanking period Fb, the scanning control circuit 52 sets the signal De to the H level. When the signal De becomes H level, the switch 70 selects the monitor signal Ma supplied to the other input terminal.
Here, assuming that the positive polarity writing is designated by the polarity designation signal Pol, the monitor signal generation circuit 58 has the negative polarity having the opposite polarity to the positive polarity and the gradation value in the vertical blanking period Fb. A monitor signal Ma having a voltage corresponding to “128” is output. Since the switch 70 selects the monitor signal Ma when the signal De becomes H level in the vertical blanking period Fb, the monitor signal Ma having the negative polarity voltage is applied to the image signal line 148 of the liquid crystal display panel 100. Is supplied.

When the signal De is at the H level, the TFT 145 is turned on, so that the monitor signal Ma is sampled on the dummy data line 115. Here, since the TFT 145 has the same characteristics as the TFT 144, it changes with the same characteristics with respect to environmental temperature and aging. Therefore, the voltage sampled on the dummy data line 115 by the TFT 145 can be considered as the voltage sampled on the data line by the TFT 144 whose characteristics have changed.
The voltage of the signal Mb sampled on the dummy data line 115 is supplied to the subtraction input terminal (−) of the subtraction circuit 64 through voltage buffering by the buffer circuit 60 and smoothing by the LPF 62.

In the subtracting circuit 64, the voltage of the signal Mb is subtracted from the voltage of the monitor signal Ma to obtain the difference voltage ΔV. This difference voltage ΔV is the difference between the monitor signal Ma supplied to the image signal line 148 and the voltage sampled on the dummy data line 115 by the TFT 145. This difference is the negative voltage data on the image signal line 148. It is considered that when the signal is supplied, the difference between the negative polarity voltage and the voltage of the data line 114 that will be sampled by the TFT 144 is approximately equal.
The difference voltage ΔV output from the subtraction circuit 64 is latched in the latch circuit 66, held and output over the vertical scanning period in which the next negative writing is designated, and the data converted by the data signal conversion circuit 54 It is added to the signal Vda.

  The difference voltage ΔV held / output by the latch circuit 66 is a simulation of the voltage drop sampled on the data line by the TFT 144 when a negative voltage is supplied to the image signal line 148 (FIG. 7). (See (c)). This drop is added to the data signal Vda converted to the negative polarity, and is output to the image signal line 148 as the data signal Vid. Therefore, when the corrected voltage of the data signal Vid is sampled on the data line 114 by the TFT 144, the voltage sampled on the data line 114 matches the negative voltage corresponding to the gradation value (FIG. 7). (See (d)).

Note that, in the vertical blanking period Fb, which is the final part of the vertical scanning period in which negative polarity writing is designated, the monitor signal generation circuit 58 has a positive polarity having a polarity opposite to the negative polarity and a gradation value of “128”. The monitor signal Ma having a voltage corresponding to "is output. For this reason, the differential voltage ΔV held by the latch circuit 66 simulates a drop in voltage sampled on the data line by the TFT 144 when a positive voltage is supplied to the image signal line 148 (FIG. 7 (a)). The difference voltage ΔV, which is the drop, is held and output over the vertical scanning period in which the next positive writing is designated, and is added to the positive data signal Vda converted by the data signal conversion circuit 54. When the corrected voltage of the data signal Vid is sampled on the data line 114 by the TFT 144, the voltage sampled on the data line 114 matches the positive voltage according to the gradation value (FIG. 7 ( b)).

  As described above, in this embodiment, even if the characteristics of the TFT 144 change due to the environmental temperature, aging, etc., it is possible to cause the data line 114 to correctly sample the voltage corresponding to the gradation value.

In the first embodiment described above, the monitor signal Ma is a positive or negative voltage corresponding to the gradation value “128”, but may be a voltage other than this gradation value. Further, a voltage corresponding to two or more gradation values may be used.
Here, as an example in the case of using voltages corresponding to two gradation values, as shown in FIG. 8, a vertical blanking period (signal De is H level) in a vertical scanning period in which positive writing is designated. Are divided into the first half and the second half. Of these, the negative polarity voltage having the reverse polarity corresponding to the gradation value “96” is set in the first half period, and the negative polarity corresponding to the gradation value “160” is set in the second half period. Similarly, in the first half and the second half of the vertical blanking period of the vertical scanning period in which the negative polarity writing is designated, the monitor signal Ma is set to the positive polarity voltage corresponding to the gradation value “96” in the first half period. ,
It can be considered that the positive polarity corresponding to the gradation value “160” is set in the latter half period.
As described above, when the monitor signal Ma is changed by voltages corresponding to two gradation values, the voltage of the signal Mb appearing on the dummy data line 115 also changes. However, since the voltage change is smoothed by the LPF 62, the signal The average value of Mb is supplied to the subtraction input terminal (−) of the addition circuit 64. Therefore, if the average value when the voltage of the monitor signal Ma is changed is supplied to the addition input terminal (+) of the addition circuit 64, a difference voltage with a small error can be obtained.
In order to obtain the average value when the voltage of the monitor signal Ma is changed, it may be smoothed by LPF as in the case of the signal Mb. The voltage corresponding to two gradation values is not limited, and a voltage corresponding to three or more gradation values may be used.

Second Embodiment
In the first embodiment described above, the influence due to the characteristic change of the TFT 144 that samples the data signal Vid on the data line 114 can be suppressed. However, the TFT 144 may also be pushed down similarly to the TFT 116, and the influence may not be ignored. is there. The cause of this push-down is the parasitic capacitance between the gate and drain electrodes in the TFT 144, and the charge accumulated in the parasitic capacitance of the data line 114 and the parasitic capacitance between the gate and drain electrodes when turned on is turned off. This is because it is redistributed to each capacity at the moment.
Since the parasitic capacitance between the gate and drain electrodes in the TFT 144 is not constant and has a property of changing depending on the drain voltage, the voltage drop due to the push-down of the TFT 144 also changes depending on the voltage of the data signal Vid. .
Here, the voltage of the data signal is determined by the gradation value and the writing polarity as described above. For this reason, the difference voltage may be stored for each voltage determined by the gradation value and the writing polarity, and the voltage of the data signal supplied to the image signal line 148 may be corrected with the stored difference voltage. Become. However, even in this configuration, it is necessary to suppress the influence due to the change in characteristics of the TFT 144 due to the environmental temperature and the secular change, so that the stored differential voltage needs to be updated one by one.

The second embodiment is intended to suppress the influence of the characteristic change due to the environmental temperature and the secular change while considering the push-down of the TFT 144. FIG. 9 illustrates the electro-optical device according to the second embodiment. FIG. 3 is a diagram illustrating a configuration of a control circuit 50. Other parts are the same as those in the first embodiment.
When the gradation value specified by the image data Vd is “0” to “255”, the voltage of the data signal Vda converted by the data signal conversion circuit 54 is positive or negative with respect to each gradation value. There are 512 ways.
A lookup table (LUT) 82 in FIG. 9 stores correction value data corresponding to each of the 512 patterns in advance. Specifically, as shown in FIG. 10, the LUT 82 supplies positive and negative correction value (difference voltage) data for each of the gradation values “0” to “255” specified by the image data Vd. The correction value data corresponding to the gradation value specified by the image data Vd and the writing polarity specified by the polarity specifying signal Pol is output in advance. For example, when the image data Vd is input, if the gradation value specified by the image data is “8” and the positive writing is specified, the LUT 82 outputs the correction value data P8.
The D / A conversion circuit (DAC) 84 converts the correction value data output from the LUT 82 into an analog difference voltage ΔV and supplies the analog difference voltage ΔV to the other input terminal of the adder circuit 68.

On the other hand, the A / D conversion circuit (ADC) 80 converts the difference voltage ΔV obtained by the subtraction circuit 64 into digital data.
In the second embodiment, the monitor signal generation circuit 58 uses the monitor signal Ma as a voltage.
Each of the gradation values “0” to “255” is positive and negative, and is output in turn while switching every vertical scanning period (F).
Here, when the monitor signal generation circuit 58 outputs a monitor signal Ma having a positive polarity voltage having a gradation value “8”, for example, the difference voltage ΔV obtained by the subtraction circuit 64 is a positive polarity having the gradation value “8”. The difference between the voltage and the voltage that will appear on the data line 114 (dummy data line 115) by the sampling of the TFT 144 (145) when the positive voltage having the gradation value “8” is supplied to the image signal line 148. Voltage.

Therefore, in this case, in the LUT 82, the correction value data P8 having the gradation value “8” and the positive polarity is updated to data obtained by A / D converting the difference voltage ΔV obtained by the subtraction circuit 64.
Since this update operation is executed in a predetermined order while switching the gradation value and polarity every vertical scanning period, the period required to update all 512 correction value data is 512 times the vertical scanning period. Is approximately 8.3 seconds (when the vertical scanning period is 16.7 milliseconds).
Therefore, in the second embodiment, unlike the first embodiment in which the difference voltage is detected in the immediately preceding vertical blanking period, the data signal Vda is corrected with the difference voltage detected 8.3 seconds before the maximum. However, changes in characteristics due to environmental temperature and aging cannot change significantly in this amount of time, so there is almost no effect.

As described above, according to the second embodiment, even if the characteristics of the TFT 144 change due to environmental temperature, aging, or the like, or even when the TFT 144 is pushed down, the data line 114 is in accordance with the gradation value. It is possible to correctly sample the voltage.
The LUT 82 is configured to store and update positive and negative correction value data for all the gradation values specified by the image data Vd. However, only correction value data for typical gradation values is stored. Is stored and updated, and the correction value data of gradation values that are not stored is obtained by interpolation from the correction data of neighboring gradation values, the storage capacity required for the LUT 82 is reduced, and The update period of the correction value data of the LUT 82 can be shortened.

<Third Embodiment>
In the first embodiment described above, a data signal Vid having a voltage corresponding to the gradation is supplied to one image signal line 148 and is sampled in this order on the first to 1920th data lines. Although it has a dot-sequential configuration, the data signal is expanded n times (n is an integer of 2 or more) on the time axis and is supplied to n image signal lines, so-called phase expansion (also called serial-parallel conversion). A configuration in which driving is also used may be employed (for example, see Japanese Patent Application Laid-Open No. 2000-112437).

The electro-optical device according to the third embodiment is used in combination with a three-phase development drive in which a data signal is expanded three times on the time axis, and FIG. 11 is a block diagram showing the configuration thereof.
As shown in this figure, the data signal Vid is developed into three phases to become data signals Vid1 to Vid3, which are supplied to the three image signal lines 148, and the sampling signals are S1 to S1.
It decreases to 1/3 with S640.
Here, the TFT 145 is provided for each of the three image signal lines 148, and three dummy data lines 115 are also provided.
The control circuit 50 of the third embodiment is not particularly shown, but supplies the same signal Ma to the three image signal lines 148, and the voltage of the signal Ma and the signals Mb1 to Mb3 appearing on the three dummy data lines. Are used to correct the data signal of each phase. Even if there is a difference in transfer characteristics between the three image signal lines 148, each phase is corrected with a difference voltage, and thus such a difference in transfer characteristics is cancelled.

  According to the third embodiment, even if the characteristics of the TFT 144 change due to environmental temperature, aging, etc., and even if there is a difference in transfer characteristics in the supply path of the three image signal lines 148, the data line 114 In addition, it is possible to correctly sample the voltage according to the gradation value.

In the first embodiment described above, the signal De is set to the H level in the vertical scanning period Fb, the monitor signal Ma is supplied to the image signal line 148, the TFT 145 is turned on, and the voltage of the signal Mb appearing on the dummy data line 115 is detected. However, the period during which the signal De is at the H level may be any time as long as it is other than the period during which the pixel data signal Vid contributing to display is supplied. For example, as shown in FIG. 12, the signal De may be set to H level in the horizontal blanking period Hb. When the signal De is set to the H level during the horizontal blanking period Hb, the latch circuit 66 is configured to hold the differential voltage output by the subtraction circuit 64 during a certain horizontal blanking period over the next horizontal scanning period. good.

When the pixel writing polarity is set to frame inversion, the writing polarity of the row except the last row is the same as the writing polarity of the next row. For this reason, the monitor signal generation circuit 58 monitors a voltage having the same polarity as the writing polarity designated by the polarity designation signal Pol and corresponding to a predetermined gradation value, except for the horizontal scanning period in which the last row is selected. The signal Ma may be output.
However, when the pixel writing polarity is frame inversion, the writing polarity is inverted from the horizontal scanning period in which the last (1080 rows) is selected to the horizontal scanning period in which the next row (one row) is selected. The monitor signal generation circuit 58 is a monitor signal having a voltage opposite to the writing polarity specified by the polarity specifying signal Pol and corresponding to a predetermined gradation value only in the horizontal scanning period in which the last row is selected. It is sufficient to output Ma.

Further, when the pixel writing polarity is inverted for each scanning line (line inversion), since 1080 is an even number, the writing polarity of the row except the last row and the writing polarity of the next row are inverted. For this reason, in the case of line inversion, the monitor signal generation circuit 58 has a predetermined gradation value that is opposite in polarity to the writing polarity specified by the polarity specifying signal Pol except for the horizontal scanning period in which the last row is selected. The monitor signal Ma having a voltage corresponding to the above may be output.
In the case of line inversion, since the writing polarity does not invert from the horizontal scanning period in which the last (1080 rows) is selected to the horizontal scanning period in which the next row (one row) is selected, the monitor signal generation circuit 58 Only in the horizontal scanning period in which the last row is selected, the monitor signal Ma having the same polarity as the writing polarity designated by the polarity designation signal Pol and corresponding to a predetermined gradation value may be output.
Note that if the number of scanning lines is an odd number and the line is inverted, the writing polarity of one row and the writing polarity of the next row are always inverted, so the monitor signal generation circuit 58 is designated by the polarity designation signal Pol. The monitor signal Ma having a voltage opposite to the written polarity and corresponding to a predetermined gradation value may be output.

As described above, with respect to what polarity is written to the pixels arranged in a matrix, the polarity of the monitor signal Ma when the difference voltage is obtained and the polarity of the data signal to be corrected using the difference voltage are determined. If there is a match, there is no particular limitation.
Further, if the configuration in which the signal De is set to the H level in the horizontal blanking period Hb is applied to the second embodiment, the LUT 82 can be updated in a shorter period.

By the way, since the TFT 145 and the dummy data line 115 are for simulating the wiring path from the TFT 144 to the data line 114 as described above, it is preferable that the operating state is made uniform as much as possible.
Therefore, the signal for turning on the TFT 145 may be a signal having a pulse width similar to that of the sampling signals S1 to S1920 (S640) instead of the signal De. For this purpose, for example, it is conceivable that the sampling signal output circuit 142 outputs the sampling signal S1921 (S641) in the horizontal blanking period and supplies it to the gate electrode of the TFT 145.

Next, an example of an electronic apparatus using the electro-optical device according to the above-described embodiment will be described. FIG. 13 is a plan view showing a configuration of a three-plate projector using the above-described electro-optical device 10 as a light valve.
In this projector 2100, the light to be incident on the light valve is supplied with three primary colors of R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. And led to the light valves 100R, 100G and 100B corresponding to the respective primary colors.
Since the optical path length of B is longer than the other optical path lengths of R and G, in order to correct the optical path length in the middle of the optical path of B, the incident lens 2122, the relay lens 2123, and the outgoing light The light is guided through a relay lens system 2121 including a lens 2124.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the liquid crystal display panel 100 of the electro-optical device 10 in the above-described embodiment, and R, G, and B supplied from an external host device (not shown). It is driven by display data corresponding to each color.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. Therefore, after the images of the respective colors are combined and enlarged and projected by the lens unit 2114, a color image is displayed on the screen 2120.

  The transmitted images of the light valves 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the transmitted image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The left-right reversed image is displayed in the direction opposite to the horizontal scanning direction by the light valve 100G.

  In addition to the electronic devices described with reference to FIG. 13, direct-view type devices such as mobile phones, personal computers, televisions, video camera monitors, car navigation devices, pagers, electronic notebooks, calculators, word processors , Workstations, videophones, POS terminals, digital still cameras, devices equipped with touch panels, and the like. Needless to say, the electro-optical device according to the present invention is applicable to these various electronic devices.

1 is a diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. It is a figure which shows the structure of the control circuit in the same electro-optical apparatus. It is a figure which shows operation | movement of the same electro-optical apparatus. It is a figure which shows operation | movement of the same electro-optical apparatus. FIG. 6 is a diagram illustrating an operation of the electro-optical device. It is a figure which shows operation | movement of the same electro-optical apparatus. FIG. 10 is a diagram illustrating an operation according to a modification of the electro-optical device. It is a figure which shows the structure of the control circuit of the electro-optical apparatus which concerns on 2nd Embodiment. It is a figure which shows the conversion content of LUT in the same control circuit. It is a figure which shows the structure of the electro-optical apparatus which concerns on 3rd Embodiment. FIG. 10 is a diagram illustrating an operation according to another example of the electro-optical device. 1 is a diagram illustrating a configuration of a projector to which an electro-optical device according to an embodiment is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 50 ... Control circuit, 54 ... Data signal conversion circuit, 58 ... Monitor signal generation circuit, 60 ... Buffer circuit, 62 ... LPF, 64 ... Subtraction circuit, 66 ... Latch circuit, 68 ... Addition circuit, 70 ... switch, 82 ... LUT, 100 ... liquid crystal display panel, 108 ... counter electrode, 110 ... pixel, 112 ... scan line, 114 ... data line, 115 ... dummy data line, 116 ... TFT, 118 ... pixel electrode, 120 ... liquid crystal Capacitance, 130 ... dummy capacitance, 144, 145 ... TFT, 2100 ... projector

Claims (9)

An image signal line to which a data signal having a voltage corresponding to the gradation is supplied;
A plurality of sampling switching elements provided on each of a plurality of columns of data lines, each sampling a data signal supplied to the image signal line onto the data line;
A plurality of pixels provided corresponding to the intersection of a plurality of rows of scanning lines and a plurality of columns of data lines, and having a gradation corresponding to the voltage of the data signal sampled on the data lines when the scanning lines are selected When,
A data signal supply circuit for an electro-optical device having:
Dummy data lines,
A switching element for monitoring for sampling the data signal supplied to the image signal line to the dummy data line;
A difference voltage between the voltage of the data signal supplied to the image signal line and the voltage sampled to the dummy data line is obtained, and the voltage of the data signal supplied to the image signal line is corrected based on the difference voltage. A correction circuit;
A data signal supply circuit for an electro-optical device. The data signal supply circuit of the electro-optical device according to claim 1, wherein the sampling by the monitoring switching element is performed in a vertical blanking period or a horizontal blanking period. The voltage of the data signal sampled on the dummy data line by the monitoring switching element is not less than two values,
The correction circuit includes:
A low-pass filter for smoothing a voltage sampled on the dummy data line, and obtaining a difference between an average voltage of the data signal supplied to the image signal line and an output voltage of the low-pass filter as the differential voltage The data signal supply circuit of the electro-optical device according to claim 1. The voltage of the data signal is determined by the gradation and polarity of the pixel,
The correction circuit includes:
A lookup table in which the difference voltage is stored in advance according to the gradation and polarity of the pixel;
Read the difference voltage according to the gradation and polarity of the pixel from the lookup table, correct the voltage of the data signal based on the read difference voltage,
The difference voltage having the predetermined gradation and the predetermined polarity stored in the look-up table is updated to the difference voltage obtained when the data signal having the predetermined gradation and the predetermined polarity is supplied to the image signal line. The data signal supply circuit of the electro-optical device according to claim 1. When the image signal line is a plurality of m lines,
There are m dummy data lines,
The monitoring switching element is m pieces,
Each of the m monitor switching elements samples the data signal supplied to the m image signal lines to the m dummy data lines,
The correction circuit includes:
Based on the difference voltage between the voltage of the data signal supplied to one image signal line and the voltage obtained by sampling the data signal supplied to the one image signal line out of the m lines, the one image The data signal supply circuit of the electro-optical device according to claim 1, wherein the voltage of the data signal to be supplied to the signal line is corrected. An image signal line to which a data signal having a voltage corresponding to the gradation is supplied;
A plurality of sampling switching elements provided on each of a plurality of columns of data lines, each sampling a data signal supplied to the image signal line onto the data line;
A plurality of pixels provided corresponding to the intersection of a plurality of rows of scanning lines and a plurality of columns of data lines, and having a gradation corresponding to the voltage of the data signal sampled on the data lines when the scanning lines are selected When,
A data signal supply method for an electro-optical device having:
Dummy data lines,
A switching element for monitoring for sampling the data signal supplied to the image signal line to the dummy data line;
Provided,
Find the voltage difference between the voltage of the data signal supplied to the image signal line and the voltage sampled on the dummy data line,
A data signal supply method for an electro-optical device, wherein a voltage of a data signal supplied to the image signal line is corrected based on the difference voltage. An image signal line to which a data signal having a voltage corresponding to the gradation is supplied;
A plurality of sampling switching elements provided on each of a plurality of columns of data lines, each sampling a data signal supplied to the image signal line onto the data line;
A plurality of pixels provided corresponding to the intersection of a plurality of rows of scanning lines and a plurality of columns of data lines, and having a gradation corresponding to the voltage of the data signal sampled on the data lines when the scanning lines are selected When,
Dummy data lines,
A switching element for monitoring for sampling the data signal supplied to the image signal line to the dummy data line;
A difference voltage between the voltage of the data signal supplied to the image signal line and the voltage sampled to the dummy data line is obtained, and the voltage of the data signal supplied to the image signal line is corrected based on the difference voltage. A correction circuit;
An electro-optical device comprising: The electro-optical device according to claim 7, further comprising a dummy capacitor having one end connected to the dummy data line and the other end connected to a power supply line having a predetermined potential.   An electronic apparatus comprising the electro-optical device according to claim 7.

Images