JP2007279198A - Electrooptical device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To smoothly generate a ramp signal with low power consumption. <P>SOLUTION: A smoothing circuit 12 which smoothes a voltage Vout and outputs a voltage Vrp is arranged behind a ramp signal generating circuit 10 which generates a voltage Vout rising or falling in steps according to a clock signal Clk. The smoothing circuit 12 is a sort of voltage amplifying circuit and its slew rate (response speed) is set an average variation rate of the voltage Vout. Consequently, even when the frequency of the clock signal Clk is low, the voltage Vrp which smoothly varies can be obtained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for generating a lamp waveform suitable for an electro-optical device.

An electro-optical device that performs display by an electro-optical change such as a liquid crystal displays a pixel by applying a voltage corresponding to a gradation to a pixel electrode through a data line during a period in which a selection voltage is applied to the scanning line. The effective voltage value applied to is controlled so that gradation display is performed.
However, in this configuration, it is necessary to generate a positive polarity voltage and a negative polarity voltage according to the gradation, so that the voltage generation circuit becomes complicated, and simplification of the configuration is hindered.
Therefore, for example, during the period when the selection voltage is applied to the scanning line, a ramp signal whose voltage gradually changes is applied to the common electrode facing the pixel electrode, and the data line is set to a predetermined period only according to the gradation. There has been proposed a technique for setting a high impedance state after maintaining the potential (see Patent Document 1).
As a technique for generating such a ramp signal, in addition to the above-mentioned document, a capacitor element (capacitor) is charged with a constant current source to change the holding voltage of the capacitor at a constant rate, and this is referred to as a ramp signal. (Refer to Patent Document 2).
JP-A-7-281642 JP-A-6-326565

By the way, in the electro-optical device, there is a strong demand for low power consumption and a need for more gradation display. Therefore, the ramp signal generation circuit is also strongly required to have low power consumption when generating the ramp signal, and the ramp signal is required to change smoothly. However, the above two technologies are not sufficient to satisfy both of them, and there are problems in terms of low power consumption and multi-gradation.
The present invention has been made in view of such circumstances, and an object of the present invention is to provide an electro-optical device and an electronic apparatus that can further reduce power consumption and display multiple gradations easily. .

In order to achieve the above object, according to the present invention, the scanning line is provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines, and is selected as the scanning line between the data line and the pixel electrode. A plurality of pixels including switching elements that are rendered conductive when a voltage is applied; a scanning line driving circuit that selects the plurality of scanning lines in a predetermined order and applies the selection voltage; and the plurality of data lines A plurality of data-side switches having one end connected to the data line and the other end commonly connected to the potential line, and a voltage that changes stepwise according to the clock signal. A ramp signal generating circuit that generates a ramp signal; a smoothing circuit that smoothes the ramp signal and applies the smoothed signal to either the common electrode or the potential line facing the pixel electrode; and the plurality of scanning lines , In the period when the selection voltage is applied to the scanning line, the data side switch is connected to the pixel level corresponding to the intersection of the scanning line to which the selection voltage is applied and the data line connected to one end of the data side switch. A data-side control circuit for turning on the data-side switch for a period corresponding to the key, and controlling the data-side switch to the off-state, and the other one of the common electrode and the potential line is the one scanning line. Further, the voltage is maintained at a predetermined potential over a period during which the selection voltage is applied. According to this configuration, the voltage that changes stepwise according to the clock signal is smoothed, so that it is possible to obtain a ramp signal that changes smoothly even if the frequency of the clock signal is low.
In the present invention, the smoothing circuit may be a voltage amplification circuit having a slew rate equal to or higher than an average rate of change of the ramp signal by the ramp signal generation circuit, or an integration circuit.
Further, the present invention can be conceptualized not only as an electro-optical device but also as an electronic apparatus including the electro-optical device.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of an electro-optical device according to an embodiment of the invention.
As shown in this figure, the electro-optical device 1 includes a display area 100, a data side control circuit 25.
0, a scanning line driving circuit 350, a control circuit 400, a ramp signal generation circuit 10, and a smoothing circuit 12. Among them, in the display area 100, 320 scanning lines 311 are provided so as to extend in the row (X) direction, while 240 data lines 211 are provided so as to extend in the column (Y) direction. . The pixel 120 includes 320 rows of scanning lines 311 and 240 columns of data lines 21.
Corresponding to the intersection with 1, each is arranged. Therefore, in this embodiment, the pixel 12
Although 0 is arranged in the form of a matrix of 320 vertical rows × 240 horizontal columns, the present invention is not intended to be limited to this arrangement.

Here, a detailed configuration of the pixel 120 will be described. FIG. 2 is a diagram illustrating a configuration of the pixel 120, i rows and (i + 1) rows adjacent thereto, j columns and (j + 1) adjacent thereto.
A configuration of a total of 4 pixels of 2 × 2 corresponding to the intersections with the columns is shown.
Note that i and (i + 1) are symbols for generally indicating a row in which the pixels 120 are arranged, and are integers of 1 to 320, and j and (j + 1) are columns in which the pixels 120 are arranged. It is a symbol in the general case, and is an integer from 1 to 240.

As shown in FIG. 2, each pixel 120 includes a liquid crystal capacitor (liquid crystal element) 130 and an n-channel thin film transistor (hereinafter simply referred to as “TFT”) 241 that functions as a switching element. . Since each pixel 120 has the same configuration, the pixel 120 in the i row and j column will be described as a representative example. In the pixel 120 in the i row and j column, the gate of the TFT 241 is connected to the scanning line 311 in the i row. On the other hand, the source is connected to the data line 211 in the jth column, and the drain is the pixel electrode 23 that is one end of the liquid crystal capacitor 130.
1 is connected.
The other end of the liquid crystal capacitor 130 is connected to the common electrode 110. This common electrode 1
In this embodiment, 10 is common to all the pixels 120 as shown in FIG. 1, and the output voltage Vrp from the smoothing circuit 12 is applied.

In the liquid crystal capacitor 130, the voltage difference between the pixel electrode 231 and the common electrode 110 is held, and the amount of light transmitted (or reflected) through the liquid crystal capacitor 130 changes according to the effective value of the hold voltage. .
Although it is considered that such a configuration does not need to be described in detail, a method in which the liquid crystal is sandwiched between the pixel electrode and the common electrode and the electric field direction applied to the liquid crystal is the substrate surface vertical direction, the pixel electrode, Examples include a method in which an insulating layer and a common electrode are stacked so that the direction of the electric field applied to the liquid crystal is the horizontal direction of the substrate surface.
In the present embodiment, for convenience of explanation, if the effective voltage value held in the liquid crystal capacitor 130 is close to zero, the light transmittance is maximized to display white, while the effective voltage value increases. The normally white mode in which the amount of light decreases and finally the black display with the minimum transmittance is achieved.

Returning to FIG. 1 again, the control circuit 400 controls the data side control circuit 250 by supplying the control signal CntX and also supplies the scanning signal driving circuit 35 by supplying the control signal CntY.
The vertical scanning of the display area 100 by 0 is controlled. Further, the control circuit 400 supplies the polarity signal “Pol”, the reset signal “Rse”, and the clock signal “Clk” to the ramp signal generation circuit 10.

When the reset signal Res is supplied at the beginning of one horizontal scanning period (1H), the ramp signal generation circuit 10 resets the output voltage Vout to the voltage Vc, and every time the clock signal Clk is supplied for one cycle, The output voltage Vout is increased or decreased by the voltage ΔV according to the polarity instruction signal Pol. Specifically, if the polarity instruction signal Pol is at L level, the ramp signal generation circuit 10 increases the output voltage Vout by the voltage ΔV every time the clock signal Clk is supplied, while the polarity instruction signal Pol is at H level. If there is, the output voltage Vout is lowered by the voltage ΔV every time the clock signal Clk is supplied.
As shown in FIG. 3, the voltage Vc corresponds to an intermediate value between the voltage Vdd corresponding to the H level and the voltage Vss corresponding to the L level. An example of the ramp signal generation circuit 10 will be described later.

The smoothing circuit 12 is a kind of voltage amplification circuit, and its slew rate (response speed) is set to be equal to or higher than the average rate of change of the output voltage Vout by the ramp signal generation circuit 10. Here, if the period T _C of the clock signal Clk is to be constant in the present embodiment, the output voltage Vout, since changes by a voltage [Delta] V with respect to the period T _C, the slew rate of the smoothing circuit 12 is [Delta] V It is set to be _{equal to} or higher than / TC.
Therefore, if the polarity instruction signal Pol is at the L level, as shown in FIG. 6, the output voltage Vrp by the smoothing circuit 12 is obtained by smoothing the waveform of the output voltage Vout that rises stepwise. .

In addition, regarding the writing polarity with respect to the liquid crystal capacitor 130, when the potential of the pixel electrode 231 is high with respect to the voltage of the common electrode 110, the polarity is positive, and when it is low, the polarity is negative. In this embodiment, since the output voltage Vrp is applied to the common electrode 110, the writing polarity to the liquid crystal capacitor 130 becomes positive when the output voltage Vrp (Vout) changes in the decreasing direction, and the output voltage Vrp increases. When it changes in the direction, it becomes negative polarity. For this reason, the polarity instruction signal Pol for designating the changing direction of the output voltage Vout can be said to be a signal for designating the polarity of writing to the liquid crystal capacitor 130.
As shown in FIG. 3, the polarity instruction signal Pol is 1 in one vertical scanning period (1F).
The polarity is inverted every horizontal scanning period (1H), and even if attention is paid to the same horizontal scanning period in adjacent one vertical scanning period (1F), the polarity is inverted. For this reason, in this embodiment, scanning line inversion (row inversion) is performed in which the writing polarity is inverted for each scanning line, but the present invention is not limited to this. The reason why the polarity is inverted in this way is to prevent deterioration due to application of a direct current component to the liquid crystal.
As described above, in this embodiment, the cycle (frequency) of the clock signal Clk is constant, and the reset signal Res is supplied every time at the beginning of one horizontal scanning period (1H).
In one horizontal scanning period (1H) in which the polarity instruction signal Pol is at the L level, rp rises smoothly at a constant rate of change starting from the voltage Vc from the start, while the polarity instruction signal Pol is at the H level. In the horizontal scanning period (1H), the voltage is smoothly lowered at a constant change rate starting from the voltage Vc.

The scanning line driving circuit 350 sequentially selects the scanning lines 311 in the first, second, third,..., 320th rows in each horizontal scanning period (1H) according to the control signal CntY. The scanning signal corresponding to 311 is set to the selection voltage Vdd corresponding to the H level over the horizontal scanning period (1H), and the scanning signals corresponding to the other scanning lines 311 are set to the non-selection voltage Vss corresponding to the L level. Is. Here, the scanning signals supplied to the scanning lines 311 in the first, second, third,..., 320th rows are denoted as Y1, Y2, Y3,..., Y320, respectively. In the description, Yi is used for explanation.

Next, the data-side control circuit 250 has storage areas (not shown) corresponding to a matrix arrangement of 320 rows × 240 columns, and each storage area stores the gradation data Da of the corresponding pixel 120. To do. The gradation data Da is data that designates the gradation value (brightness) of the pixel 120. The gradation data Da is supplied from a host device (not shown) and is stored in a corresponding storage area when the display content is changed. The gradation data Da thus set is rewritten.
Further, when one scanning line 311 is selected by the scanning line driving circuit 350, the data-side control circuit 250, in accordance with the control signal CntX, outputs one row of the gradation data Da of the pixel located on the scanning line. Are read out in advance, and the switch control signals X1, X2, X3,..., X240 are applied to the scanning line for 1, 2, 3, 3 over the period during which the selection voltage Vdd is applied according to one row of the gradation data Da. ,..., And 240 lines of data lines 211 are output simultaneously.
Here, when the switch control signals X1, X2, X3,..., X240 are generally described as Xj when they are generally described without specifying a column, the data-side control circuit 250 scans the switch control signal Xj by one horizontal scan. Designated by the gradation data Da of the pixel corresponding to the intersection of the scanning line 311 selected in the horizontal scanning period and the data line 211 of the j-th column from the start end of the period (1H) to the rear side of the time axis. The H level is set only during the period corresponding to the gradation value, and the L level is set during the remaining period.

A switch 260 is provided corresponding to each column. Here, switch 260 in each column
One terminal is connected to the data line 211, and the other terminal is commonly connected to a potential line 281 maintained at the voltage Vc. For example, the switches 260 corresponding to the data line 211 in the j-th column are turned on when the switch control signal Xj is at the H level.

Here, the data line 211 connected to one terminal of the switch 260 which is off is in a high impedance state. Therefore, for convenience, the voltage of the data line 211 in the 1, 2, 3,..., 240th column is expressed as S1, S2, S3,..., S240. I will write it.

Next, writing in the electro-optical device 1 having such a configuration will be described.
FIG. 4 is a diagram showing the writing of pixels in i rows and j columns and the writing of pixels in (i + 1) rows and j columns adjacent one row below this in relation to the scanning signals Yi and Y (i + 1). is there.
When the pixel in i row and j column is gray between white and black, the switch is switched in one horizontal scanning period (1H) in which the scanning signal Yi is H level when the polarity instruction signal Pol is L level. control signal Xj from the start of the 1 horizontal scanning period (1H), becomes only the H level period T ₁ corresponding to the gray. When the switch control signal Xj becomes H level, the switch 260 in the j-th column is turned on (conductive), so that the voltage Sj of the data line 211 in the j-th column is kept at the voltage Vc.
Further, when the scanning signal Yi becomes H level, the TFT 241 is turned on in the pixel 120 for one row located on the scanning line 311 of the i-th row. Therefore, pixel 120 in i row and j column
, The pixel electrode 231 becomes equal to the voltage Vc in the same way as the data line 211 in the j-th column.
On the other hand, during the one horizontal scanning period (1H), when the polarity instruction signal Pol is at the L level, the voltage of the common electrode 110, that is, the output voltage Vrp by the smoothing circuit 12, rises from the voltage Vc. For this reason, when the switch 260 in the j-th column is turned on, writing with the pixel electrode 231 at the high-order side is started in the liquid crystal capacitor 130 in the pixel in the i-th row and j-th column.

Next, when the period T _{1 has} elapsed since the start of the one horizontal scanning period, the data signal Xj is H
It changes from level to L level. For this reason, since the switch 260 is turned off (non-conducting), the data line 211 in the j-th column is in a high impedance state in which the voltage is uncertain.
Here, even if the switch 260 is turned off, the voltage Vrp applied to the common electrode 110 continues to rise during one horizontal scanning period in which the i-th scanning line 311 is at the H level, and the TFT
Since the ON state of 241 continues, the voltage Sj of the data line 211 in the j-th column in the high impedance state decreases at the same rate of change as the output voltage Vrp from the moment when the switch 260 is turned off. .
Therefore, the write voltage for the liquid crystal capacitor 130 in the i row and the j column is determined at the moment when the switch 260 in the j column is turned off during the period in which the scanning signal Yi is at the H level, and the polarity instruction signal Pol is at the L level. If so, the voltage V at the moment when the switch 260 in the j-th column is turned off.
The difference voltage between rp and the voltage Vc (the voltage indicated by ↓ in FIG. 4) is held even after the switch 260 is turned off with the pixel electrode 231 at the lower side.
When the one horizontal scanning period (1H) ends and the scanning signal Yi changes to the L level, the TFTs 241 of the pixels for one row located in the i-th scanning line 311 are turned off. 231 is electrically disconnected from the corresponding data line 211 and enters a floating state. For this reason, the potential of the pixel electrode 231 in the i row and the j column also changes with the voltage of the common electrode 110, but the voltage held in the liquid crystal capacitor 130, that is, the switch 2 in the j column.
The difference voltage between the voltage Vrp and the voltage Vc at the moment when 60 is off is maintained even if the switch 260 is turned off or the scanning signal Yi changes to the L level.
In addition, although the operation is described as a representative of the pixels in the i-th row among the pixels in the i-th row, in the period in which the scanning signal Yi is at the H level, 1 to 240 positioned in the i-th row. Writing for the j-th column is executed simultaneously in parallel for all the pixels in one column.

In the next one horizontal scanning period (1H), since the scanning signal Y (i + 1) is at the H level, writing is similarly performed on the pixels for one row located in the (i + 1) th row. However, in this embodiment, since the writing polarity is inverted for each scanning line, as a result of the polarity instruction signal Pol being inverted to the H level, the output voltage Vout drops from the voltage Vc in the one horizontal scanning period.
Therefore, the write voltage for the liquid crystal capacitor 130 in (i + 1) rows and j columns is equal to the scanning signal Y (
i + 1) is determined at the moment when the switch 260 in the j-th column is turned off during the period when the switch 260 in the j-th column is turned off. (The voltage indicated by ↑) with the pixel electrode 231 on the higher side, the switch 26
It is held even after 0 is turned off.

Here, the writing of the i and (i + 1) th rows adjacent to each other is described.
Such writing is executed for each horizontal scanning period in the order of the first, second, third,..., 320th row in one vertical scanning period (1F), and an image of one frame is displayed. . In the next one vertical scanning period (1F), the writing polarity is reversed in each row, and the same writing is executed.

In the present embodiment, when the smoothing circuit 12 is not present, the output voltage Vout cannot be smoothed unless the frequency of the clock signal Clk is sufficiently high for one horizontal scanning period (1H). If the output voltage Vout is not smooth, the voltage that can be held by the liquid crystal capacitor 130 is
Rather than the period T ₁ the switch 260 is turned on, it means that is determined depending on the number of steps of the output voltage Vout at 1 horizontal scanning period (1H), that representable gradation number is limited Become. In other words, assuming two different periods, it should be possible to darken the pixel by turning on the switch 260 for a longer time (in the case of the normally white mode), but the frequency of the clock frequency Clk is If it is low, the output voltage Vout does not change when compared in the two periods, and the same voltage is held in the liquid crystal capacitor 130, and there is a case where there is no difference in gradation.
On the other hand, if the frequency of the clock signal Clk is increased, the output voltage Vout can be made smooth, but there is also a problem that power consumption accompanying the increase in frequency cannot be ignored.
On the other hand, according to the present embodiment, even if the clock frequency is low and the number of steps of the output voltage Vout by the ramp signal generation circuit 10 is small, the smoothing circuit 12 smoothes the output voltage Vout smoothly. possible gradation number will depend on the accuracy of period T _1, not only it is easy to increase the number of representable gradations, further also possible to suppress the power consumption associated with the higher frequency It becomes possible.

Next, an example of the configuration of the ramp signal generation circuit 10 will be described. FIG. 5 is a circuit diagram showing a configuration of the ramp signal generation circuit 10.
As shown in this figure, the ramp signal generating circuit 10 includes a single throw switches _{S 0,} double throw switch _{S 1-u, S 1-} d, and _{S 2,} S _5-p and _{S 5-q,} capacitor 21, 22, 2
3, a reference voltage source 30, and a buffer circuit 40.
Of these, single-throw switches S _0, the control circuit 400 is intended the reset signal Res is supplied (see FIG. 1) is closed when the H level, also, double throw switch S _1-u, S _{1 −}
Each of the _d and S _2, when the clock signal Clk is at the H level, while closed between the common terminal and the terminal a, when the clock signal Cl k is L level, the common terminal and the terminal b It closes in between. In the present embodiment, the double throw switches S _1-u , S _1-d and S ₂ correspond to the first, second and third double throw switches.
Each of the double throw switches S _5-p and S _5-q is closed between the common terminal and the terminal a when the polarity indicating signal Pol is at the H level, while when the polarity indicating signal Pol is at the L level. And closed between the common terminal and the terminal b.

Between each common end of the double throw switches S1 _-u and S1 _-d , a capacitor 21 (first capacitance element)
Is inserted. Here, of the terminals of the capacitor 21, the double throw switch S1 _-u side is _defined as one terminal m.
The terminal a of the double throw switch S1 _-u is connected to the positive terminal of the reference voltage source 30 for generating the reference voltage Vref, and the terminal b of the double throw switch S1 _{-u is} the terminal of the double throw switch S5 _-p . a and the double-throw switch S _5-q are connected to the terminal b. In addition, double throw switch S _1-
The terminal b of _{d is connected to} the terminal b of the double throw switch S5 _{-p and} the terminal a of the double throw switch S5 _-q , respectively.
The common terminal of the double-throw switch S ₂ is connected to one terminal n of the capacitor 22 (second capacitor element), the terminal a of the double throw switch S ₂ is one terminal of the single-throw switches S _0, the capacitor 23
One terminal of the (third capacitive element), and are connected to the input terminal of the buffer circuit 40, the terminal b of the double-throw switch S ₂ is connected to the common terminal of the double throw switch S _5-q.

The buffer circuit 40 is a voltage amplification circuit with an amplification factor of “1”, and the output voltage thereof is the output voltage Vout of the ramp signal generation circuit 10. In addition, this output terminal is a double throw switch S _5.
-It is connected to the common end of _p .
The terminal a of the double throw switch S _{1 -d} , the other terminal of the capacitor 22, the other terminal of the single throw switch S ₀ , and the other terminal of the capacitor 23 are commonly connected to the negative terminal of the reference voltage source 30. In addition, the common connection portion is kept at the same voltage Vc as that of the potential line 281.

As shown in FIG. 6, the reset signal Res becomes H level simultaneously with the clock signal Clk at the start of one horizontal scanning period (1H), but its pulse width is shorter than that of the clock signal Clk. The cycle of the clock signal Clk is constant over a period during which the output voltage Vout is increased or decreased, that is, one horizontal scanning period (1H).
Note that the single throw switch S ₀ and the double throw switches S _1-u , S _1-d, and S ₂ are described here as mechanical switches, but actually, a single transistor or a combination of transistors is used. It consists of an electronic switch consisting of a transmission gate.

Next, the operation of the ramp signal generation circuit 10 will be described.
Here, the operation when the polarity instruction signal Pol is at the L level and the output voltage Vout is raised from the voltage Vc will be described first. FIG. 7 is a diagram schematically showing the configuration of the ramp signal generation circuit 10 divided into each period, and FIG. 8 shows the relationship between the switch state, the voltage at the terminal n, and the output voltage Vout in each period. FIG.
When the polarity instruction signal Pol is at the L level, the double throw switches S _5-p and S _5-q are closed between the common terminal and the terminal b, so that the output terminal of the buffer circuit 40 is connected to the double throw switch S. _1-
is connected to the terminal _d b of the terminal b of the double-throw switch S ₂ would be connected to the terminal b of the double throw switch S _1-u.
In the period (1) in which the reset signal Res and the clock signal Clk are simultaneously at the H level at the start of operation, the single throw switch S ₀ is closed and the double throw switches S _1-u and S _1−
d and S ₂ is closed between the common terminal and the terminal a.
For this reason, the ramp signal generation circuit 10 is configured so that the capacitor 21 is charged to the reference voltage Vref while the both ends of the capacitors 22 and 23 are short-circuited as shown in FIG. The hold state is cleared.
Since the input terminal of the buffer circuit 40 becomes the voltage Vc, the output voltage Vout also becomes the voltage Vc.

Subsequently, the reset signal Res is the L level, in the period of the clock signal Clk is maintained at H level (2), since the single-throw switch S ₀ is opened, simplified manner the circuit shown in FIG. 7 (2) It becomes. Input terminal of the buffer circuit 40, with the opening of the single-throw switches S _0, becomes disconnected from the common part, immediately after the period of (1), since the hold voltage of the capacitor 22 is zero The output voltage Vout is still the voltage Vc.

Next, in the period (3) when the clock signal Clk is at the L level, the double throw switches S _1-u , S
_1-d and S ₂ is closed between the common terminal and the terminal b. For this reason, the ramp signal generation circuit 10 is simply a circuit as shown in FIG. At this time, since the holding voltage of the capacitor 23 is zero, the output voltage Vout is still the voltage Vc.
On the other hand, the terminal m of the capacitor 21 charged with the voltage Vref is connected to the terminal n of the capacitor 22. The other terminal of the capacitor 21 is connected to the output terminal of the buffer circuit 40 of the voltage Vc, and the other end of the capacitor 22 is connected. Is in a state of being connected to the common portion having the voltage Vc, a part of the electric charge accumulated in the capacitor 21 moves to the capacitor 22.
Here, when the capacitance values of the capacitors 21 and 22 are C ₁ and C ₂ , respectively, the holding voltage of the capacitor 22, that is, the voltage at the terminal n is Vref · C ₁ / (C ₁ + C ₂ ) + Vc. .

Subsequently, in the period (4) when the clock signal Clk is at the H level, the double throw switch S1 _-u.
Since S _1-d and S ₂ is closed between the common terminal and the terminal a, the same circuit configuration as the period (2).
However, the holding voltage of the capacitor 22 immediately before is Vref · C ₁ /
Since (C ₁ + C ₂ ) + Vc, the voltage at the input terminal of the buffer circuit 40 becomes Vref · C ₁ / (C ₁ + C ₂ + C ₃ ) + Vc, which is redistributed by the capacitance value C ₃ of the capacitor 23. This voltage is output as Vout. For convenience, this Vref · C ₁ / (C ₁ + C ₂ +
Let C ₃ ) be ΔV.
On the other hand, the capacitor 21 charges the reference voltage Vref again with the terminal m as the high-order side.

In the period (5) when the clock signal Clk is at the L level, the double throw switches S _1-u , S _1-d
And since S ₂ is closed between the common terminal and the terminal b, the same circuit configuration as the period (3).
However, the output voltage Vout obtained by amplifying the holding voltage of the capacitor 23 with the amplification factor “1” by the buffer circuit 40 is ΔV + Vc, and this voltage is applied to the other terminal of the capacitor 21 charged with the voltage Vref, and The terminal m and the terminal n are connected, and the capacitor 22
Since the other terminal is connected to the common portion having the voltage Vc, a part of the electric charge accumulated in the capacitor 21 moves to the capacitor 22. At this time, the voltage at the terminal n is Vref.
- the _{C 1 / (C 1 + C} 2) + ΔV + Vc.
When the clock signal Clk becomes H level in the period (6), the double throw switches S _1-u , S
Since _1-d and _{S 2} is closed between the common terminal and the terminal a, the voltage at the input terminal of the buffer circuit 40, ΔV + ΔV + Vc, i.e. 2.DELTA.V + Vc becomes, this is the output voltage Vout
It becomes.

Thereafter, the capacitor 21 is set to the reference voltage Vre during the period when the clock signal Clk is at the H level.
In the period when the clock signal Clk is at the L level, the charge voltage Vref of the capacitor 21 is increased by the output voltage Vout and distributed to the capacitor 22 during the period when the clock signal Clk is at the L level.
During the period in which lk becomes H level again, the operation of redistributing the charging voltage of the capacitor 22 to the capacitor 23 and outputting it through the buffer circuit 40, while charging the capacitor 21 to the reference voltage Vref is repeated.
Thereby, in the ramp signal generation circuit 10, if the polarity instruction signal Pol is at the L level, the output voltage Vout increases by ΔV for each cycle of the clock signal Clk as shown in FIG. .

On the other hand, when the polarity instruction signal Pol is at the H level, the double throw switches S _5-p and S _5-q
Because There is closed between the common terminal and the terminal a, an output terminal of the buffer circuit 40 is connected to the terminal b of the double throw switch S _1-u, the terminal b of the double-throw switch S ₂ is double-throw switch It is connected to the terminal b of S1 _-d .
Therefore, as shown in FIG. 9, in the period (1), the charging voltages of the capacitors 22 and 23 are reset to zero, and the output voltage Vout is reset to the voltage Vc.
In 2), the capacitor 21 is charged to the reference voltage Vref. In the period (3), the charging voltage Vref of the capacitor 21 is distributed to the capacitor 22 in a state where the output voltage Vout is based on the high-order side. In the period (4), The operation of redistributing the charging voltage of the capacitor 22 to the capacitor 23 and outputting it via the buffer circuit 40 while charging the capacitor 21 to the reference voltage Vref is repeated. Therefore, in the configuration shown in FIG. The output voltage Vout decreases by ΔV every cycle of Clk.

According to the ramp signal generation circuit 10 shown in FIG. 5, the reference voltage Vref charged in the capacitor 21 is distributed to the capacitor 22 using the output voltage Vout as the reference potential, and further redistributed to the capacitor 23, which is buffered. Since 40 is configured to output, it is possible to keep power consumption extremely low compared to a configuration in which D / A conversion is performed using resistance division or a constant current source.
Further, according to the configuration shown in FIG. 5, the output voltage Vout becomes Δ in one cycle of the clock signal Clk.
If the frequency of the clock signal Clk is constant, the output voltage V
The rate of change of out is also constant. In other words, this means that the rate of change of the output voltage Vout can be arbitrarily set by controlling the frequency of the clock signal Clk.

In the configuration shown in FIG. 5, the output terminal of the buffer circuit 40 / the terminal a of the double throw switch S2 is connected as the connection destination to the terminal b of the double throw switch S1 _-u / the terminal b of the double throw switch S1 _-d .
The output voltage Vout is raised or lowered stepwise by switching with the double throw switches S5 _-p and S5 _{-q in} accordance with the polarity instruction signal Pol. In either connection state, the reference voltage source 30 is connected. Even with a configuration that only reverses the polarity, the output voltage Vout
Can be raised or lowered stepwise.

In the electro-optical device 1 described above, the smoothing circuit 12 is a voltage amplification circuit, and the slew rate is set to be equal to or higher than the average rate of change of the output voltage Vout, whereby the output voltage Vo.
Although the output voltage Vrp obtained by smoothing ut is obtained, as shown in FIG. 10, the same smoothing is possible even with an integrating circuit composed of a resistor R and a capacitor C, for example, and an integrating circuit using a voltage amplifier circuit But the same is true.

In the electro-optical device 1 shown in FIG. 1, the output voltage Vrp is increased from the voltage Vc and then reset to the voltage Vc. However, after the voltage Vc is increased to a predetermined voltage, A configuration in which the voltage is lowered from the predetermined voltage to the voltage Vc may be employed. In this configuration, when the voltage is lowered from the predetermined voltage to the voltage Vc, it is necessary to keep the potential line 281 at the predetermined voltage. As described above, in the configuration in which the voltage Vc is not the starting point, the change range of the output voltage Vrp can be halved, so that the voltage amplitude required for the logic signal of the scanning signal and the switch control signal can be suppressed. For this reason, since the withstand voltage of the scanning line driving circuit 350 and the data side control circuit 250 is small, the configuration can be simplified correspondingly.
Furthermore, the common connection portion may be reset not only by the voltage Vc but also by switching to a predetermined voltage different from the voltage Vc.

Further, in the electro-optical device 1 shown in FIG. 1, the output voltage Vout, which is a ramp signal, is supplied to the common electrode 110 and the potential line 281 is kept constant at the voltage Vc. The output voltage Vout may be supplied to the potential line 281.
Furthermore, although the liquid crystal capacitor 130 is in the normally white mode, it may be in a normally black mode that is dark when no voltage is applied.

<Electronic equipment>
Next, an electronic apparatus having the electro-optical device 1 according to the above-described embodiment as a display device will be described. FIG. 11 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 1 according to the embodiment.
As shown in this figure, the mobile phone 1200 includes a plurality of operation buttons 1202, the earpiece 1204 and the mouthpiece 1206, and the display area 100 of the electro-optical device 1 described above. Note that components of the electro-optical device 1 other than the display area 100 do not appear as appearance.

As an electronic apparatus to which the electro-optical device 1 is applied, in addition to the mobile phone shown in FIG. 11, a digital still camera, a notebook personal computer, a liquid crystal television, a viewfinder type (or a monitor direct view type) video recorder. , Car navigation device, pager, electronic notebook,
Examples include calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the above-described electro-optical device 1 is applicable as a display device of these various electronic devices.

1 is a diagram illustrating a configuration of an electro-optical device according to an embodiment of the invention. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. FIG. 6 is a diagram for explaining an operation in the electro-optical device. FIG. 6 is a diagram for explaining an operation in the electro-optical device. It is a figure which shows an example of the ramp signal generation circuit in the same electro-optical device. It is a figure which shows the reset signal etc. in the same ramp signal generation circuit. It is a figure for demonstrating operation | movement of the ramp signal generation circuit. It is a figure for demonstrating operation | movement of the ramp signal generation circuit. It is a figure for demonstrating operation | movement of the ramp signal generation circuit. It is a figure which shows another example of the smoothing circuit in the same electro-optical apparatus. It is a figure which shows the structure of the mobile telephone to which the electro-optical apparatus which concerns on embodiment is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Electro-optical apparatus, 10 ... Lamp signal generation circuit, 12 ... Smoothing circuit, 21, 22, 23 ...
Capacitor 30 ... Reference voltage source 40 ... Buffer circuit 60 ... Capacitor 70 ... Capacitance changing circuit 110 ... Common electrode 120 ... Pixel 211 ... Data line 231 ... Pixel electrode 2
41 ... TFT, 250 ... Data side control circuit, 311 ... Scanning line, 350 ... Scanning line drive circuit,
400 ... Control circuit

Claims (5)

A switching element that is provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines, and is rendered conductive when a selection voltage is applied to the scanning lines between the data lines and the pixel electrodes. A plurality of pixels including
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order and applying the selection voltage;
A plurality of data-side switches provided corresponding to each of the plurality of data lines, one end of which is connected to the data line and the other end of which is commonly connected to a potential line;
A ramp signal generation circuit for generating a ramp signal of a voltage that changes stepwise according to a clock signal;
A smoothing circuit that smoothes the ramp signal and applies it to either the common electrode or the potential line facing the pixel electrode;
Among the plurality of scanning lines, in a period in which a selection voltage is applied to one scanning line, the data side switch is connected to the scanning line to which the selection voltage is applied and a data line connected to one end of the data side switch. It is turned on only for a period corresponding to the gradation of the pixel corresponding to the intersection with
A data side control circuit for controlling the data side switch to an OFF state;
With
The electro-optical device, wherein either the common electrode or the potential line is maintained at a predetermined potential over a period in which the selection voltage is applied to the one scanning line. The electro-optical device according to claim 1, wherein the smoothing circuit is a voltage amplification circuit having a slew rate equal to or higher than an average rate of change of the ramp signal by the ramp signal generation circuit. The electro-optical device according to claim 1, wherein the smoothing circuit is an integration circuit. The ramp signal generation circuit includes:
A single throw switch, first, second and third double throw switches, first, second and third capacitive elements, a reference voltage source, a buffer circuit,
Comprising
The first capacitive element is inserted at a common end of the first and second double throw switches,
One pole of the reference voltage source is connected to the terminal a of the first double throw switch,
One terminal of the second capacitive element is connected to the common end of the third double throw switch,
The terminal a of the third double throw switch is connected to one terminal of the single throw switch, one terminal of the third capacitive element, and the input end of the buffer circuit,
A terminal b of the third double-throw switch is connected to one terminal b of the first or second double-throw switch;
The other pole of the reference voltage source, the terminal a of the second double throw switch, the other terminal of the second capacitive element, the other terminal of the single throw switch, and the other terminal of the third capacitive element Being connected in common and kept at the predetermined potential,
The output terminal of the buffer circuit is the other terminal b of the first or second double throw switch.
Connected to
The voltage of the buffer circuit is output,
As the first stroke, the single throw switch is closed,
As the second stroke, the single throw switch is opened, the terminals a and the common end of the first, second and third double throw switches are closed,
As the third stroke, the terminals b and the common ends of the first, second and third double throw switches are closed,
Thereafter, the second and third steps are repeated. The electro-optical device according to claim 1, wherein:   An electronic apparatus comprising the electro-optical device according to claim 1.

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