JP2003060212A - Schottky barrier diode and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of a GaN Schottky barrier diode being difficult to manufacture at a low cost. SOLUTION: A buffer layer 2, having a laminated structure composed of first AlN layers 8 and second GaN layers 9 which are alternately laminated in some layers, is formed on a silicon substrate 1. A gallium nitride semiconductor region 3 for a Schottky barrier diode is formed on the buffer layer 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon oxide barrier diode using a nitride compound semiconductor and a method for manufacturing the same.

[0002]

2. Description of the Related Art A Schottky barrier diode using a gallium nitride-based compound semiconductor, that is, a compound semiconductor based on nitrogen and gallium is known. Conventional typical gallium nitride shea yacht key barrier diode, and a n + -type GaN semiconductor region and the n ^one type semiconductor region via an AlN or buffer layer made of GaN was formed at a low temperature on an insulating substrate made of sapphire sequentially it has a semiconductor body formed by laminating, electrically connected to each anode electrode to n ^one type semiconductor region (Schottky barrier electrode) electrically connected to the cathode electrode to the n + -type semiconductor region (ohmic contact electrode). Since the sapphire substrate is an insulator, the cathode electrode cannot be formed on the lower surface of the semiconductor substrate. Therefore, a portion of the n + type semiconductor region n ^one type semiconductor region formed on the upper surface of that removed by etching, the surface of the semiconductor substrate n +
A part of the upper surface of the shaped semiconductor region is exposed, and the cathode electrode is electrically connected thereto. Therefore, both the anode electrode and the cathode electrode are arranged on the upper surface of the semiconductor.

[0003]

The sailboat barrier diode described above has the following problems. (1) In the sheet yacht key barrier diode of the sapphire substrate, there a part of the n ^one type semiconductor region formed on the upper surface of the n + type semiconductor region to form an ohmic electrode should be removed by etching. However, since the nitride-based compound semiconductor is chemically stable, reactive ion etching using chlorine-based gas is used for the above etching. In this case, a defect or the like is generated on the surface of the semiconductor region due to etching damage, and some ions of the etching material enter the inside of the crystal of the surface which is not etched to deteriorate the crystal. As a result, a leak current is generated due to surface states and crystal defects, which results in deterioration of diode characteristics such as breakdown voltage. (2) The thermal conductivity of sapphire is O. Since it is as small as 126 W / cm · K, the heat generated during the operation of the device is not sufficiently dissipated and the device characteristics deteriorate, and the device is destroyed in the high current region. (3) A robust sapphire substrate must be made into chips by dicing or the like, which increases the manufacturing cost of the sailboat barrier diode.

Therefore, an object of the present invention is to provide a sailboat barrier diode capable of improving productivity and performance and reducing cost, and a method of manufacturing the same.

[0005]

DISCLOSURE OF THE INVENTION The present invention for solving the above problems and for achieving the above objects is a silicon dioxide barrier diode using a nitride-based compound semiconductor, which comprises silicon or a silicon compound containing impurities. A substrate having a low resistivity, a buffer layer disposed on one main surface of the substrate, a nitride-based compound semiconductor region disposed on the buffer layer, and a surface of the semiconductor region to a first electrode which is Shiyottokibaria contact, on the other main surface of the substrate and a second electrode which is in ohmic contact, wherein the buffer layer has the chemical formula _{Al x M y Ga 1-xy} N , where , M is In (indium) and B (boron)
At least one element selected from the following, x and y are 0 <x ≦ 1, 0 ≦ y <1, x + y ≦ 1, and a first layer made of a material represented by the following chemical formula: Al _a M _b Ga _{1 -ab} N Here, M is at least one element selected from In (indium) and B (boron), and a and b are 0 ≦ a ≦ 1 and 0 ≦ b <1, a numerical value satisfying a + b ≦ 1 and a composite layer with a second layer made of a material represented by the following.

As described in claim 2, the first layer is made of Al _x G _a1-x N, and the second layer is made of AlaG _a1-a N.
Can be Further, as described in claim 3, the first layer is Al _x In _y Ga _1-xy N, and the second layer is Al _a In _b Ga _1-ab N. Two
In (indium) can be contained in at least one of the layers. Further, as shown in claim 4, said first layer, and _{Al x B y G a1-xy} N, the second layer, Al
_a B _b G _a1-ab N, B (boron) can be contained in at least one of the first and second layers. Further, as described in claim 5, it is preferable that the buffer layer includes a plurality of the first and second layers, and the first layer and the second layer are alternately laminated. . Further, as described in claim 6, it is preferable that the first layer in the buffer layer has a thickness of 0.5 nm to 10 nm and the second layer has a thickness of 0.5 nm to 300 nm. Further, as described in claim 7, the thickness of the first layer in the buffer layer is 0.5 nm to 10 nm and the second layer has a thickness of 0.5 nm to 10 nm.
The layer thickness is preferably 10 nm to 300 nm. Further, as described in claim 8, it is desirable that the second layer contains silicon as an n-type impurity. As described in claim 9, the main surface of the substrate on the side where the buffer layer is disposed is (−111) just plane or −4 degrees to +4 from the (111) plane in the crystal plane orientation indicated by Miller index. It is desirable that the surface is inclined in the range of degrees. Further, as set forth in claim 10, the semiconductor region includes GaN (gallium nitride), AlInN (indium aluminum nitride), GaAlN (gallium aluminum nitride), InGaN (indium gallium nitride), and InGaAlN (indium gallium aluminum nitride). A gallium nitride-based or indium nitride-based compound semiconductor selected from the above is desirable. Further, as set forth in claim 11, in a method for manufacturing a chain barrier diode using a nitride-based compound semiconductor, a step of preparing a substrate made of silicon or silicon compound containing impurities and having a low resistivity If, on one main surface of the substrate, by a vapor deposition method, wherein the chemical formula _{Al x M y Ga 1-xy} N, wherein M is an in (indium) B (boron)
At least one element selected from, x and y are 0 <x ≦ 1, 0 ≦ y <1, x + y ≦ 1, and a first layer made of a material represented by the following chemical formula: Al _a M _b Ga _{1 -ab} N, where M is at least one element selected from In (indium) and B (boron), and a and b are 0 <a ≦ 1 and 0 ≦ b <1 and a value satisfying a + b ≦ 1 are sequentially formed to obtain a buffer layer, and a nitride-based compound semiconductor region is formed on the buffer layer. A step of forming by vapor phase growth, a step of forming a first electrode in contact with the silicon barrier on the surface of the semiconductor region, and a step of forming a second electrode in ohmic contact with the other main surface of the substrate. It is desirable to have and.

[0007]

According to the invention of each claim, the following effects can be obtained. (1) Since the substrate has conductivity, an ohmic electrode can be formed on the other main surface of the substrate. Therefore, the n formed on the upper surface of the n + type semiconductor region is formed to form an ohmic electrode like a conventional Schottky barrier diode.
There is no need to remove by etching a part of ^one type semiconductor region. For this reason, it is possible to prevent defects from being generated on the surface due to etching damage, and to prevent some ions of the etching material from penetrating into the inside of the crystal of the unetched surface to deteriorate the crystal. .
As a result, good diode characteristics can be obtained. (2) Silicon has a thermal conductivity of 1.4 W / cm · K, which is about 10 times that of sapphire, so the heat generated during device operation must be sufficiently dissipated through the substrate. You can As a result, good diode characteristics are obtained, and the element is not destroyed even in the large current region. (3) Since a robust sapphire substrate is not used and a substrate made of silicon or a silicon compound, which is easy to process and inexpensive, is used, it is possible to improve the productivity of the shutter barrier diode and reduce the manufacturing cost. (4) The buffer layer composed of the composite layer of the first layer and the second layer contributes to improvement of crystallinity and flatness of the nitride-based compound semiconductor region formed thereon. That is, the buffer layer composed of the composite layer of the first layer and the second layer can favorably take over the crystal orientation of the substrate composed of silicon or a silicon compound, and one main surface of the buffer layer has a nitride-based structure. The compound semiconductor region can be favorably formed with the crystal orientations aligned. If a buffer layer made of only a GaN semiconductor layer is formed on one main surface of a substrate made of silicon or a silicon compound, the difference in lattice constant between silicon and GaN is large. A nitride-based compound semiconductor region having excellent flatness cannot be formed. On the other hand, according to the present invention, the substrate and between the nitride compound semiconductor region, the lattice constant difference between the substrate made of silicon or silicon compound is relatively small Al _x M _y Ga
_{Since the} buffer layer composed of the composite layer of the first layer composed of _1-xy N and the second layer composed of Al _a M _b Ga _{1 -a -b} N is interposed, the nitride-based compound semiconductor region Flatness is improved. As a result, the diode characteristics are improved. (5) Since the first and second electrodes are arranged so as to face each other, it is possible to reduce the resistance value of the current path and reduce the power consumption and operating voltage. (6) The buffer layer is a composite layer of a first layer containing at least Al and N and a second layer containing at least Ga and N. The coefficient of thermal expansion of this buffer layer has an intermediate value between the coefficient of thermal expansion of a substrate made of silicon or its compound and the coefficient of thermal expansion of a semiconductor region made of a nitride compound. Therefore, the buffer layer relatively well suppresses the occurrence of strain due to the difference in thermal expansion coefficient between the substrate and the semiconductor region. According to the invention of claim 3, indium is contained in at least one of the first layer and the second layer forming the buffer layer. When at least one of the first and second layers is a nitride-based compound semiconductor containing indium (indium nitride-based compound semiconductor), the stress relaxation effect between the substrate and the nitride-based semiconductor region can be more excellently obtained. . That is, an indium nitride-based compound semiconductor that forms at least one of the first and second layers, such as InN, InGaN, and AlIn
N, AlInGaN, and the like have a thermal expansion coefficient closer to that of a substrate made of silicon or a silicon compound, as compared with other nitride-based compound semiconductors that do not contain In as a constituent element, such as GaN and AlN. Therefore, by including indium in at least one of the first layer and the second layer that form the buffer layer, the strain of the semiconductor region caused by the difference in the coefficient of thermal expansion between the substrate and the semiconductor region is reduced. Can be effectively prevented. According to the invention of claim 4, B (boron) is contained in at least one of the first layer and the second layer that form the buffer layer. A buffer layer containing B (boron) has a thermal expansion coefficient closer to that of a substrate made of silicon or a silicon compound than a buffer layer containing no B (boron). Therefore, according to the buffer layer of the fourth aspect of the present invention, it is possible to favorably prevent distortion of the semiconductor region due to the difference in thermal expansion coefficient between the substrate made of silicon or a silicon compound and the semiconductor region. In the invention of claim 5, since the plurality of first layers and the plurality of second layers are alternately laminated to form the buffer layer, a plurality of thin first layers are formed.
One layer is distributed. As a result, a good buffer function can be obtained as the entire buffer layer, and the crystallinity of the semiconductor region formed on the buffer layer is improved. According to the invention of claim 6, since the first layer of the buffer layer is set to a thickness that produces a quantum mechanical tunnel effect,
It is possible to suppress an increase in the resistance value of the buffer layer and reduce the power consumption and operating voltage of the Schottky barrier diode. In the invention of claim 7, the thickness of the second layer is 10
It is limited to the range of nm to 300 nm. When the thickness of the second layer is 10 nm or more, the resistance and voltage between the first and second electrodes during the operation of the Schottky barrier diode are relatively small. That is, if the thickness of the second layer is 1
When the thickness is less than 0 nm, discrete energy levels are generated in the valence band and the conduction band of the second layer, and the energy level involved in the conduction of carriers in the second layer apparently increases. As a result, the energy band discontinuity between the substrate and the second layer becomes relatively large, and the resistance and voltage between the first and second electrodes during the operation of the Schottky barrier diode become relatively large. . On the other hand, when the thickness of the second layer is 10 nm or more, generation of discrete energy levels in the valence band and conduction band of the second layer is suppressed,
The increase in the energy level involved in the conduction of carriers in the layer is suppressed. As a result, deterioration of the energy band discontinuity between the substrate and the second layer is suppressed, and the resistance and voltage between the first and second electrodes during operation of the Schottky barrier diode are reduced. According to the invention of claim 8,
Not only can the second layer be an n-type semiconductor region, but the second layer contains impurities, so that the resistance is reduced,
The resistance and voltage between the first and second electrodes can be reduced, and a Schottky barrier diode with less power loss can be provided. According to the invention of claim 7, the buffer layer and the semiconductor region can be favorably formed on the substrate, and the efficiency of the shutter barrier diode can be improved. That is, by making the plane orientation of the main surface of the substrate a (111) just plane or a plane having a small off-angle from the (111) just plane, atomic steps of the crystal surface of the buffer layer and the semiconductor region, that is, steps at the atomic level. Can be eliminated or reduced. If (11
1) When the buffer layer and the semiconductor region are formed on the main surface having a large off-angle from the just surface, a relatively large step is generated in the buffer layer and the semiconductor region at the atomic level. On the contrary,
If the main surface of the substrate is a (111) just surface or a surface with a small off-angle, the step becomes small. According to the eleventh aspect of the present invention, it is possible to inexpensively and easily form the Schottky barrier diode having excellent characteristics.

[0008]

First Embodiment Next, a Schottky barrier diode using a gallium nitride-based compound semiconductor according to a first embodiment of the present invention will be described with reference to FIGS.

The Schottky barrier diode according to the first embodiment of the present invention shown in FIG.
A semiconductor substrate 4 composed of a buffer layer 2 and a GaN semiconductor region 3, and one main surface of the semiconductor substrate 4, that is, G
A first electrode 5 in contact with the main surface of the aN semiconductor region 3 in a shallow barrier and a second electrode 6 in ohmic contact with the other main surface of the semiconductor substrate 4, that is, the lower surface of the silicon substrate 1.
And an insulating film 7.

The semiconductor region 3 is composed of n-type GaN (gallium nitride) doped with Si (silicon) as an n-type impurity. A shock barrier occurs between the semiconductor region 3 and the first electrode 5.

The substrate 1 is made of an n ^{+ type} silicon single crystal containing As (arsenic) as an n type conductivity determining impurity. One main surface 1a of the substrate 1 on the side where the buffer layer 2 is arranged has a crystal orientation (11
1) Just side. The impurity concentration of As (arsenic) of the substrate 1 is 5 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁹ c.
m ⁻³ , and the resistivity of this substrate 1 is 0.0001Ω
-Cm to 0.01 Ω-cm. The substrate 1 having a relatively low resistivity functions as a current path between the first electrode 5 and the second electrode 6. Also, the substrate 1 is relatively thick, about 3
The semiconductor region 3 and the buffer layer 2 have a thickness of 50 μm.
Function as a support.

The buffer layer 2 arranged so as to cover the entire one main surface of the substrate 1 is a composite layer in which a plurality of first layers 8 and a plurality of second layers 9 are alternately laminated. . Figure 1
Then, for convenience of illustration, the first layer 8 and the second layer of the buffer layer 2 are
In practice, the buffer layer 2 has 20 first layers 8 and 20 second layers 9, although only 2 layers 9 and 9 are shown respectively.

The first layer 8 is formed of a material that can be represented by the chemical formula Al _x Ga _1-x N, where x is any numerical value satisfying 0 <x ≦ 1. That is, the first layer 8 is
It is formed of AlN (aluminum nitride) or AlGaN (gallium aluminum nitride). In the embodiment of FIGS. 1 and 2, Al corresponding to the material in which x in the above formula is 1.
N (aluminum nitride) is used for the first layer 8. The first layer 8 is an extremely thin film having an insulating property. The lattice constant and the thermal expansion coefficient of the first layer 8 are closer to the silicon substrate 1 than the second layer 9.

[0014] The second layer 9, where GaN (gallium nitride) or formula _{Al y Ga 1-y N,} y is y <x and 0 <y <Any numerical value satisfying 1, in the indicated It is an extremely thin film of n-type semiconductor made of a material that can be used. When an n-type semiconductor made of Al _y Ga _{1 -y} N is used as the second layer 9, y is set to 0 <y <0.8 in order to suppress an increase in the electric resistance of the second layer 9. It is desirable to set it to a satisfactory value, that is, larger than 0 and smaller than 0.8. The second layer 9 of the first embodiment
Is composed of GaN corresponding to y = 0 in the above chemical formula. Incidentally, the material of the second layer 9, wherein the chemical formula _{Al y Ga 1-y N,} y can also be expressed by a numerical value, which satisfies y <x and 0 ≦ y <1. The second layer 9 functions as a semiconductor having a relatively small resistance value, and has a function of electrically connecting the first layers 8 to each other.

The thickness T1 of the first layer 8 of the buffer layer 2 is
The thickness is preferably 0.5 nm to 10 nm, that is, 5 to 100 Å, and more preferably 1 nm to 8 nm. When the thickness of the first layer 8 is less than 0.5 nm, the flatness of the n-type semiconductor region 3 formed on the upper surface of the buffer layer 2 cannot be maintained well. When the thickness of the first layer 8 exceeds 10 nm, the quantum mechanical tunnel effect cannot be satisfactorily obtained, and the electrical resistance of the buffer layer 2 increases.

The thickness T2 of the second layer 9 is preferably 0.
It is 5 nm to 300 nm, that is, 5 to 3000 angstroms, and more preferably 10 nm to 300 nm.
When the thickness of the second layer 9 is less than 0.5 nm, that is, 5 angstroms, it is formed under one of the first layer 8 and the second layer 9 formed on the second layer 9. The electrical connection with the other first layer 8 is not achieved well, and the electrical resistance of the buffer layer 2 increases. The thickness of the second layer 9 is 300
When it exceeds nm, that is, 3000 angstrom,
The ratio of the first layer 8 to the entire buffer layer 2 is reduced,
The buffer function becomes relatively small, and the flatness of the semiconductor region 3 cannot be kept good.

FIG. 4 shows the relationship between the thickness T2 of the second layer 9 and the forward voltage Vf during operation of the Schottky barrier diode. As is clear from FIG. 4, the thickness T2
Is smaller than 10 nm, the voltage Vf is high, and when the thickness T2 is 10 nm or larger, the voltage Vf is high.
Becomes smaller. When the thickness T2 of the second layer 9 is less than 10 nm, the electrical connection function between the first layer 8 and the second layer 9 is deteriorated, and the energy between the silicon substrate 1 and the second layer 9 is reduced. Band discontinuity increases. That is,
When the thickness of the second layer 9 is less than 10 nm, discrete energy levels are generated in the valence band and the conduction band of the second layer 9 and are involved in the conduction of carriers in the second layer 9. The energy level apparently increases. That is, the first layer 8
And the second layer 9 are in a superlattice state. As a result, the discontinuity of the energy band between the substrate 1 and the second layer 9 becomes relatively large, and the resistance between the first and second electrodes 5 and 6 and the voltage Vf become relatively large. On the other hand, when the thickness of the second layer 9 is 10 nm or more, generation of discrete energy levels in the second 9-valence band and the conduction band is suppressed, and the conduction of carriers in the second layer 9 is suppressed. The increase in the energy level associated with is suppressed. That is, the first layer 8 and the second layer 9 are prevented from becoming a superlattice state.
As a result, the deterioration of the discontinuity of the energy band between the substrate 1 and the second layer 9 is suppressed, and the first and second electrodes 5,
The resistance between 6 and the voltage Vf becomes low. In this example,
The thickness T1 of the first layer 8 is 5 nm and the thickness T2 of the second layer 9 is 30 nm.

Next, a method of manufacturing a semiconductor semiconductor device in which the first layer 8 is AIN and the second layer 9 is GaN will be described.

First, a substrate 1 made of an n ^{+ type} silicon semiconductor in which an n type impurity is introduced at a high concentration as shown in FIG.
To prepare. One main surface 1a of the silicon substrate 1 on the side where the buffer layer 2 is formed is a (111) just plane, that is, an exact (11) plane in the crystal plane orientation shown by the Miller index.
1) surface. However, in FIG.
1) Substrate 1 within the range of -θ to + θ with respect to the just surface
The main surface 1a of can be inclined. The range of −θ to + θ is −4 ° to + 4 °, preferably −3 ° to + 3 °, and more preferably −2 ° to + 2 °. By setting the crystal orientation of the main surface 1a of the silicon substrate 1 to be a (111) just plane or a plane having a small off angle from the (111) just plane, atoms at the time of epitaxial growth of the buffer layer 2 and the device semiconductor region 3 Steps at the level can be eliminated or reduced.

Next, as shown in FIG. 3B, a well-known MOCVD (Metal Organic Chromium) is formed on the main surface 1a of the substrate 1.
The buffer layer 2 is formed by repeatedly stacking the first layer 8 made of AlN and the second layer 9 made of GaN by the metal organic chemical vapor deposition method. That is, the n-type silicon single crystal substrate 1 pretreated with the HF-based etchant is placed in the reaction chamber of the MOCVD apparatus, and first, thermal annealing is performed at 950 ° C. for about 10 minutes to remove the oxide film on the surface. next,
TMA (trimethylaluminum) gas and N in the reaction chamber
H ₃ (ammonia) gas is supplied for about 24 seconds, and the substrate 1
A first layer 8 made of an AlN layer having a thickness of about 5 nm is formed on one of the main surfaces. In this embodiment, the heating temperature of the substrate 1 is set to 11
After the temperature is set to 20 ° C., the flow rate of TMA gas, that is, the supply amount of Al is about 63 μmol / min, the flow rate of NH ₃ gas, that is, NH ₃
Was supplied at about 0.14 mol / min. Then, the heating temperature of the substrate 1 is set to 1120 ° C., the supply of TMA gas is stopped, and then TMG (trimethylgallium) gas, NH ₃ (ammonia) gas and SiH ₄ (silane) gas are supplied for about 90 seconds into the reaction chamber. Then, a second layer 9 of n-type GaN having a thickness of about 30 nm is formed on the upper surface of the first layer 8 of AlN formed on one main surface of the substrate 1. In this embodiment, the flow rate of TMG gas, that is, the supply amount of Ga is about 60 μmol / min, and the flow rate of NH ₃ gas, that is, N.
H ₃ supply rate is about 0.14 mol / min, SiH
₄ (silane) gas flow rate, that is, SiH ₄ supply amount of about 21 n
It was set to mol / min. Here, the SiH ₄ (silane) gas is for introducing Si as an n-type impurity into the second layer 9. In the present embodiment, the formation of the first layer 8 made of AlN and the second layer 9 made of GaN described above is repeated 20 times to form the first layer 8 made of AlN and the second layer 9 made of GaN. Buffer layer 2 in which 40 layers are laminated in total
To get Of course, the first layer 8 made of AlN and the second layer 9 made of GaN can be changed to an arbitrary number such as 50 layers.

Next, a well-known MOC is formed on the upper surface of the buffer layer 2.
The n-type semiconductor region 3 is formed by the VD method. That is, the substrate 1 having the buffer layer 2 formed on the upper surface is placed in the reaction chamber of the MOCVD apparatus, and trimethylgallium gas, that is, TMG gas, NH ₃ (ammonia) gas, and SiH ₄ (silane) gas are first placed in the reaction chamber. Then, the semiconductor region 3 made of n-type GaN having a thickness of about 150 nm is formed on the upper surface of the buffer layer 2. In this embodiment, the flow rate of TMG gas, that is, G
The supply amount of a is about 4.3 μmol / min, the flow rate of NH ₃ gas, that is, the supply amount of NH ₃ is about 53.6 mmol / min, S
The supply amount of iH ₄ (silane) gas, that is, SiH ₄ is about 1.5 n.
It was set to mol / min.

After that, the silicon substrate 1 on which the semiconductor region 3 and the buffer layer 2 are formed is taken out from the MOCVD apparatus, and an insulating film 7 made of a silicon oxide film is formed on the entire surface of the semiconductor region 3 by well-known plasma CVD. The thickness of the insulating film 7 is about 100 nm.

Next, after forming an opening for the first electrode 5 in the insulating film 7 by using photolithography and a hydrofluoric acid type etchant, Pd (paradium), Ti (titanium) is formed by using electron beam evaporation or the like. ), Au (gold) is vapor-deposited and lifted off to form the first electrode 5 having a function as a shell barrier electrode. The first electrode 5 has a circular planar shape as shown in FIG. 2, and is arranged substantially at the center of the upper surface of the semiconductor substrate 4. In the region of the upper surface of the semiconductor substrate 4 where the first electrode 5 is not formed, S
The insulating film 7 made of iO ₂ is formed by the CVD method.

The second electrode 6 is formed by sequentially vacuum-depositing, for example, Ti (titanium) and nickel on the entire other main surface of the substrate 1.

According to this embodiment, the following effects can be obtained. (1) Since the silicon substrate 1 has conductivity, the first electrode 5 as a checkered barrier electrode is formed on the upper surface of the n-type semiconductor region 3 of the semiconductor substrate 4, and the lower surface of the silicon substrate 1 as a cathode electrode is formed. The second electrode 6 can be formed. Therefore, it was necessary in the manufacture of conventional sheet yachts key barrier diode, a part of the n ^one type semiconductor region formed on the upper surface of the n + type semiconductor region to form an ohmic electrode process is unnecessarily removed by etching Become. Therefore, it is possible to prevent defects and the like from being generated on the surface of the n-type semiconductor region 3 due to etching damage,
Further, it is possible to prevent a part of ions of the etching material from penetrating into the inside of the crystal of the surface which is not etched to deteriorate the crystal. As a result, good diode characteristics can be obtained. (2) The thermal conductivity of the silicon substrate 1 is about 1.4 W / cm · K, which is about 10 times that of sapphire.
The heat generated during the operation of the device can be sufficiently dissipated through the silicon substrate 1. As a result, good diode characteristics are obtained, and the element is not destroyed even in the large current region. (3) The robust sapphire substrate is not used, and the silicon substrate 1 that is easy to process and inexpensive is used, so that it is possible to improve the productivity of the shutter barrier diode and reduce the manufacturing cost. (4) Substrate 1 The buffer layer 2 made of a composite layer of the first layer 8 made of AlN and the second layer 9 made of GaN formed on the one main surface contributes to improvement of crystallinity and flatness of the semiconductor region 3. . That is, the buffer layer 2 can favorably take over the crystal orientation of the substrate 1 made of silicon. As a result, the n-type semiconductor region 3 can be favorably formed on the main surface of the buffer layer 2 with the crystal orientations aligned. Therefore, the characteristics of the GaN semiconductor region 3 are improved and the diode characteristics are also improved. (5) When the semiconductor region 3 made of a nitride-based compound is formed via the buffer layer 2 formed by laminating a plurality of first layers 8 and second layers 9, the flatness of the semiconductor region 3 is improved.
That is, if one main surface of the substrate 1 made of silicon is
When a buffer layer composed of only the aN semiconductor layer is formed, a large difference in lattice constant between silicon and GaN makes it impossible to form a GaN-based semiconductor region having excellent flatness on the upper surface of this buffer layer. Further, if the buffer layer 2 is formed relatively thick only with the first layer 8,
The resistance of the buffer layer increases. Moreover, if the buffer layer 2 is formed to be relatively thin with only the first layer 9, a sufficient buffer function cannot be obtained. On the other hand, in the present embodiment, the composite of the first layer 8 made of AlN and the second layer 9 made of GaN between the substrate 1 and the GaN semiconductor region 3 has a relatively small lattice constant difference from silicon. Since the buffer layer 2 composed of layers is interposed, the flatness of the GaN semiconductor region 3 is improved. As a result, a Schottky barrier is favorably formed between the GaN semiconductor region 3 and the first electrode 5. (6) Since the first electrode 5 and the second electrode 6 are arranged so as to face each other, if a forward voltage is applied between them,
A forward current flows in the thickness direction (longitudinal direction) of the semiconductor substrate 4. Therefore, the resistance value and the voltage between the first electrode 5 and the second electrode 6 can be reduced, and the power consumption can be reduced. (7) A plurality of first layers 8 included in the buffer layer 2
Since each of them is set to a thickness at which a quantum mechanical tunnel effect occurs, an increase in the resistance of the buffer layer 2 can be suppressed. (8) It is possible to suppress the occurrence of strain due to the difference in thermal expansion coefficient between the substrate 1 and the GaN semiconductor region 3. That is, since the coefficient of thermal expansion of silicon and the coefficient of thermal expansion of GaN are significantly different, if the both are directly laminated, distortion due to the difference in coefficient of thermal expansion is likely to occur. However, in this embodiment, the first layer 8 and the second layer
The coefficient of thermal expansion of the buffer layer 2 composed of the composite layer of the layer 9 and the layer 9 has an intermediate value between the coefficient of thermal expansion of the substrate 1 and the coefficient of thermal expansion of the GaN semiconductor region 3. Therefore, the buffer layer 2 can suppress the occurrence of strain due to the difference in thermal expansion coefficient between the substrate 1 and the GaN semiconductor region 3. (9) A cathode electrode, that is, a second electrode 6 as compared with a conventional Schottky barrier diode using a sapphire substrate.
Formation is facilitated. That is, in the case of a conventional Schottky barrier diode using a sapphire substrate, a part corresponding to the n-type semiconductor region 3 of FIGS. 1 and 2 is removed and provided below the n-type semiconductor region 3. to expose part of the n ⁺ type semiconductor region, cathode to the exposed n ⁺ type semiconductor region - it has become necessary to connect the cathode electrode. Therefore, the conventional Schottky barrier diode has a drawback that the cathode electrode is difficult to form, and that the area of the n-type semiconductor region is large to form the cathode electrode. The Schottky barrier diode of FIGS. 1 and 2 does not have the above drawbacks. (10) The crystal orientation of the main surface 1a of the silicon substrate 1 is set to (1
11) Since the surface is just, the number of steps in the semiconductor region 3 is reduced.

[0026]

Second Embodiment The configuration of the buffer layer 2 of the first embodiment can be changed. FIG. 5 shows a part of the buffer layer 2a according to the second embodiment that can be used for a Schottky barrier diode. The buffer layer 2a in FIG. 5 is formed by alternately stacking a plurality of first layers 8a and a plurality of second layers 9a. The first layer 8a is represented by the chemical formula Al _x In _y Ga _1-xy N, where x and y are represented by 0 <x ≦ 1, 0 ≦ y <1, and x + y ≦ 1. It is made of a material that can That is, the first layer 8a is made of AlN (aluminum nitride), AlGaN (gallium aluminum nitride),
AlInN (Indium Aluminum Nitride), and A
It is formed of a material selected from lInGaN (gallium indium aluminum nitride). In the embodiment of FIG. 5, the formula of x is 0.5, y is equivalent to material which is a _{0.01 Al 0.5 In 0.01 Ga 0.4 9} N first layer 8a
Is used for. The first layer 8a is an extremely thin film having an insulating property. The first layer 8a containing aluminum has a lattice constant and a thermal expansion coefficient which are intermediate values between the lattice constant and the thermal expansion coefficient of the silicon substrate 1 and the semiconductor region 3.

The second layer 9a is of the chemical formula Al _a In _b Ga _{1 -ab} N, where a and b are any numerical values satisfying 0 ≦ a <1, 0 ≦ b <1, a + b ≦ 1, It is a thin film of semiconductor made of a material that can be represented by. That is, the second layer 9a is formed of, for example, GaN, AlN, InN, InGaN, AlGaN, A.
It is formed of one selected from lInN and AlInGaN. In the embodiment of FIG. 5, a in the above equation is 0.05,
Al _0.05 In _0.35 corresponding to the material in which b is _0.35
Ga _0.6 N is used for the second layer 9a. The gap between the valence band and the conduction band of the second layer 9a, that is, the band gap, is larger than the band gap of the first layer 8a.
In order to reduce the resistance of the second layer 9a, the Al content a
Is smaller than the Al ratio x of the first layer 8a, for example, 0.
It is desirable to set it to 8 or less, more preferably 0.1 or less. The second layer 9a functions as a semiconductor having a relatively small resistance value, and has a function of electrically connecting the first layers 8a to each other.

Next, the first layer 8a is formed of Al _0.5 In _0.01 G.
a _0.49 N, the second layer 9a is Al _0.05 In _0.35 Ga _0.6 N
A method of manufacturing the buffer layer 2a that has been described will be described. The buffer layer 2a is formed on the main surface 1a of the substrate 1 having a (111) just surface similar to that of the first embodiment. The buffer layer 2a is formed by the well-known MOCVD (Metal Organic Chem).
ical vapor deposition), that is, the first layer 8a made of Al _0.5 In _0.01 Ga _0.49 N and the second layer 9 made of Al _0.05 In _0.35 Ga _0.6 N by metal organic chemical vapor deposition.
It is formed by repeatedly laminating a and a. That is,
The silicon single crystal substrate 1 is placed in a reaction chamber of an MOCVD apparatus, and first, thermal annealing is performed to remove the oxide film on the surface. Next, TMA (trimethylaluminum) gas, TMG (trimethylgallium) gas, TMIn (trimethylindium) gas and NH3 are placed in the reaction chamber.
(Ammonia) gas is supplied for about 24 seconds to form a first layer 8a of Al _0.5 In _0.01 Ga _0.49 N having a thickness T1 of about 5 nm, that is, about 50 angstroms on one main surface of the substrate 1.
To form. In this embodiment, the heating temperature of the substrate 1 is 800 ° C.
After that, the flow rate of TMA gas, that is, the supply amount of Al is about 1
4 μmol / min, TMG gas flow rate 31 μmol
/ Min, the flow rate of TMIn gas is 47 μmol / mi
n, flow rate of NH ₃ gas, that is, NH ₃ supply amount is about 0.23 m
ol / min. Then, the supply of TMA gas, TMG gas and TMIn gas is stopped, and the heating temperature of the substrate 1 is set to 7
Lower the temperature to 50 ° C, then TMA gas, TMG gas,
TMIn gas, NH ₃ (ammonia) gas, and S
The iH ₄ gas is supplied for about 83 seconds to form a second layer 9a of Al _0.05 In _0.35 Ga _0.6 N having a thickness T2 of 30 nm, that is, 300 Å on the upper surface of the first layer 8a. SiH ₄ gas is for introducing Si as an n-type impurity. In this embodiment, the flow rate of TMA gas is 2.8 μmol / min and the flow rate of TMG gas is 46.
μmol / min, flow rate of TMIn gas is 59 μmol
/ Min, the flow rate of NH ₃ gas, that is, the supply amount of NH ₃ is about 0.
23 mol / min, the flow rate of SiH ₄ gas, that is, the supply amount of SiH ₄ was set to about 21 nmol / min. In this embodiment, the above-described Al _0.5 In _0.01 Ga _{0 .49} formation of the first layer 8a and the second layer 9a made of Al _0.05 In _0.35 Ga _0.6 N of N was repeated 10 times Al _0.5 In _0.01 Ga
First layer 8a of _0.49 N and Al _0.05 In _0.35 Ga
_The buffer layer 2a is formed by alternately stacking 20 layers of the second layers 9a of _0.6 N. Of course Al _0.5 In _0.01 G
a _0.49 N first layer 8a, Al _0.05 In _0.35 Ga
The second layer 9a made of _0.6 N can be changed to any number such as 50 layers.

The buffer layer 2a of the second embodiment shown in FIG. 5 has the same effect as that of the first embodiment shown in FIG. 1, and further, since the buffer layer 2a contains indium, the buffer layer 2a has the same effect. Buffer layer 2 as compared to the case where indium is not included
It has an effect that the coefficient of thermal expansion of a can be approximated to that of the silicon substrate 1.

[0030]

[Third Embodiment] A buffer layer 2b of a third embodiment shown in FIG. 6 is a modification of the buffer layer 2 of FIG. 1, and is formed by alternately laminating first and second layers 8b and 9b. Become. The first layer 8b is here formula _{Al x B y Ga 1-xy} N, x, y are, 0 <x ≦ 1, 0 ≦ y <1, any numerical value satisfying x + y ≦ 1 be represented by, It is made of a material that can That is, the first layer 8b is formed of AlN (aluminum nitride), AlGaN (gallium aluminum nitride),
AlBN (Boron Nitride Aluminum) and AlBG
It is made of a material selected from aN (gallium boron aluminum nitride). In the embodiment of FIG. 6, Al _0.5 corresponding to a material in which x is 0.5 and y is 0 in the above formula.
Ga _0.5 N is used for the first layer 8b. The first layer 8b is an extremely thin film having an insulating property. First layer 8b
The lattice constant and the thermal expansion coefficient of are closer to those of the silicon substrate 1 than those of the second layer 9b.

The second layer 9b has a chemical formula of Al _a B _b Ga _1-ab N, where a and b are any numerical values satisfying 0 ≦ a <1, 0 ≦ b <1, a + b ≦ 1, It is a thin film of semiconductor made of a material that can be represented by. That is, the second layer 9b is made of Al,
A layer containing at least one element selected from B and Ga and N, for example, GaN, BN, AlN, BGa
It is formed of one selected from N, AlGaN, AlBN, and AlBGaN. In the embodiment of FIG. 6, B _0.3 Ga corresponding to a material in which a is 0 and b is 0.3 in the above formula
_0.7 N is used for the second layer 9b. Second layer 9b
The gap between the valence band and the conduction band, that is, the band gap is larger than the band gap of the first layer 8b.

The buffer layer 2b comprises a first layer 8b made of Al _0.5 Ga _0.5 N and a B _0.3 Ga layer formed on the main surface 1a of the substrate 1 having the (111) just plane by the well-known MOCVD, that is, metalorganic chemical vapor deposition. It is formed by repeatedly laminating the second layer 9b made of _0.7 N. That is, the silicon single crystal substrate 1 is placed in the reaction chamber of the MOCVD apparatus, and first, thermal annealing is performed to remove the oxide film on the surface. Next, in the reaction chamber, TMA (trimethylaluminum) gas, TMG (trimethylgallium) gas,
NH ₃ (ammonia) gas is supplied for about 27 seconds, and the first layer 8b made of Al _0.5 Ga _0.5 N having a thickness T1 of about 5 nm, that is, about 50 angstroms is formed on one main surface of the substrate 11.
To form. In this embodiment, the heating temperature of the substrate 1 is 1080
After the temperature is set to ℃, the flow rate of TMA gas, that is, the supply amount of Al is about 31 μmol / min, and the flow rate of TMG gas is 31 μmo.
The flow rate of NH ₃ gas, that is, the supply amount of NH ₃ was set to about 0.14 mol / min. Then, the supply of TMA gas is stopped, the heating temperature of the substrate 1 is lowered to 1120 ° C.,
After that, about 8 TEB (triethylboron) gas, TMG gas, NH ₃ (ammonia) gas, and SiH ₄ gas are added.
After being supplied for 5 seconds, the thickness T2 is 3 on the upper surface of the first layer 8b.
0 nm or 300 angstrom n-type B _0.3 Ga
_A second layer 9b made of _0.7 N is formed. In addition, SiH ₄
The gas is for introducing Si as an n-type impurity into the second layer 9b. In this embodiment, the TEB gas flow rate, that is, the boron supply amount is 75 μmol / min, the TMG gas flow rate, that is, the gallium supply amount is 63 μmol / min,
The flow rate of NH ₃ gas, that is, the supply amount of NH ₃ is about 0.14 mol.
/ Min, the flow rate of SiH ₄ gas, that is, the supply amount of SiH ₄ was about 21 nmol / min. In the present embodiment, the above A
1 _0.5 Ga _0.5 N first layer 8b and B _0.3 Ga _0.7 N
The formation of the second layer 9b consisting of Al is repeated 10 times.
A buffer layer 2b is formed by alternately stacking a total of 20 first layers 8b made of _0.5 Ga _0.5 N and second layers 9b made of B _0.3 Ga _0.7 N. Of course, the first layer 8b made of Al _0.5 Ga _0.5 N and the second layer 9b made of B _0.3 Ga _0.7 N can be changed to an arbitrary number such as 50 layers.

The buffer layer 2b of FIG. 6 has the same effect as the buffer layer 2 of FIG. 1, and further, since the second layer 9b contains boron, the second layer 9b does not contain boron. As compared with the case, it is more robust, and has an effect that the second layer 9b can be formed relatively thick while preventing the occurrence of cracks.

[0034]

Fourth Embodiment Next, a semiconductor device of a fourth embodiment will be described with reference to FIG. However, in FIG. 7, parts that are substantially the same as those in FIG. 1 are assigned the same reference numerals and explanations thereof are omitted.

The semiconductor device shown in FIG. 7 is obtained by providing a transistor 20 as another semiconductor element on the silicon substrate 1 of the Schottky barrier diode shown in FIG. The transistor 20 comprises a collector region C, a base region B and an emitter region E formed in a P-type semiconductor region 21 for element isolation. In this way, by combining the Schottky barrier diode and the transistor, it is possible to reduce the size and cost of the circuit device including them.

[0036]

[Modification] The present invention is not limited to the above-described embodiment, and the following modifications are possible. (1) The substrate 1 can be made of polycrystalline silicon other than single crystal silicon or a silicon compound such as SiC. (2) The conductivity type of each layer of the semiconductor substrate 4 can be reversed from that of the embodiment. (3) The semiconductor region 3 is formed of GaN (gallium nitride), A
lInN (indium aluminum nitride), AlGa
A gallium nitride-based compound semiconductor or an indium nitride-based compound semiconductor selected from N (gallium aluminum nitride), InGaN (gallium indium aluminum), and AlInGaN (gallium indium aluminum nitride) can be used. (4) First layers 8, 8 of the buffer layers 2, 2a, 2b
The number of a and 8b is one more than that of the second layers 9, 9a and 9b, and the uppermost layer of the buffer layers 2, 2a and 2b is the first layer 8,
8a, 8b. On the contrary, the number of the second layers 9, 9a and 9b can be increased by one layer more than the number of the first layers 8, 8a and 8b. (5) First layers 8, 8a, 8b and second layers 9, 9
a and 9b may contain impurities as long as they do not hinder these functions. (6) A laminated body including an AlN layer and a GaInN layer can be further interposed between the substrate 1 and the buffer layers 2, 2a and 2b. Thereby, the forward voltage of can be further reduced.

[Brief description of drawings]

FIG. 1 is a central longitudinal sectional view schematically showing a sailboat barrier diode according to a first embodiment of the present invention.

FIG. 2 is a perspective view of the sailboat barrier diode of FIG.

FIG. 3 is a cross-sectional view showing the structure of the sailboat barrier diode of FIG. 1 in an enlarged manner in the order of manufacturing steps.

4 is a diagram showing the relationship between the thickness and the voltage of the second layer of the buffer layer of the sailboat barrier diode of FIG.

FIG. 5 is a cross-sectional view showing a part of a substrate and a buffer layer of the sailboat barrier diode of the second embodiment.

FIG. 6 is a cross-sectional view showing a part of a substrate and a buffer layer of a sailboat barrier diode according to a third embodiment.

FIG. 7 is a cross-sectional view showing a semiconductor device including a sailboat barrier diode according to a fourth embodiment.

[Explanation of symbols]

1 Substrate made of silicon single crystal 2, 2a, 2b buffer layer 8, 8a, 8b First layer 9, 9a, 9b Second layer 3 Semiconductor area

Continued front page    F-term (reference) 4M104 AA04 BB07 BB14 CC03 DD99                       GG03                 5F038 AV05 AV20 EZ02 EZ14 EZ20                 5F045 AA04 AB09 AB14 AB17 AB18                       AC01 AC08 AC12 AD15 AF03                       AF13 BB08 DA53 EB13 EE12

Claims (11)

[Claims] 1. A substrate comprising a nitride compound semiconductor, comprising a substrate made of silicon or a silicon compound containing impurities and having a low resistivity, and one main surface of the substrate. A buffer layer disposed on the buffer layer, a nitride-based compound semiconductor region disposed on the buffer layer, a first electrode in contact with the surface of the semiconductor region in a Schottky barrier, and on the other main surface of the substrate. A second electrode in ohmic contact, the buffer layer comprising:
Here the formula _{Al x M y Ga 1-xy} N, wherein M is, In
At least one element selected from (indium) and B (boron), and the material in which x and y are values satisfying 0 <x ≦ 1, 0 ≦ y <1, x + y ≦ 1, And a chemical formula of Al _a M _b Ga _{1 -ab} N, wherein M is at least one element selected from In (indium) and B (boron), and a and b are A yacht barrier barrier diode comprising a composite layer of a material represented by 0 ≦ a ≦ 1, 0 ≦ b <1, and a + b ≦ 1 and a second layer formed of the material. 2. The seashore barrier according to claim 1, wherein the first layer is made of Al _x Ga _1-x N and the second layer is made of Al _a Ga _1-a N. diode. 3. The first layer is Al _x In _y Ga _1-xy N
The second layer is made of Al _a In _b Ga _{1 -ab} N, and In is contained in at least one of the first and second layers.
The yacht barrier diode according to claim 1, which contains (indium). Wherein said first layer consists _{Al x B y G a1-xy} N, wherein the second layer is Al _a consist B _b G _a1-ab N, wherein the first and second The chain barrier diode according to claim 1, wherein B (boron) is contained in at least one of the layers. 5. The buffer layer comprises a plurality of the first and second layers, and the first layers and the second layers are alternately laminated. Alternatively, the sailboat barrier diode according to 2 or 3 or 4. 6. The buffer layer according to claim 1, wherein the first layer has a thickness of 0.5 nm to 10 nm, and the second layer has a thickness of 0.5 nm to 300 nm. 3. A sailboat barrier diode according to 3. 7. The buffer layer according to claim 1, wherein the first layer has a thickness of 0.5 nm to 10 nm, and the second layer has a thickness of 10 nm to 300 nm. Cayottki barrier diode. 8. The sailboat barrier diode according to claim 1, wherein the second layer contains silicon as an n-type impurity. 9. The main surface of the substrate on the side where the buffer layer is arranged is in the (111) just plane or in the range of −4 to +4 degrees from the (111) plane in the crystal plane orientation indicated by the Miller index. The sailboat barrier diode according to claim 1, wherein the sailboat barrier diode is a surface that is inclined at. 10. The semiconductor region comprises GaN (gallium nitride), AlInN (indium aluminum nitride), AlGaN (gallium aluminum nitride), I.
nGaN (Indium gallium nitride), and AlIn
The chain barrier diode according to claim 1, wherein the shell diode is selected from GaN (gallium indium aluminum nitride). 11. A method for manufacturing a chain barrier diode using a nitride-based compound semiconductor, comprising the steps of providing a substrate made of silicon or a silicon compound containing impurities and having a low resistivity, on one main surface of the substrate, by a vapor deposition method, wherein the chemical formula _{Al x M y Ga 1-xy} N, wherein M is, an in (indium) and B (boron)
At least one element selected from, x and y are 0 <x ≦ 1, 0 ≦ y <1, x + y ≦ 1, and a first layer made of a material represented by the following chemical formula: Al _a M _b Ga _{1 -ab} N, where M is at least one element selected from In (indium) and B (boron), and a and b are 0 <a ≦ 1 and 0 ≦ b <1 and a value satisfying a + b ≦ 1 are sequentially formed to obtain a buffer layer, and a nitride-based compound semiconductor region is formed on the buffer layer. A step of forming by vapor phase growth, a step of forming a first electrode in contact with the silicon barrier on the surface of the semiconductor region, and a step of forming a second electrode in ohmic contact with the other main surface of the substrate. Cayott Kibalia Daio characterized by having The method of production.