JP2006216576A - Compound semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compound semiconductor device exhibiting high efficiency and a high breakdown voltage while reducing energy loss. <P>SOLUTION: On an Si single crystal substrate 2 of n conductivity type having a crystal face orientation of ä111} and carrier concentration of 10<SP>16</SP>-10<SP>21</SP>/cm<SP>3</SP>(≈resistivity of 1-0.00001 Ωcm), a 3C-SiC single crystal buffer layer 3 of n conductivity type having a thickness of 0.05-2 μm and carrier concentration of 10<SP>16</SP>-10<SP>21</SP>/cm<SP>3</SP>, a hexagonal In<SB>w</SB>Ga<SB>x</SB>Al<SB>1-w-x</SB>N single crystal buffer layer 4 (0≤w<1, 0≤x<1, w+x<1) having a thickness of 0.01-0.5 μm, and a hexagonal In<SB>y</SB>Ga<SB>z</SB>Al<SB>1-y-z</SB>N single crystal layer 5 of n conductivity type (0≤y<1, 0<z≤1, y+z≤1) having a thickness of 0.1-5 μm and carrier concentration of 10<SP>11</SP>-10<SP>16</SP>/cm<SP>3</SP>(≈resistivity of 1-100,000 Ωcm) are formed sequentially. Furthermore, a back electrode 6 is formed on the back of the Si single crystal substrate 2 and a surface electrode 7 is formed on the surface of the hexagonal In<SB>y</SB>Ga<SB>z</SB>Al<SB>1-y-z</SB>N single crystal layer 5. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention is represented by 3C-SiC (cubic silicon carbide), GaN (hexagonal gallium nitride), and AlN (hexagonal aluminum nitride) used for short wavelength semiconductor light emitting devices, high frequency and high efficiency semiconductor devices, and the like. The present invention relates to a compound semiconductor device including a compound semiconductor single crystal film such as a nitride.

Compound semiconductors are superior in high-speed signal processing because they have a much higher electron transfer speed than silicon, and have excellent characteristics such as operating at a low voltage, reacting to light, and emitting microwaves. Due to such excellent physical properties, devices using compound semiconductors are expected to surpass the physical property limits of semiconductor silicon, which is currently the mainstream.
Conventionally, for example, a Schottky barrier diode in which a nitride compound semiconductor single crystal layer is stacked on a Si substrate via a buffer layer is known (see Patent Document 1).
JP 2003-60212 A

However, the conventional device manufactured using the compound semiconductor as described above has a high resistance of the buffer layer made of the compound semiconductor single crystal, which causes energy loss. Was considerably lower than the ideal state, and it was difficult to say that it was sufficient for practical use.
Particularly, in the diode having the basic structure, it has been difficult to sufficiently withstand practical use due to energy loss due to a large amount of leakage current.

In the conventional products as described above, the low carrier concentration of the compound semiconductor single crystal buffer layer made of nitrides typified by hexagonal GaN or hexagonal AlN is the cause of high resistance. In the layer, it is physically difficult to increase the carrier concentration.
Moreover, the improvement for relaxation of the electric field concentration in the electrode has not been made sufficiently.

  Therefore, in the compound semiconductor device, in order to fully utilize the excellent characteristics as described above and to expand the application, an improvement measure for reducing the leakage current and increasing the breakdown voltage is required.

  The present invention has been made to solve the above technical problem, and an object of the present invention is to provide a compound semiconductor device with low energy loss, high efficiency, and high breakdown voltage.

The compound semiconductor device according to the present invention has a crystal plane orientation {111}, a carrier concentration of 10 ¹⁶ to 10 ²¹ / cm ³ (≈resistivity 1 to 0.00001 Ωcm), and a conductive n-type Si single crystal substrate. 0.05 to 2 μm, carrier concentration 10 ¹⁶ to 10 ²¹ / cm ³ , conductivity type n-type 3C—SiC single crystal buffer layer, and 0.01 to 0.5 μm thick hexagonal In _w Ga _x Al _{1 -wx} N single crystal buffer layer (0 ≦ w <1, 0 ≦ x <1, w + x <1), thickness 0.1 to 5 μm, carrier concentration 10 ¹¹ to 10 ¹⁶ / cm ³ (≈resistivity 1 to 100000Omucm), conductivity type n-type hexagonal _{in y Ga z Al 1-yz} n single crystal layer (0 ≦ y <1,0 <z ≦ 1, y + z ≦ 1) and are sequentially stacked, and the Si single back electrode on the back surface of the crystal substrate, and the hexagonal _{in y Ga z Al 1-yz} N single crystal layer A surface electrode is formed on the surface.
According to the compound semiconductor device as described above, by setting the crystal plane orientation to {111}, generation of antiphase boundary defects can be reduced and electric field concentration on the defects can be mitigated. It can be made 1.5 times larger than Further, since the carrier concentration can be increased by the 3C—SiC single crystal buffer layer, the resistance can be reduced to about ½ compared to the conventional case when energized.

In the compound semiconductor device, between the Si single crystal substrate and the 3C—SiC single crystal buffer layer, a thickness of 0.01 to 1 μm, a carrier concentration of 10 ¹⁶ to 10 ²¹ / cm ³ , a conductive n-type c− A BP single crystal buffer layer is preferably inserted and formed.
By inserting and forming the c-BP single crystal buffer layer, the carrier concentration of the 3C-SiC single crystal buffer layer can be further increased, and when energized, the resistance can be reduced to about 1/5 compared to the conventional case. .

Further, in the above compound semiconductor device, the hexagonal _{In w Ga x Al 1-wx} N single crystal buffer layer is hexagonal AlN (w = 0, x = 0), and the hexagonal In _y Ga _z Al _{1 The -yz} N single crystal layer is preferably hexagonal GaN (y = 0, z = 1).
The 3C-SiC single crystal buffer layer, hexagonal AlN and hexagonal GaN have lattice constants that change in a stepwise manner and small lattice mismatch, so that misfit dislocations can be reduced, and electric field concentration on misfit dislocations. Can be relaxed, and the breakdown voltage can be doubled compared to the prior art.

The back electrode and the front electrode are each formed of a metal including at least one of Al, Ti, In, Au, Ni, Pt, W, and Pd, and the back electrode is an ohmic junction, a surface electrode is a Schottky junction, and the 3C-SiC single crystal buffer layer, hexagonal _{in w Ga x Al 1-wx} N single crystal buffer layer and the hexagonal _{in y Ga z Al 1-yz} N single crystal layer is an ohmic Bonding is preferable.
By adopting such a configuration, when energized, the resistance can be reduced to about 1/10 compared to the conventional case.

Alternatively, the back electrode and the front electrode are each formed of a metal containing at least one of Al, Ti, In, Au, Ni, Pt, W, and Pd, and the back electrode is an ohmic junction, surface electrode is an ohmic junction, and the 3C-SiC single crystal buffer layer, hexagonal _{in w Ga x Al 1-wx} N single crystal buffer layer and the hexagonal _{in y Ga z Al 1-yz} N single crystal layer A heterojunction having an energy barrier is preferred.
With such a configuration, electric field concentration can be relaxed, and the breakdown voltage can be tripled compared to the conventional case.

Furthermore, in the compound semiconductor device, two or more surface electrodes are formed, each formed of a metal including at least one of Al, Ti, In, Au, Ni, Pt, W, and Pd. In addition, at least one of these surface electrodes is preferably an ohmic junction, and the others are preferably Schottky junctions.
With such a configuration, the 3C-SiC single crystal buffer layer and the Si single crystal substrate, which have a high carrier concentration and are highly conductive, can be used as electrodes, and electric field concentration can be reduced. The breakdown voltage can be quadrupled compared to the conventional case.

Furthermore, it is preferable that an insulating layer and an upper electrode are sequentially laminated on the surface electrode.
By adopting such a configuration, the electric field concentration can be further relaxed, and the breakdown voltage can be increased by a factor of 5 compared to the conventional case.

Further, the surface electrode, the area for each of the 3C-SiC single crystal buffer layer, hexagonal _{In w Ga x Al 1-wx} N single crystal buffer layer and the hexagonal _{In y Ga z Al 1-yz} N single crystal layer The ratio is preferably 0.2 to 0.9.
By setting the area of the surface electrode / the area of each compound semiconductor layer to 0.2 to 0.9, a device with higher efficiency and higher breakdown voltage can be obtained.

As described above, according to the semiconductor compound device of the present invention, the carrier concentration of the buffer layer can be increased, the resistance can be reduced, and the energy loss in the device can be suppressed.
Further, the compound semiconductor device according to the present invention can be suitably used as a Schottky barrier diode or the like because electric field concentration is relaxed, high efficiency and high breakdown voltage.

Hereinafter, the present invention will be described in more detail.
The compound semiconductor device according to the present invention includes a 3C—SiC single crystal buffer layer and a hexagonal In _w Ga _x Al _1-wx N single crystal buffer layer (0 ≦ w <1, 0 ≦ x on a Si single crystal substrate. <1, w + x and <1), hexagonal _{In y Ga z Al 1-yz} N single crystal layer (0 ≦ y <1,0 <z ≦ 1, y + z ≦ 1) and are sequentially stacked, and, Si single back electrode on the back surface of the crystal substrate, and one in which the surface electrode is formed on the surface of the hexagonal _{in y Ga z Al 1-yz} N single crystal layer.
Thus, the buffer layer on the Si single crystal substrate is made of 3C—SiC single crystal and hexagonal In _w Ga _x Al _1-wx N single crystal (0 ≦ w <1, 0 ≦ x <1, w + x <1). By configuring, the carrier concentration can be increased, and when energized, the resistance can be reduced to about ½ compared to the conventional case.

The Si single crystal substrate in the present invention is not limited to those manufactured by the CZ (Czochralski) method, but those manufactured by the FZ (floating zone) method, and vapor phase growth on these Si single crystal substrates. It is also possible to use an Si single crystal layer epitaxially grown (Si epi substrate).
Note that the epitaxial growth has an advantage that a single crystal layer (epi layer) having excellent crystallinity can be obtained and the crystal plane orientation of the substrate can be inherited by the epi layer.

As the Si single crystal substrate, one having a crystal plane orientation {111} is used, and the plane orientation {111} here is a slight inclination (about tens of degrees) of the crystal plane orientation {111}, or { 211} and other higher-order plane index crystal plane orientations are also included.
Thus, by setting the crystal plane orientation {111}, the occurrence of anti-phase boundary defects can be reduced, the electric field concentration on the defects can be reduced, and the breakdown voltage can be increased by 1.5 times compared to the conventional case. can do.

The Si single crystal substrate having a carrier concentration of 10 ¹⁶ to 10 ²¹ / cm ³ is used.
When the carrier concentration is less than 10 ¹⁶ / cm ³ , since the resistance is high, energy loss increases when a Si single crystal substrate is energized. On the other hand, the carrier concentration is preferably as high as possible from the viewpoint of energy loss, but exceeding 10 ²¹ / cm ³ is physically difficult in a Si single crystal.
The lower limit of the carrier concentration of the Si single crystal substrate is preferably 10 ¹⁷ / cm ³ .

The thickness of the Si single crystal substrate is preferably 100 to 1000 μm, and more preferably 200 to 800 μm.
When the thickness of the Si single crystal substrate is less than 100 μm, the mechanical strength is insufficient. On the other hand, when the thickness exceeds 1000 μm, the raw material cost increases, and it cannot be said that an effect commensurate with it is obtained.

The thickness of the 3C—SiC single crystal buffer layer formed on the Si single crystal substrate is 0.05 to 2 μm.
When the thickness of the 3C—SiC single crystal buffer layer is less than 0.05 μm, the buffering effect is insufficient. On the other hand, when the thickness exceeds 2 μm, only the raw material cost increases.
The thickness of the 3C—SiC single crystal buffer layer is more preferably 0.1 to 1 μm.

The conductivity type of the 3C—SiC single crystal buffer layer is n-type.
If the conductivity types are different, a pn junction is formed in the vicinity of the interface between the 3C-SiC single crystal buffer layer and the Si single crystal substrate, and the resistance becomes high and energy loss occurs when energized.

The carrier concentration of the 3C—SiC single crystal buffer layer is 10 ¹⁶ to 10 ²¹ / cm ³ .
When the carrier concentration is less than 10 ¹⁶ / cm ³ , since the resistance is high, energy loss occurs when energized. On the other hand, the carrier concentration is preferably as high as possible from the viewpoint of energy loss, but it is physically difficult to exceed 10 ²¹ / cm ³ .
The lower limit of the carrier concentration of the 3C—SiC single crystal buffer layer is preferably 10 ¹⁷ / cm ³ .

In the semiconductor device, a c-BP single crystal buffer layer is preferably inserted and formed between the Si single crystal substrate and the 3C-SiC single crystal buffer layer, and the thickness thereof is 0.01 to 1 μm. It is preferable.
When the thickness is less than 0.01 μm, the buffer effect and resistance reduction effect of the c-BP single crystal buffer layer are insufficient. On the other hand, when the thickness exceeds 0.5 μm, only the raw material cost increases.

The c-BP single crystal buffer layer is an n-type that has the same conductivity type as the 3C-SiC single crystal buffer layer so that a pn junction is not formed near the interface with the 3C-SiC single crystal buffer layer.
When a pn junction is formed, the resistance increases when energized, resulting in energy loss.

The carrier concentration of the c-BP single crystal buffer layer is preferably 10 ¹⁶ to 10 ²¹ / cm ³ .
When the carrier concentration is less than 10 ¹⁶ / cm ³ , since the resistance is high, energy loss occurs when energized. On the other hand, the carrier concentration is preferably as high as possible from the viewpoint of energy loss, but it is physically difficult to exceed 10 ²¹ / cm ³ .
The lower limit of the carrier concentration of the c-BP single crystal buffer layer is preferably 10 ¹⁷ / cm ³ .

Further, the thickness of the hexagonal In _w Ga _x Al _{1 -wx} N single crystal buffer layer formed on the 3C—SiC single crystal buffer layer is set to 0.01 to 0.5 μm.
When the thickness is less than 0.01 μm, the buffering effect of the hexagonal In _w Ga _x Al _{1 -wx} N single crystal buffer layer becomes insufficient. On the other hand, when the thickness exceeds 0.5 μm, the resistance is high, and thus energy loss occurs when energized.
The thickness of the hexagonal In _w Ga _x Al _1-wx N single crystal buffer layer is more preferably 0.02 to 0.1 μm.

Furthermore, the thickness of the hexagonal In _y Ga _z Al _1-yz N single crystal layer formed on the hexagonal In _w Ga _x Al _{1 -wx} N single crystal buffer layer is 0.1 to 5 μm.
When the thickness is less than 0.1 μm, a desired device having a high breakdown voltage cannot be obtained. On the other hand, if the thickness exceeds 5 μm, only the raw material cost increases.
The thickness of the hexagonal _{In y Ga z Al 1-yz} N single crystal layer is more preferably 0.5 to 4 .mu.m.

Further, the conduction type of the hexagonal _{In y Ga z Al 1-yz} N single crystal layer is an n-type.
When conductivity types are different, 3C-SiC single crystal buffer layer, hexagonal _{In w Ga x Al 1-wx} N pn junction near the interface of the single crystal buffer layer and the hexagonal _{In y Ga z Al 1-yz} N single crystal layer When this is formed and energized, the resistance is high and energy loss occurs.

The carrier concentration of the hexagonal _{In y Ga z Al 1-yz} N single crystal layer, and 10 ¹¹ ~10 ¹⁶ / cm ^3.
The carrier concentration is preferably as low as possible from the viewpoint of compound semiconductor performance, but it is physically difficult to make it less than 10 ¹¹ / cm ³ . On the other hand, if the carrier concentration is higher than 10 ¹⁶ / cm ^3, hexagonal _{In y Ga z Al 1-yz} N single crystal layer is a problem to break at a low voltage.

Wherein in the compound semiconductor device, the hexagonal _{In w Ga x Al 1-wx} N single crystal buffer layer is hexagonal AlN (w = 0, x = 0), and the hexagonal In _y Ga _z Al _1-yz The N single crystal layer is preferably hexagonal GaN (y = 0, z = 1).
The lattice constants of the 3C—SiC single crystal buffer layer, hexagonal AlN, and hexagonal GaN are 3.083Å (a-axis conversion), 3.112Å, and 3.18 変 化, which change stepwise, Since the matching is small, misfit dislocations caused by lattice mismatch can be reduced, and electric field concentration on the misfit dislocations can be mitigated, and the breakdown voltage can be doubled compared to the conventional case.

Further, the back surface electrode formed on a back surface of the Si single crystal substrate, and the hexagonal _{In y Ga z Al 1-yz} N surface electrode formed on the single crystal layer, each Al, Ti, an In, Au , Ni, Pt, W, and Pd are preferably formed of a metal containing at least one of them.
Further, an ohmic junction back electrode, a surface electrode is Schottky junction, and, 3C-SiC single crystal buffer layer, hexagonal _{In w Ga x Al 1-wx} N single crystal buffer layer and the hexagonal In _y Ga _z Al _{1 By forming the -yz} N single crystal layer as an ohmic junction, a device with high efficiency and high breakdown voltage can be obtained.

Alternatively, for the bonding of the layers and electrodes as described above, ohmic junction surface electrodes, 3C-SiC single crystal buffer layer, hexagonal _{In w Ga x Al 1-wx} N single crystal buffer layer and the hexagonal an In _y Ga _z Even when the Al _1-yz N single crystal layer is a heterojunction having an energy barrier, a 3C—SiC single crystal buffer layer and a Si single crystal substrate having a high carrier concentration and high conductivity can be used as electrodes. Therefore, a device with high efficiency and high breakdown voltage can be obtained.

  Further, two or more surface electrodes are formed, and even when at least one of these surface electrodes is an ohmic junction and the others are Schottky junctions, similarly, high efficiency and high breakdown voltage are obtained. A device is obtained.

In addition, by sequentially laminating the insulating layer and the upper electrode on the surface electrode, a device with higher efficiency and higher breakdown voltage can be obtained.
Note that the insulating layer can be formed by a CVD method, an insulator coating method, or the like. The upper electrode can be formed by vacuum deposition, an electron beam gun heating method, or the like.

Furthermore, the area of the surface electrode, the compound 3C-SiC single crystal buffer layer as a semiconductor layer, hexagonal _{In w Ga x Al 1-wx} N single crystal buffer layer and the hexagonal _{In y Ga z Al 1-yz} N It is preferably smaller than each area of the single crystal layer. In particular, the area ratio (area of surface electrode / area of each compound semiconductor layer) is preferably 0.2 to 0.9 from the viewpoint of obtaining a device with higher efficiency and higher breakdown voltage.
In addition, the adjustment method of the area of a surface electrode can be performed by the fine process by the lithography and metal mask which are performed in normal semiconductor device manufacture.

EXAMPLES Hereinafter, although this invention is demonstrated further more concretely based on an Example, this invention is not restrict | limited by the following Example.
[Example 1]
FIG. 1 is a conceptual cross-sectional view of the compound semiconductor device according to this example.
A compound semiconductor device 1 shown in FIG. 1 has a crystal plane orientation {111}, a carrier concentration of 10 ¹⁷ / cm ³ (≈resistivity 0.1 Ωcm), a conduction type n-type Si single crystal substrate 2 having a thickness of 400 μm, Thickness 1 μm, carrier concentration 10 ¹⁷ / cm ³ , conductive n-type 3C—SiC single crystal buffer layer 3, 0.02 μm thick hexagonal In _w Ga _x Al _1-wx N single crystal buffer layer 4 hexagonal AlN (w = 0, x = 0), the thickness of 4 [mu] m, the carrier concentration of 10 ¹⁵ / cm ³ (≒ resistivity 10 .OMEGA.cm), conductivity type n-type hexagonal _{in y Ga z Al 1-yz} n single crystal layer hexagonal GaN as 5 (y = 0, z = 1) are sequentially laminated, and a back electrode 6 on the back surface of the Si single crystal substrate 2, the hexagonal _{in y Ga z Al 1-yz} N single crystal layer 4 A surface electrode 7 is formed on the surface.

Hereinafter, the manufacturing process of this compound semiconductor device 1 will be described.
First, a Si single crystal substrate 2 having a crystal plane orientation {111}, a carrier concentration of 10 ¹⁷ / cm ³ , a conductivity type n type, and a thickness of 400 μm manufactured by the CZ method is heat-treated at 1000 ° C. in a hydrogen atmosphere. The surface was cleaned.
The Si single crystal substrate 2 is heat-treated at 1000 ° C. in a C ₃ H ₈ source gas atmosphere to form a 3C—SiC single crystal buffer layer 3 having a thickness of 10 nm, a carrier concentration of 10 ¹⁷ / cm ³ , and a conductivity type. did.
Subsequently, a SiH ₄ gas and a C ₃ H ₈ gas are used as source gases, and a thickness of 1 μm and a carrier concentration of 10 ¹⁷ / cm ^{3 are formed} on the 3C—SiC single crystal buffer layer 3 by vapor phase growth at 1000 ° C. Further, a conductive n-type 3C—SiC single crystal buffer layer 3 was further laminated to obtain a desired thickness.
The thickness of the 3C—SiC single crystal buffer layer 3 was adjusted by the flow rate and time of the source gas, and the carrier concentration was adjusted by adding N ₂ as a dopant during vapor phase growth.

Next, TMA gas and NH ₃ gas are used as source gases, and a 0.02 μm-thick hexagonal In _w Ga _x Al film is formed on the 3C—SiC single crystal layer buffer layer 3 by vapor phase growth at 1000 ° C. Hexagonal AlN (w = 0, x = 0) as _1-wx N single crystal buffer layer 4 was laminated.
Further, TMG gas and NH ₃ gas are used as source gases, and a thickness of 4 μm and a carrier concentration of 10 ¹⁵ / cm ³ (≈ resistivity 10 Ωcm) are formed on the hexagonal AlN single crystal buffer layer 4 by vapor phase growth at 1000 ° C. ), a laminate of conduction type n-type hexagonal _{in y Ga z Al 1-yz} n hexagonal GaN as a single crystal layer 5 (y = 0, z = 1).
The thicknesses of the hexagonal AlN single crystal buffer layer 4 and the hexagonal GaN single crystal layer 5 were adjusted by the raw material flow rate and time, and the carrier concentration was adjusted low by not adding a dopant during the heat treatment.

Finally, the back electrode 6 was formed by Al vacuum deposition, and the front electrode 7 was formed by Au vacuum deposition. The ohmic junction and Schottky junction of these electrodes were adjusted by heat treatment.
Further, 3C-SiC single crystal buffer layer 3, an ohmic junction of the hexagonal _{In w Ga x Al 1-wx} N single crystal buffer layer 4 and the hexagonal _{In y Ga z Al 1-yz} N single crystal layer 5, the layers The composition (w, x, y, z) was adjusted.

  About the compound semiconductor device 1 obtained by the said manufacturing process, when resistance and a breakdown voltage were measured, resistance was reduced to about 1/100 of the past, and the breakdown voltage increased about 2 times compared with the past, and fully It can withstand practical use.

[Example 2]
FIG. 2 is a conceptual cross-sectional view of the compound semiconductor device according to this example.
The compound semiconductor device 8 shown in FIG. 2 has a crystal plane orientation {111}, a carrier concentration of 10 ¹⁷ / cm ³ (≈resistivity 0.1 Ωcm), a conduction type n-type Si single crystal substrate 2 having a thickness of 400 μm, Thickness 0.5 μm, carrier concentration 10 ¹⁶ to 10 ²¹ / cm ³ , conductive n-type c-BP single crystal buffer layer 9, thickness 1 μm, carrier concentration 10 ¹⁷ / cm ³ , conductive n-type 3C -SiC single crystal buffer layer 3, hexagonal AlN (w = 0, x = 0) as a hexagonal In _w Ga _x Al _{1 -wx} N single crystal buffer layer 4 having a thickness of 0.02 μm, and a thickness of 4 μm a carrier concentration of 10 ¹⁵ / cm ³ (≒ resistivity 10 .OMEGA.cm), the conductivity type n-type hexagonal _{in y Ga z Al 1-yz} n hexagonal GaN as a single crystal layer 5 (y = 0, z = 1) And the back electrode 6 is formed on the back surface of the Si single crystal substrate 2. Made, also, the hexagonal _{In y Ga z Al 1-yz} N plurality of surface electrodes 7 on the surface of the single crystal layer 5, on top of the surface electrode 7, the insulating layer 10 and the upper electrode 11 are sequentially stacked Is.

Hereinafter, the manufacturing process of the compound semiconductor device 8 will be described.
First, on the cleaned Si single crystal substrate 2 in the same manner as in Example 1, PH ₃ gas and B ₂ H ₆ gas were used as source gases, and the thickness was 0.5 μm by vapor growth at 1000 ° C. A conductivity type n-type c-BP single crystal buffer layer 9 having a concentration of 10 ¹⁷ / cm ³ was laminated.
Note that the thickness of the c-BP single crystal buffer layer 9 was adjusted by the flow rate and time of the source gas, and the carrier concentration was adjusted by the flow rate of the source gas.

Next, SiH ₄ gas and C ₃ H ₈ gas are used as source gases, and a thickness of 1 μm and a carrier concentration of 10 ¹⁷ / cm ^{3 are formed} on the c-BP single crystal buffer layer 9 by vapor phase growth at 1000 ° C. A conductive n-type 3C—SiC single crystal buffer layer 3 was laminated.
The thickness of the 3C—SiC single crystal buffer layer 3 was adjusted by the flow rate and time of the source gas, and the carrier concentration was adjusted by adding N ₂ as a dopant during vapor phase growth.

Then, the hexagonal _{In w Ga x Al 1-wx} N hexagonal AlN as a single crystal buffer layer 4 (w = 0, x = 0) and conductivity type n-type hexagonal _{In y Ga z Al 1-yz} N single Hexagonal GaN (y = 0, z = 1) as the crystal layer 5 was sequentially laminated in the same manner as in Example 1.

Next, the back electrode 6 was formed by vacuum deposition of Al, and the plurality of surface electrodes 7 were formed by separately performing vacuum deposition of Al and Au. The ohmic junction and Schottky junction of these electrodes were adjusted by heat treatment.
Further, 3C-SiC single crystal buffer layer 3, an ohmic junction of the hexagonal _{In w Ga x Al 1-wx} N single crystal buffer layer 4 and the hexagonal _{In y Ga z Al 1-yz} N single crystal layer 5, the layers The composition (w, x, y, z) was adjusted.

Finally, the insulating layer 10 and the upper electrode 11 were sequentially laminated on the surface electrode 7.
When the resistance and breakdown voltage of the compound semiconductor device 8 obtained by the above manufacturing process were measured, the resistance was reduced to about 1/200 of the conventional one, and the breakdown voltage was increased to about five times that of the conventional one. Can withstand practical use.

1 is a cross-sectional view conceptually showing a compound semiconductor device according to Example 1. FIG. 6 is a sectional view conceptually showing a compound semiconductor device according to Example 2. FIG.

Explanation of symbols

4 hexagonal 2 Si single crystal substrate 3 3C-SiC single crystal buffer layer crystal _{In w Ga x Al 1-wx} N single crystal buffer layer 5 hexagonal _{In y Ga z Al 1-yz} N single crystal layer 6 back electrode 7 surface electrode 9 c-BP single crystal buffer layer 10 Insulating layer 11 Upper electrode

Claims (8)

Crystal plane orientation {111}, carrier concentration 10 ¹⁶ to 10 ²¹ / cm ³ (≈resistivity 1 to 0.00001 Ωcm), conductive n-type Si single crystal substrate, thickness 0.05 to 2 μm, carrier concentration 10 ¹⁶ to 10 ²¹ / cm ³ , a conductivity type n-type 3C—SiC single crystal buffer layer, and a hexagonal In _w Ga _x Al _1-wx N single crystal buffer layer having a thickness of 0.01 to 0.5 μm (0 ≦ w <1, 0 ≦ x <1, w + x <1), thickness 0.1 to 5 μm, carrier concentration 10 ¹¹ to 10 ¹⁶ / cm ³ (≈resistivity 1 to 100000 Ωcm), conduction type n-type hexagon crystal _{in y Ga z Al 1-yz} N single crystal layer (0 ≦ y <1,0 <z ≦ 1, y + z ≦ 1) and are sequentially stacked, and a back electrode on the back surface of the Si single crystal substrate, and , that the surface electrode is formed on the hexagonal _{in y Ga z Al 1-yz} N surface of the single crystal layer A featured compound semiconductor device. Between the Si single crystal substrate and the 3C-SiC single crystal buffer layer, a thickness of 0.01 to 1 μm, a carrier concentration of 10 ¹⁶ to 10 ²¹ / cm ³ , a conductive n-type c-BP single crystal buffer layer is inserted. The compound semiconductor device according to claim 1, wherein the compound semiconductor device is formed. The hexagonal _{In w Ga x Al 1-wx} N single crystal buffer layer is hexagonal AlN (w = 0, x = 0), and the hexagonal _{In y Ga z Al 1-yz} N single crystal layer is hexagonal 3. The compound semiconductor device according to claim 1, wherein the compound semiconductor device is GaN (y = 0, z = 1). The back electrode and the front electrode are each formed of a metal containing at least one of Al, Ti, In, Au, Ni, Pt, W, and Pd, the back electrode is an ohmic junction, and the front electrode is a Schottky junction, and the 3C-SiC single crystal buffer layer, with hexagonal _{in w Ga x Al 1-wx} N single crystal buffer layer and the hexagonal _{in y Ga z Al 1-yz} N single crystal layer is an ohmic junction The compound semiconductor device according to claim 1, wherein the compound semiconductor device is provided. The back electrode and the front electrode are each formed of a metal containing at least one of Al, Ti, In, Au, Ni, Pt, W, and Pd, the back electrode is an ohmic junction, and the front electrode is an ohmic contact, and the 3C-SiC single crystal buffer layer, the hexagonal _{in w Ga x Al 1-wx} N single crystal buffer layer and the hexagonal _{in y Ga z Al 1-yz} N single crystal layer energy barrier The compound semiconductor device according to claim 1, wherein the compound semiconductor device has a heterojunction.   Two or more surface electrodes are formed, each formed of a metal including at least one of Al, Ti, In, Au, Ni, Pt, W, and Pd, and of these surface electrodes The compound semiconductor device according to claim 1, wherein at least one is an ohmic junction and the other is a Schottky junction.   The compound semiconductor device according to claim 1, wherein an insulating layer and an upper electrode are sequentially laminated on the surface electrode. The surface electrodes, the 3C-SiC single crystal buffer layer, an area ratio each of the hexagonal _{In w Ga x Al 1-wx} N single crystal buffer layer and the hexagonal _{In y Ga z Al 1-yz} N single crystal layer The compound semiconductor device according to claim 1, wherein the compound semiconductor device is 0.2 to 0.9.

Images