JP2014022698A - Si SUBSTRATE FOR NITRIDE SEMICONDUCTOR GROWTH, EPITAXIAL SUBSTRATE FOR ELECTRONIC DEVICE USING THE SAME AND MANUFACTURING METHODS OF THOSE - Google Patents
Si SUBSTRATE FOR NITRIDE SEMICONDUCTOR GROWTH, EPITAXIAL SUBSTRATE FOR ELECTRONIC DEVICE USING THE SAME AND MANUFACTURING METHODS OF THOSE Download PDFInfo
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本発明は、窒化物半導体、とくに、電子デバイス用エピタキシャル基板に用いるＳｉ基板およびその製造方法に関し、特に、横方向を電流導通方向とするHEMT用エピタキシャル基板およびその製造方法に関する。 The present invention relates to a nitride semiconductor, in particular, an Si substrate used for an electronic device epitaxial substrate and a method for manufacturing the same, and more particularly to an HEMT epitaxial substrate having a lateral direction as a current conduction direction and a method for manufacturing the same.
Ｓｉ基板上に、ＡｌＮなどのバッファ層を介して、ＧａＮなどのＩＩＩ族窒化物をエピタキシャル成長できることが知られている。このような技術を用いて、近年、ＩＩＩ族窒化物を用いた高電子移動度トランジスタ（HEMT: High electron mobility transistor)が実用化されようとしている。 It is known that a group III nitride such as GaN can be epitaxially grown on a Si substrate via a buffer layer such as AlN. In recent years, a high electron mobility transistor (HEMT) using a group III nitride has been put into practical use using such a technique.
特許文献１は、ＣＺ法でのＳｉ基板表面のＣＯＰ等のピットが無いことを特徴とするＧａＮ形成用のＳｉ基板を開示している。 Patent Document 1 discloses a Si substrate for forming GaN characterized by no pits such as COP on the surface of the Si substrate by the CZ method.
特許文献２は、比抵抗値が０．０１Ω・ｃｍ以下である低抵抗Ｓｉ基板を用いることで、反りを抑制した電子デバイス用エピタキシャル基板を開示している。 Patent Document 2 discloses an epitaxial substrate for electronic devices in which warpage is suppressed by using a low-resistance Si substrate having a specific resistance value of 0.01 Ω · cm or less.
特許文献１に記載のＣＺ法による低ＣＯＰ基板は、通常のＳｉ基板にくらべて入手が困難である。また、特許文献２に記載のボロン濃度が１０１９／ｃｍ３以上の低抵抗Ｓｉ基板においては、ピットが大量発生する場合があった。本発明者らは大気暴露に起因してボロンの表面変質が起きるためと考えた。本発明の目的は、高濃度のボロンを有するＳｉ基板であっても、エピ表面のピット欠陥を低減させ、さらに、裏面への不純物拡散抑制も可能なＳｉ基板を提供し、高品質の電子デバイス用エピタキシャル基板を提供することにある。 The low COP substrate by the CZ method described in Patent Document 1 is difficult to obtain compared to a normal Si substrate. In addition, in the low resistance Si substrate described in Patent Document 2 having a boron concentration of 10 19 / cm 3 or more, a large number of pits may be generated. The present inventors considered that the surface alteration of boron occurs due to atmospheric exposure. An object of the present invention is to provide a high-quality electronic device by providing a Si substrate capable of reducing pit defects on the epi surface and suppressing impurity diffusion to the back surface even for a Si substrate having a high concentration of boron. It is to provide an epitaxial substrate for use.
上記目的を達成するため、鋭意研究した結果、高濃度のボロンを有するＳｉ基板上にボロン濃度が小さいＳｉ単結晶層を別途形成することにより、ピットの大量発生リスクを大幅に抑えることができることを見出し、本発明を完成するに至った。
すなわち、Ｂ濃度が２×１０１８／ｃｍ３以上であるＳｉ単結晶基板と、Ｓｉ単結晶基板の主面上に形成されたＳｉ単結晶層を有し、Ｓｉ単結晶層の表面のＢ濃度がＳｉ単結晶基板のＢ濃度よりも小さいＩＩＩ族窒化物半導体成長用Ｓｉ単結晶基板である。
As a result of diligent research to achieve the above object, it is possible to significantly reduce the risk of pit mass formation by separately forming a Si single crystal layer having a low boron concentration on a Si substrate having a high concentration of boron. The headline and the present invention were completed.
That is, it has a Si single crystal substrate having a B concentration of 2 × 10 18 / cm 3 or more and a Si single crystal layer formed on the main surface of the Si single crystal substrate, and the B concentration on the surface of the Si single crystal layer Is a group III nitride semiconductor growth Si single crystal substrate having a B concentration lower than that of the Si single crystal substrate.
Ｓｉ単結晶層の表面のＢ濃度は０．１〜０．７×１０１８／ｃｍ３であることが好ましい。 The B concentration on the surface of the Si single crystal layer is preferably 0.1 to 0.7 × 10 18 / cm 3 .
Ｓｉ単結晶基板の抵抗値は
０．０３Ω・ｃｍ以下であり、Ｓｉ単結晶層の抵抗値がＳｉ単結晶基板の抵抗値より大きいことが好ましい。さらに、Ｓｉ単結晶層の表面の抵抗値が０．０５Ω・ｃｍより大きいことがより好ましい。
The resistance value of the Si single crystal substrate is 0.03 Ω · cm or less, and the resistance value of the Si single crystal layer is preferably larger than the resistance value of the Si single crystal substrate. Further, the resistance value of the surface of the Si single crystal layer is more preferably larger than 0.05 Ω · cm.
Ｓｉ単結晶基板の主面とは反対側の表面にＳｉ酸化物層を有していても良い。 A Si oxide layer may be provided on the surface opposite to the main surface of the Si single crystal substrate.
Ｂ濃度が２×１０１８／ｃｍ３以上であるSi単結晶基板と、Ｓｉ単結晶基板の主面上のＳｉ単結晶層を有し、Ｓｉ単結晶層の表面はＢを０．１〜０．７×１０１８／ｃｍ３含み、Ｓｉ単結晶層上に形成した絶縁層としてのバッファと、バッファ上に複数層のIII族窒化物層をエピタキシャル成長させて形成した主積層体とを具え、横方向を電流導通方向とする電子デバイス用エピタキシャル基板である。 It has a Si single crystal substrate having a B concentration of 2 × 10 18 / cm 3 or more, and a Si single crystal layer on the main surface of the Si single crystal substrate. .7 × 10 18 / cm 3 , comprising a buffer as an insulating layer formed on the Si single crystal layer, and a main laminate formed by epitaxially growing a plurality of Group III nitride layers on the buffer. It is the epitaxial substrate for electronic devices which makes a direction a current conduction direction.
Ｓｉ単結晶基板の主面とは反対側の表面にＳｉ酸化物層を有する電子デバイス用エピタキシャル基板であってもよい。 The epitaxial substrate for electronic devices which has a Si oxide layer in the surface on the opposite side to the main surface of Si single crystal substrate may be sufficient.
上記目的を達成するための本発明の製造方法は、すなわち、Ｂ濃度が２×１０１８/ｃｍ３以上であるＳｉ単結晶基板の主面上に気相成長によりＢ濃度がＳｉ単結晶基板より少ないＳｉ単結晶層を形成する工程を有する窒化物半導体成長用Ｓｉ単結晶基板の製造方法である。 The manufacturing method of the present invention for achieving the above object is that the B concentration is higher than that of the Si single crystal substrate by vapor phase growth on the main surface of the Si single crystal substrate having a B concentration of 2 × 10 18 / cm 3 or more. This is a method for producing a Si single crystal substrate for growing a nitride semiconductor, which includes a step of forming a few Si single crystal layers.
Ｓｉ単結晶層の表面のＢ濃度が０．１〜０．７×１０１８／ｃｍ３であることが好ましい。 The B concentration on the surface of the Si single crystal layer is preferably 0.1 to 0.7 × 10 18 / cm 3 .
Ｓｉ単結晶基板の抵抗値は
０．０３Ω・ｃｍ以下であり、Ｓｉ単結晶層の抵抗値が前記Si単結晶基板の抵抗値より大きいことが好ましい。さらには、Ｓｉ単結晶層の表面の抵抗値が０．０５Ω・ｃｍより大きいことがより好ましい。
The resistance value of the Si single crystal substrate is 0.03 Ω · cm or less, and the resistance value of the Si single crystal layer is preferably larger than the resistance value of the Si single crystal substrate. Further, the resistance value of the surface of the Si single crystal layer is more preferably larger than 0.05 Ω · cm.
Ｓｉ単結晶基板の主面とは反対側の表面にＳｉ酸化物層を有していても良い。 A Si oxide layer may be provided on the surface opposite to the main surface of the Si single crystal substrate.
Ｂ濃度が２×１０１８／ｃｍ３以上であるＳｉ単結晶基板の主面上に気相成長により表面のＢ濃度が０．１〜０．７×１０１８／ｃｍ３であるＳｉ単結晶層を形成する工程と、
該Ｓｉ単結晶層上に形成した絶縁層としてのバッファと、該バッファ上に複数層のIII族窒化物層をエピタキシャル成長させて形成した主積層体とを具え、横方向を電流導通方向とする電子デバイス用エピタキシャル基板の製造方法である。
A Si single crystal layer having a B concentration of 0.1 to 0.7 × 10 18 / cm 3 on the main surface of the Si single crystal substrate having a B concentration of 2 × 10 18 / cm 3 or more by vapor phase growth. Forming a step;
Electrons having a buffer as an insulating layer formed on the Si single crystal layer and a main laminate formed by epitaxially growing a plurality of Group III nitride layers on the buffer, with the horizontal direction being a current conduction direction It is a manufacturing method of the epitaxial substrate for devices.
Ｂ濃度が２×１０１８／ｃｍ３以上であるＳｉ単結晶基板の両面を酸化して酸化膜を形成する工程と、一方の面の酸化膜を保持して他方の面の酸化膜を除去する工程と、酸化膜を除去した面上に気相成長により表面のＢ濃度が０．１〜０．７×１０１８／ｃｍ３であるＳｉ単結晶層を形成する工程と、
該Ｓｉ単結晶層上に形成した絶縁層としてのバッファと、該バッファ上に複数層のIII族窒化物層をエピタキシャル成長させて形成した主積層体とを具え、横方向を電流導通方向とする電子デバイス用エピタキシャル基板の製造方法である。
A step of oxidizing both surfaces of the Si single crystal substrate having a B concentration of 2 × 10 18 / cm 3 or more to form an oxide film, and holding the oxide film on one surface and removing the oxide film on the other surface Forming a Si single crystal layer having a surface B concentration of 0.1 to 0.7 × 10 18 / cm 3 by vapor phase growth on the surface from which the oxide film has been removed;
Electrons having a buffer as an insulating layer formed on the Si single crystal layer and a main laminate formed by epitaxially growing a plurality of Group III nitride layers on the buffer, with the horizontal direction being a current conduction direction It is a manufacturing method of the epitaxial substrate for devices.
本発明の窒化物半導体成長用Ｓｉ単結晶基板および電子デバイス用エピタキシャル基板は、２×１０１８／ｃｍ３以上のＢ濃度を有するＳｉ単結晶基板の上に、より少ないＢ濃度を有するＳｉ単結晶層を具えることにより、Ｓｉ単結晶表面の局所的なＢの改質を抑制できると共に、その上に形成されるＩＩＩ族窒化物半導体層へのＢの拡散が抑制され、ピットの発生を抑制することができる。 The Si single crystal substrate for growing a nitride semiconductor and the epitaxial substrate for an electronic device according to the present invention have a Si single crystal having a lower B concentration on a Si single crystal substrate having a B concentration of 2 × 10 18 / cm 3 or more. By providing a layer, local modification of B on the surface of the Si single crystal can be suppressed, and diffusion of B into the group III nitride semiconductor layer formed thereon can be suppressed, thereby suppressing generation of pits. can do.
また、本発明の窒化物半導体成長用Ｓｉ単結晶基板の製造方法によれば、
Ｂ濃度が２×１０１８／ｃｍ３以上であるＳｉ単結晶基板の上に、Ｂをより少なく含むＳｉ単結晶層を、気相成長法（ＣＶＤ法、ＭＢＥ法など）を用いて形成することにより、
上記のようにＩＩＩ族窒化物半導体層とＳｉ単結晶との界面のＢの改質を抑制できると共に、その上に形成されるＩＩＩ族窒化物半導体層へのＢの拡散が抑制され、ピットの発生を抑制することができる基板を提供することができる。
Further, according to the method for manufacturing a nitride single crystal growth Si substrate of the present invention,
A Si single crystal layer containing less B is formed on a Si single crystal substrate having a B concentration of 2 × 10 18 / cm 3 or more by using a vapor phase growth method (CVD method, MBE method, etc.). By
As described above, the modification of B at the interface between the group III nitride semiconductor layer and the Si single crystal can be suppressed, and the diffusion of B to the group III nitride semiconductor layer formed thereon can be suppressed. A substrate capable of suppressing the generation can be provided.
次に、本発明の電子デバイス用エピタキシャル基板の実施形態について図面を参照しながら説明する。図２は、本発明に従う電子デバイス用エピタキシャル基板の断面構造を模式的に示したものである。なお、図２は、説明の便宜上、厚さ方向を誇張して描いたものである。 Next, an embodiment of the epitaxial substrate for electronic devices of the present invention will be described with reference to the drawings. FIG. 2 schematically shows a cross-sectional structure of an epitaxial substrate for an electronic device according to the present invention. Note that FIG. 2 shows the thickness direction exaggerated for convenience of explanation.
図２に示すように、本発明の電子デバイス用エピタキシャル基板１は、横方向を電流導通方向とする電子デバイス用エピタキシャル基板１であって、Ｂ濃度が２×１０１８／ｃｍ３以上であるSi単結晶基板２と、このＳi単結晶基板２の主面２ｂ上に形成したＳｉ単結晶層４とからなる窒化物半導体成長用Ｓｉ単結晶基板を有し、このＳｉ単結晶層４上に複数層のIII族窒化物層をエピタキシャル成長させて形成した、初期成長層６および超格子積層体７からなる絶縁層としてのバッファと、バッファ上の主積層体５とを具え、Ｓｉ単結晶層４のＢ濃度はＳｉ基板に比べ小さく、かかる構成を有することにより、ＨＥＭＴのピット密度を小さく抑制できるものである。さらに、Ｓi単結晶基板２の裏面２ａ上に形成した不純物拡散抑制層を具える構成も、好ましい構成である。 As shown in FIG. 2, the electronic device epitaxial substrate 1 of the present invention is an electronic device epitaxial substrate 1 in which the lateral direction is a current conduction direction, and a B concentration is 2 × 10 18 / cm 3 or more. There is a Si single crystal substrate for growing a nitride semiconductor comprising a single crystal substrate 2 and a Si single crystal layer 4 formed on the main surface 2b of the Si single crystal substrate 2. A plurality of Si single crystal substrates 4 are formed on the Si single crystal layer 4. And a buffer as an insulating layer formed by epitaxially growing a group III nitride layer, which is an initial growth layer 6 and a superlattice laminate 7, and a main laminate 5 on the buffer. The B concentration is smaller than that of the Si substrate, and by having such a configuration, the pit density of the HEMT can be suppressed to be small. Furthermore, a configuration including an impurity diffusion suppression layer formed on the back surface 2a of the Si single crystal substrate 2 is also a preferable configuration.
ここで、「横方向を電流導通方向とする」とは、図１で示したように、ソース電極２４からドレイン電極２５へ、主に積層体の幅方向に電流が流れることを意味し、例えば半導体を一対の電極で挟んだ構造のように、主に縦方向すなわち積層体の厚さ方向に電流が流れるものとは異なることを意味する。 Here, “the lateral direction is the current conduction direction” means that a current flows from the source electrode 24 to the drain electrode 25 mainly in the width direction of the stacked body as shown in FIG. This means that the current flows mainly in the longitudinal direction, that is, in the thickness direction of the stacked body, as in a structure in which a semiconductor is sandwiched between a pair of electrodes.
Si単結晶基板２の面方位は特に指定されず、(111),(100),(110)面等を使用することができるが、III族窒化物の(0001)面を表面平坦性よく成長させるためには、(111)面を使用することが望ましい。また、伝導型はｐ型であり、電気伝導性の高い低抵抗基板である。 The plane orientation of the Si single crystal substrate 2 is not particularly specified, and (111), (100), (110) planes, etc. can be used, but the (0001) plane of group III nitride is grown with good surface flatness. For this purpose, it is desirable to use the (111) plane. Further, the conductivity type is p-type, and it is a low-resistance substrate with high electrical conductivity.
基板のオフ角度については、０．２°以下であることが望ましい。通常Ｓｉ単結晶基板上にＳｉ単結晶層を成長させる場合、Ｓｉ単結晶層の表面に発生する表面欠陥であるヘイズを抑制するために、オフ角度を０．５℃以上とするのが通常である。しかし、本発明を検討する中で、オフ角度を０．２°より大きくすると、III族窒化物層にピットが多く発生すること、前記ヘイズはIII族窒化物層の表面には悪影響を与えないことが確認された結果としてIII族窒化物層成長用のより好ましい形態として想到された条件である。 The off angle of the substrate is preferably 0.2 ° or less. Usually, when a Si single crystal layer is grown on a Si single crystal substrate, the off angle is usually 0.5 ° C. or more in order to suppress haze, which is a surface defect generated on the surface of the Si single crystal layer. is there. However, when examining the present invention, when the off-angle is larger than 0.2 °, many pits are generated in the group III nitride layer, and the haze does not adversely affect the surface of the group III nitride layer. As a result, it has been conceived as a more preferable mode for growing a group III nitride layer.
Si単結晶基板２は、Ｂ濃度が２×１０１８／ｃｍ３以上（比抵抗が０．０３Ω・ｃｍ以下）である。より好ましくは３×１０１８／ｃｍ３以上（比抵抗が０．０２Ω・ｃｍ以下）、さらに好ましくは９×１０１８／ｃｍ３以上（比抵抗が０．０１Ω・ｃｍ以下）である。Ｂ濃度が大きいことにより、比抵抗が小さくなると共に、特開２０１０−１５３８１７に記載のように、基板の硬度が向上し、基板の反りに対する耐性が増すことになる。 The Si single crystal substrate 2 has a B concentration of 2 × 10 18 / cm 3 or more (specific resistance is 0.03 Ω · cm or less). More preferably, it is 3 × 10 18 / cm 3 or more (specific resistance is 0.02 Ω · cm or less), and further preferably 9 × 10 18 / cm 3 or more (specific resistance is 0.01 Ω · cm or less). When the B concentration is large, the specific resistance is reduced, and as described in JP 2010-153817 A, the hardness of the substrate is improved and the resistance to warpage of the substrate is increased.
Ｓｉ単結晶層４は、表面のＢ濃度がＳｉ単結晶基板より小さく、好ましくは２×１０１８／ｃｍ３未満である。なお、本発明のＳｉ単結晶層４のＢ濃度の値は、Ｓｉ基板の主面と対向するＩＩＩ族窒化物を成長させる予定面である表面の値とする。Ｓｉ単結晶層４のＳｉ基板の主面側においてはＳｉ基板からのＢ拡散の影響があるためである。Ｓｉ単結晶層４はＭＯＣＶＤ法を用いて製造することができ、その厚さは例えば１〜３μｍである。Ｓｉ単結晶層４の表面のＢ濃度は０．１〜０．７×１０１８／ｃｍ３であることがより好ましい。２×１０１８／ｃｍ３未満とすることで、大気中に放置した場合でも、Ｂの酸化が原因と考えられるＩＩＩ族窒化物半導体層でのピットの大量発生が起きる恐れがなくなり、さらに、０．７×１０１８／ｃｍ３以下とすることで、ピット密度を１／ｃｍ２以下に抑制することができる。なお、０．１×１０１８／ｃｍ３未満とした場合には、その上に形成するＩＩＩ族窒化物半導体層との間のミスフィット転位が発生しやすくなるため好ましくない。
なお、ここでいうピットは、電子供給層5ｂの表面における開口面積が０．２５μｍ２以上のものをいう。
The Si single crystal layer 4 has a surface B concentration lower than that of the Si single crystal substrate, preferably less than 2 × 10 18 / cm 3 . Note that the value of the B concentration of the Si single crystal layer 4 of the present invention is the value of the surface that is the surface on which the group III nitride facing the main surface of the Si substrate is to be grown. This is because the Si single crystal layer 4 has an influence of B diffusion from the Si substrate on the main surface side of the Si substrate. The Si single crystal layer 4 can be manufactured using the MOCVD method, and the thickness thereof is, for example, 1 to 3 μm. The B concentration on the surface of the Si single crystal layer 4 is more preferably 0.1 to 0.7 × 10 18 / cm 3 . By setting it to less than 2 × 10 18 / cm 3 , there is no possibility that a large amount of pits are generated in the group III nitride semiconductor layer considered to be caused by oxidation of B even when left in the atmosphere. By setting it to 0.7 × 10 18 / cm 3 or less, the pit density can be suppressed to 1 / cm 2 or less. In addition, when it is less than 0.1 × 10 18 / cm 3, misfit dislocation between the group III nitride semiconductor layer formed thereon is likely to occur, which is not preferable.
Here, the pits herein mean those having an opening area of 0.25 μm 2 or more on the surface of the electron supply layer 5b.
Ｓｉ単結晶層４は、表面の抵抗値が０．０５Ω・ｃｍより大きいことが好ましい。０．０５Ω・ｃｍより大きいことにより、その上に形成するＩＩＩ族窒化物半導体層のピット密度を１／ｃｍ２以下に抑制することができる。Ｓｉ単結晶層４の厚さとしては１〜３μｍが好ましい。 The Si single crystal layer 4 preferably has a surface resistance value larger than 0.05 Ω · cm. By being larger than 0.05 Ω · cm, the pit density of the group III nitride semiconductor layer formed thereon can be suppressed to 1 / cm 2 or less. The thickness of the Si single crystal layer 4 is preferably 1 to 3 μm.
Ｓｉ単結晶層４と主積層体５との間に形成されるバッファは、超格子構造または傾斜組成構造を有するのが好ましい。超格子構造とは、図２に示すように、第１層７ａと第２層７ｂを周期的に含むように積層することを意味する。第１層７ａと第２層７ｂ以外の層(たとえば組成遷移層)を含むことは可能である。また、傾斜組成構造とは、特定のIII族元素含有量を膜厚方向に傾斜させることを意味する。 The buffer formed between the Si single crystal layer 4 and the main laminate 5 preferably has a superlattice structure or a graded composition structure. As shown in FIG. 2, the superlattice structure means that the first layer 7a and the second layer 7b are periodically stacked so as to include them. It is possible to include a layer (for example, a composition transition layer) other than the first layer 7a and the second layer 7b. Further, the gradient composition structure means that a specific group III element content is inclined in the film thickness direction.
また、バッファは、図２に示すように、Si単結晶層４と接する初期成長層６および初期成長層６上の超格子積層構造からなる超格子積層体７を有するのが好ましい。初期成長層６は例えばAlN材料からなることができ、初期成長層６をAlNで形成することにより、Si単結晶基板２との反応を抑制し、縦方向耐圧の向上を可能とする。 Further, as shown in FIG. 2, the buffer preferably has an initial growth layer 6 in contact with the Si single crystal layer 4 and a superlattice laminate 7 having a superlattice laminate structure on the initial growth layer 6. The initial growth layer 6 can be made of, for example, an AlN material. By forming the initial growth layer 6 with AlN, the reaction with the Si single crystal substrate 2 is suppressed, and the vertical breakdown voltage can be improved.
Ｓi単結晶基板２の裏面２ａ上に形成する不純物拡散抑制層としては、例えばSiの酸化物、窒化物または炭化物等が挙げられ、その厚さは０．１μｍ〜１０μｍであるのが好ましい。 Examples of the impurity diffusion suppression layer formed on the back surface 2a of the Si single crystal substrate 2 include Si oxide, nitride, and carbide, and the thickness is preferably 0.1 μm to 10 μm.
電子デバイス用エピタキシャル基板１は、HEMTに用いるのが好ましい。図２に示すエピタキシャル基板１の主積層体５は、Ba1Alb1Gac1Ind1N(0≦a1≦1, 0≦b1≦1, 0≦c1≦1, 0≦d1≦1, a1+b1+c1+d1=1)材料からなるチャネル層５ａおよびチャネル層５ａよりバンド
ギャップの大きいBa2Alb2Gac2Ind2N(0≦a2≦1, 0≦b2≦1, 0≦c2≦1, 0≦d2≦1, a2+b2+c2+d2=1)材料からなる電子供給層５ｂを有することができる。この際、両層とも単一もしくは複数の組成から構成することができる。特に、合金散乱をさけ、電流導通部分の比抵抗を下げるためには、チャネル層５ａの少なくとも電子供給層５ｂと接する部分はGaN材料とすることが好ましい。
The epitaxial substrate 1 for electronic devices is preferably used for HEMT. The main laminated body 5 of the epitaxial substrate 1 shown in FIG. 2 has B a1 Al b1 Ga c1 In d1 N (0 ≦ a1 ≦ 1, 0 ≦ b1 ≦ 1, 0 ≦ c1 ≦ 1, 0 ≦ d1 ≦ 1, a1 + b1 + c1 + d1 = 1) channel layer 5a made of a material and B a2 Al b2 Ga c2 In d2 N (0 ≦ a2 ≦ 1, 0 ≦ b2 ≦ 1, 0 ≦ c2 ≦ 1 having a larger band gap than the channel layer 5a , 0 ≦ d2 ≦ 1, a2 + b2 + c2 + d2 = 1) The electron supply layer 5b made of a material can be provided. At this time, both layers can be composed of a single composition or a plurality of compositions. In particular, in order to avoid alloy scattering and to lower the specific resistance of the current conducting portion, it is preferable that at least a portion of the channel layer 5a in contact with the electron supply layer 5b is made of a GaN material.
次に、本発明の電子デバイス用エピタキシャル基板の製造方法の実施形態について図面を参照しながら説明する。 Next, an embodiment of a method for producing an epitaxial substrate for an electronic device according to the present invention will be described with reference to the drawings.
図２に示すように、Si単結晶基板２の主面２ｂ上に、Ｓｉ単結晶層４を形成した窒化物半導体成長用Ｓｉ単結晶基板を得る工程と、このＳｉ単結晶層４上に、複数層のIII族窒化物層をエピタキシャル成長させて初期成長層６および超格子積層体７からなる絶縁層としてのバッファと、バッファ上の主積層体５を形成してエピタキシャル基板を作製する工程とを具えることを特徴とし、かかる工程を有することにより、ＨＥＭＴのピット密度を小さく抑制できるエピタキシャル基板を製造できる。さらに、あらかじめＳi単結晶基板２の裏面２ａ上に不純物拡散抑制層３を形成する工程を有する場合も、好ましい工程である。 As shown in FIG. 2, a step of obtaining a Si single crystal substrate for growing a nitride semiconductor having a Si single crystal layer 4 formed on the main surface 2b of the Si single crystal substrate 2; A step of epitaxially growing a plurality of group III nitride layers to form an epitaxial substrate by forming a buffer as an insulating layer composed of an initial growth layer 6 and a superlattice laminate 7, and forming a main laminate 5 on the buffer; By providing such a process, an epitaxial substrate that can suppress the HEMT pit density can be manufactured. Furthermore, it is a preferable process to have a step of forming the impurity diffusion suppression layer 3 on the back surface 2a of the Si single crystal substrate 2 in advance.
また、主積層体５を形成する工程の後、不純物拡散抑制層３およびSi単結晶基板２の少なくとも一部を除去する工程と、主積層体５上に電極を形成する工程とをさらに具えることができる。 Further, after the step of forming the main laminate 5, a step of removing at least a part of the impurity diffusion suppression layer 3 and the Si single crystal substrate 2 and a step of forming an electrode on the main laminate 5 are further provided. be able to.
不純物拡散抑制層３は、公知の方法、例えば裏面２ａに貼り付ける、裏面２ａ上にＣＶＤ法、スパッタ法等により蒸着させる、熱酸化により形成するといった方法により形成することができる。不純物拡散抑制層３がＳｉ酸化物の場合は、より好ましくは、高抵抗で、かつ緻密でエッチング耐性の高い層を形成することができる熱酸化によって形成されるのが好ましい。基板の全面に不純物拡散抑制層３を形成した後に、主面上の不純物拡散抑制層３を除去する工程を有しても良い。 The impurity diffusion suppression layer 3 can be formed by a known method, for example, a method of attaching to the back surface 2a, depositing the back surface 2a by a CVD method, a sputtering method, or the like, or forming by thermal oxidation. When the impurity diffusion suppression layer 3 is a Si oxide, it is more preferable that the impurity diffusion suppression layer 3 is formed by thermal oxidation that can form a high-resistance, dense, and etching-resistant layer. After the impurity diffusion suppression layer 3 is formed on the entire surface of the substrate, a step of removing the impurity diffusion suppression layer 3 on the main surface may be included.
主面２ｂ側に形成される層は、化学気相成長法を用いてエピタキシャル成長させることにより形成されるのが好ましい。成長方法としてはMOCVD法を用い、Ｓｉ単結晶の成長にはシランガスを用い、III族窒化物半導体の成長にはIII族原料としては、TMA(トリメチルアルミニウム)・TMG(トリメチルガリウム)等、Ｖ族原料としてはアンモニア等を用い、キャリアガスとして、水素および窒素ガス等を用いることができる。Ｂなどの不純物の濃度は、SIMSを用いて測定することができる。 The layer formed on the main surface 2b side is preferably formed by epitaxial growth using a chemical vapor deposition method. The growth method is MOCVD, silane gas is used for the growth of the Si single crystal, and the Group III material is used for the growth of the Group III nitride semiconductor, such as TMA (trimethylaluminum), TMG (trimethylgallium), etc. Ammonia or the like can be used as a raw material, and hydrogen, nitrogen gas, or the like can be used as a carrier gas. The concentration of impurities such as B can be measured using SIMS.
なお、図１および図２は、代表的な実施形態の例を示したものであって、本発明はこれらの実施形態に限定されるものではない。たとえば、各層の間に本発明の効果に悪影響を与えない程度の中間層を挿入したり、他の超格子層を挿入したり、組成に傾斜をつけたりすることも可能である。 1 and 2 show examples of typical embodiments, and the present invention is not limited to these embodiments. For example, an intermediate layer that does not adversely affect the effects of the present invention can be inserted between the layers, another superlattice layer can be inserted, or the composition can be graded.
（実施例１）
図２に示すように (111)面（オフ角度0.08°）６インチＳｉ単結晶基板２(厚さ：６００μｍ、比抵抗：０．０１５Ω・ｃｍ、Ｂ濃度：４×１０１８／ｃｍ３)の表面２ｂ（主面）上に、シランガスを用いてＭＯＣＶＤ法（成長温度１１５０℃）によりＳｉ単結晶層４（厚さ：２μｍ、比抵抗：０．０１５Ω・ｃｍ、Ｓｉ単結晶層４表面のＢ濃度：０．５×１０１８／ｃｍ３）を形成した。その後、初期成長層６(ＡｌＮ材料、厚さ:１００ｎｍ)および超格子積層体７(ＡｌＮ（厚さ:４ｎｍ）とＡｌ０．１５Ｇａ０．８５Ｎ（厚さ:２５ｎｍ）のペアを合計７５層)を成長させてバッファ４を形成し、この超格子積層体７上にチャネル層５ａ（ＧａＮ材料、厚さ:０．７５μｍ）および電子供給層５ｂ(Ａｌ0.15Ｇａ0.85Ｎ材料、厚さ：４０ｎｍ)をエピタキシャル成長させてＨＥＭＴ構造の主積層体５を形成し、試料を得た。
表面欠陥観察装置（ＣＳ−２０）を用いて電子供給層５ｂ表面のピット密度を測定したところ、ウエハ上の測定点１０箇所のピット密度は０．５〜１．０／ｃｍ２であり、ウエハ１枚あたりの平均は０．８／ｃｍ２であった。
Example 1
As shown in FIG. 2, a (111) plane (off angle 0.08 °) 6 inch Si single crystal substrate 2 (thickness: 600 μm, specific resistance: 0.015 Ω · cm, B concentration: 4 × 10 18 / cm 3 ) On the surface 2b (main surface), a Si single crystal layer 4 (thickness: 2 μm, specific resistance: 0.015 Ω · cm, B on the surface of the Si single crystal layer 4 is formed by MOCVD (growth temperature 1150 ° C.) using silane gas. Concentration: 0.5 × 10 18 / cm 3 ) was formed. Thereafter, a total of 75 pairs of the initial growth layer 6 (AlN material, thickness: 100 nm) and the superlattice laminate 7 (AlN (thickness: 4 nm) and Al 0.15 Ga 0.85 N (thickness: 25 nm) are combined. The layer 4 is grown to form the buffer 4, and the channel layer 5 a (GaN material, thickness: 0.75 μm) and the electron supply layer 5 b (Al 0.15 Ga 0.85 N material, thickness: on the superlattice laminate 7: 40 nm) is epitaxially grown to form a main laminate 5 having a HEMT structure, and a sample is obtained.
When the pit density on the surface of the electron supply layer 5b was measured using a surface defect observation apparatus (CS-20), the pit density at 10 measurement points on the wafer was 0.5 to 1.0 / cm 2. The average per sheet was 0.8 / cm 2 .
（実施例２）
Ｓｉ単結晶基板２として比抵抗が０．００８Ω・ｃｍ、Ｂ濃度が１×１０１９／ｃｍ３の基板を使用した以外は、実施例１と同様の構造を同条件にて形成し、試料を得た。
電子供給層５ｂ表面のピット密度を測定したところ、ウエハ上の測定点１０箇所のピット密度は０．５〜１．０／ｃｍ２であり、ウエハ１枚あたりの平均は０．８／ｃｍ２であった。
(Example 2)
A structure similar to that of Example 1 was formed under the same conditions except that a substrate having a specific resistance of 0.008 Ω · cm and a B concentration of 1 × 10 19 / cm 3 was used as the Si single crystal substrate 2. Obtained.
When the pit density on the surface of the electron supply layer 5b was measured, the pit density at 10 measurement points on the wafer was 0.5 to 1.0 / cm 2 , and the average per wafer was 0.8 / cm 2. Met.
（比較例１）
Ｓｉ単結晶層４を形成しなかった以外は、実施例１と同様の構造を同条件にて形成し、試料を得た。
電子供給層５ｂ表面のピット密度を測定したところ、ウエハ上の測定点１０箇所のピット密度は２.０〜５.０／ｃｍ２であり、ウエハ１枚あたりの平均は３．０／ｃｍ２であった。
(Comparative Example 1)
A sample was obtained by forming the same structure as in Example 1 under the same conditions except that the Si single crystal layer 4 was not formed.
When the pit density on the surface of the electron supply layer 5b was measured, the pit density at 10 measurement points on the wafer was 2.0 to 5.0 / cm 2 , and the average per wafer was 3.0 / cm 2. Met.
（比較例２）
Ｓｉ単結晶層４を形成しなかった以外は、実施例２と同様の構造を同条件にて形成し、試料を得た。
電子供給層５ｂ表面のピット密度を測定したところ、ウエハ上の測定点１０箇所のピット密度は２.０〜１００／ｃｍ２であり、ウエハに局所的なピットの大量発生が生じていた。
(Comparative Example 2)
A sample was obtained by forming the same structure as in Example 2 under the same conditions except that the Si single crystal layer 4 was not formed.
When the pit density on the surface of the electron supply layer 5b was measured, the pit density at 10 measurement points on the wafer was 2.0 to 100 / cm 2 , and a large number of local pits were generated on the wafer.
（実施例３）
実施例１のＳｉ単結晶基板２を、熱酸化することにより基板の両面にＳｉ酸化物層を形成後、主面と反対側の裏面２ａにレジストを塗布し、ＢＨＦ溶液により主面２ｂのＳｉ酸化物層を除去した。その後、アセトンを用いてレジストを除去することにより、裏面２ａにＳｉ酸化物層３(厚さ:０．３μｍ)を有するＳｉ基板を形成した。その後、主面２ｂ上に、シランガスを用いたＭＯＣＶＤ法により実施例１と同様のＳｉ単結晶層を形成した。
その後、実施例１と同様にして主面上のＨＥＭＴ構造の主積層体５を形成し、試料を得た。
表面欠陥観察装置（CS-20）を用いて電子供給層５ｂ表面のピット密度を測定したところ、ピット密度はウエハ１枚（測定点１０箇所）あたりの平均で０．９／ｃｍ２であった。
(Example 3)
The Si single crystal substrate 2 of Example 1 is thermally oxidized to form Si oxide layers on both surfaces of the substrate, and then a resist is applied to the back surface 2a opposite to the main surface, and the Si surface of the main surface 2b is coated with a BHF solution. The oxide layer was removed. Thereafter, the resist was removed using acetone to form a Si substrate having a Si oxide layer 3 (thickness: 0.3 μm) on the back surface 2a. Thereafter, a Si single crystal layer similar to that in Example 1 was formed on the main surface 2b by MOCVD using silane gas.
Then, the main laminated body 5 of the HEMT structure on a main surface was formed like Example 1, and the sample was obtained.
When the pit density on the surface of the electron supply layer 5b was measured using a surface defect observation apparatus (CS-20), the pit density was 0.9 / cm 2 on average per one wafer (10 measurement points). .
本発明によれば、Ｂ濃度が高いＳｉ単結晶基板を用いても、ピットの発生を抑制することができる電子デバイス用エピタキシャル基板を提供することができる。 ADVANTAGE OF THE INVENTION According to this invention, even if it uses Si single crystal substrate with high B density | concentration, the epitaxial substrate for electronic devices which can suppress generation | occurrence | production of a pit can be provided.
また、本発明の電子デバイス用エピタキシャル基板の製造方法によれば、Ｂ濃度が高いＳｉ単結晶基板であっても、ピット密度が小さい電子デバイス用エピタキシャル基板を製造することができる。 Further, according to the method for manufacturing an epitaxial substrate for electronic devices of the present invention, an epitaxial substrate for electronic devices having a low pit density can be manufactured even with a Si single crystal substrate having a high B concentration.
１ 電子デバイス用エピタキシャル基板
２ Ｓｉ単結晶基板
２ａ 裏面
２ｂ 主面
３ 不純物拡散抑制層
４ Ｓｉ単結晶層
５ 主積層体
５ａ チャネル層
５ｂ 電子供給層
６ 初期成長層
７ 超格子積層体
７ａ 第１層
７ｂ 第２層
DESCRIPTION OF SYMBOLS 1 Epitaxial substrate for electronic devices 2 Si single crystal substrate 2a Back surface 2b Main surface 3 Impurity diffusion suppression layer 4 Si single crystal layer 5 Main laminate 5a Channel layer 5b Electron supply layer 6 Initial growth layer 7 Superlattice laminate 7a First layer 7b 2nd layer
Claims (14)
０．０３Ωｃｍ以下であるSi単結晶基板と、前記Ｓｉ単結晶基板の主面上に形成されたＳｉ単結晶層を有し、前記Ｓｉ単結晶層の抵抗値が前記Ｓｉ単結晶基板の抵抗値より大きいＩＩＩ族窒化物半導体成長用Ｓｉ単結晶基板。 A Si single crystal substrate having a resistance value of 0.03 Ωcm or less, and a Si single crystal layer formed on a main surface of the Si single crystal substrate, wherein the Si single crystal layer has a resistance value of the Si single crystal substrate Si single crystal substrate for group III nitride semiconductor growth larger than resistance value of.
０．０３Ωｃｍ以下であるＳｉ単結晶基板の主面上に、気相成長により抵抗値が前記Si単結晶基板の抵抗値より大きいＳｉ単結晶層を形成する工程を有する窒化物半導体成長用Ｓｉ単結晶基板の製造方法。 Nitride semiconductor growth having a step of forming a Si single crystal layer having a resistance value larger than the resistance value of the Si single crystal substrate by vapor phase growth on the main surface of the Si single crystal substrate having a resistance value of 0.03 Ωcm or less Method for manufacturing Si single crystal substrate.
前記Ｓｉ単結晶層上に複数層のIII族窒化物層をエピタキシャル成長させて形成した、絶縁層としてのバッファと、前記バッファ上に主積層体とを具え、横方向を電流導通方向とする電子デバイス用エピタキシャル基板の製造方法。 A Si single crystal layer having a B concentration of 0.1 to 0.7 × 10 18 / cm 3 on the main surface of the Si single crystal substrate having a B concentration of 2 × 10 18 / cm 3 or more by vapor phase growth. Forming a step;
An electronic device comprising a buffer as an insulating layer formed by epitaxially growing a plurality of group III nitride layers on the Si single crystal layer, and a main laminate on the buffer, wherein the lateral direction is a current conduction direction Of manufacturing an epitaxial substrate for use.
前記Ｓｉ単結晶層上に複数層のIII族窒化物層をエピタキシャル成長させて形成した、絶縁層としてのバッファと、前記バッファ上の主積層体とを具え、横方向を電流導通方向とする電子デバイス用エピタキシャル基板の製造方法。 A step of thermally oxidizing both surfaces of a Si single crystal substrate having a B concentration of 2 × 10 18 / cm 3 or more to form an oxide film, and an oxidation of the main surface opposite to the back surface while holding the back surface oxide film A step of removing the film, a step of forming a Si single crystal layer having a surface B concentration of 0.1 to 0.7 × 10 18 / cm 3 by vapor phase growth on the main surface from which the oxide film has been removed,
An electronic device comprising a buffer as an insulating layer formed by epitaxially growing a plurality of group III nitride layers on the Si single crystal layer, and a main laminate on the buffer, the lateral direction being a current conduction direction Of manufacturing an epitaxial substrate for use.
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| JP (1) | JP2014022698A (en) |
Cited By (4)
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| JP2014236093A (en) * | 2013-05-31 | 2014-12-15 | サンケン電気株式会社 | Silicon-based substrate, semiconductor device and method for manufacturing semiconductor device |
| JP2015002329A (en) * | 2013-06-18 | 2015-01-05 | シャープ株式会社 | Epitaxial wafer, method for manufacturing the same, and nitride semiconductor device |
| WO2016088348A1 (en) * | 2014-12-04 | 2016-06-09 | Ｄｏｗａエレクトロニクス株式会社 | Iii nitride semiconductor epitaxial substrate and method for manufacturing the same |
| WO2019151441A1 (en) * | 2018-02-01 | 2019-08-08 | 住友化学株式会社 | Semiconductor wafer and method for producing same |
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| JPH1140506A (en) * | 1997-07-18 | 1999-02-12 | Shin Etsu Handotai Co Ltd | Manufacture of epitaxial wafer |
| JP2010153817A (en) * | 2008-11-27 | 2010-07-08 | Dowa Electronics Materials Co Ltd | Epitaxial substrate for electronic device and method of manufacturing the same |
| JP2011023664A (en) * | 2009-07-17 | 2011-02-03 | Dowa Electronics Materials Co Ltd | Epitaxial substrate for electronic device using transverse direction as direction of current conduction and manufacturing method therefor |
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| JPH1140506A (en) * | 1997-07-18 | 1999-02-12 | Shin Etsu Handotai Co Ltd | Manufacture of epitaxial wafer |
| JP2010153817A (en) * | 2008-11-27 | 2010-07-08 | Dowa Electronics Materials Co Ltd | Epitaxial substrate for electronic device and method of manufacturing the same |
| JP2011023664A (en) * | 2009-07-17 | 2011-02-03 | Dowa Electronics Materials Co Ltd | Epitaxial substrate for electronic device using transverse direction as direction of current conduction and manufacturing method therefor |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014236093A (en) * | 2013-05-31 | 2014-12-15 | サンケン電気株式会社 | Silicon-based substrate, semiconductor device and method for manufacturing semiconductor device |
| JP2015002329A (en) * | 2013-06-18 | 2015-01-05 | シャープ株式会社 | Epitaxial wafer, method for manufacturing the same, and nitride semiconductor device |
| WO2016088348A1 (en) * | 2014-12-04 | 2016-06-09 | Ｄｏｗａエレクトロニクス株式会社 | Iii nitride semiconductor epitaxial substrate and method for manufacturing the same |
| JP2016111138A (en) * | 2014-12-04 | 2016-06-20 | Ｄｏｗａエレクトロニクス株式会社 | Group iii nitride semiconductor epitaxial substrate and manufacturing method of the same |
| WO2019151441A1 (en) * | 2018-02-01 | 2019-08-08 | 住友化学株式会社 | Semiconductor wafer and method for producing same |
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