JP2014241387A - Substrate, method of manufacturing the same, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate having a graphene layer with an excellent film quality, and to provide a method of manufacturing the same and to provide an electronic equipment.SOLUTION: The substrate includes: a nitride semiconductor layer 12 provided on a top surface of a silicon substrate 10 of which the top surface is (111) plane; a silicon carbide layer 14 provided on the top surface of the nitride semiconductor layer 12; and a graphene layer 16 provided on a top surface of the silicon carbide layer 14. A graphene layer with an excellent film quality, for instance, such as, a D/G value of 1.1 or less, may be obtained.

Description

  The present invention relates to a substrate, a method for manufacturing the substrate, and an electronic device, for example, a substrate having a graphene layer, a method for manufacturing the substrate, and an electronic device.

  In recent years, research on graphene, which is a nanocarbon material obtained by extending a hexagonal skeleton formed by carbon atoms into a sheet shape, has been made in various fields. For example, since graphene has a feature of high carrier mobility, a transistor using graphene as a channel has been studied.

  Various methods for producing graphene have been proposed. For example, a method of forming a graphene layer on a silicon carbide substrate using a silicon carbide substrate has been proposed. However, this method has a problem that the silicon carbide substrate is expensive and it is difficult to increase the diameter of the substrate. Therefore, a method has been proposed in which a silicon carbide layer is formed on a silicon substrate that is inexpensive and easy to increase in diameter, and a graphene layer is formed on the silicon carbide layer.

  For example, a method has been proposed in which an aluminum nitride layer and a silicon carbide layer are sequentially formed on a (100) surface of a silicon substrate, and a graphene layer is formed on the silicon carbide layer (see, for example, Non-Patent Document 1). Research has also been conducted on a structure in which an aluminum nitride layer and a silicon carbide layer are formed on the (100) surface of a silicon substrate (see, for example, Non-Patent Document 2).

Benjamin Hsia, 5 others, “Epitaxial Graphene Growth on 3C-SIC (111) / AlN (0001) / Si (100)”, Electrochemical and Solid-State Letters, 2011, 14, p. K13-K15 Wei-Cheng Lien, 5 others, “Growth of 3C-SiC Thin Film on AlN / Si (100) with Atomically Abrupt Interface via Tailored Precursor Feeding Procedure”, Electrochemical and Solid-State Letters, 2010, 13, p. D53-D56

  However, the method of forming a graphene layer using a silicon carbide layer formed on the (100) surface of a silicon substrate leaves room for improvement in terms of the film quality of the graphene layer.

  The present invention has been made in view of the above problems, and an object thereof is to provide a substrate having a graphene layer with good film quality, a method for manufacturing the substrate, and an electronic device.

  The present invention provides a nitride semiconductor layer provided on the upper surface of a silicon substrate having a (111) plane as an upper surface, a silicon carbide layer provided on the upper surface of the nitride semiconductor layer, and an upper surface of the silicon carbide layer. And a provided graphene layer. According to the present invention, a graphene layer with good film quality can be obtained.

  In the above structure, the intensity ratio (D / G) of the D band to the G band in the Raman spectroscopy for the graphene layer may be 1.1 or less.

  In the above configuration, the nitride semiconductor layer may be an aluminum nitride layer.

  In the above structure, the aluminum nitride layer may have a thickness of 100 nm to 700 nm.

  In the above structure, the silicon carbide layer may be a cubic silicon carbide layer.

  The present invention includes a step of forming a nitride semiconductor layer on the upper surface of a silicon substrate having a (111) plane as an upper surface, a step of forming a silicon carbide layer on the upper surface of the nitride semiconductor layer, and the silicon carbide. And a step of forming a graphene layer on the upper surface of the layer. According to the present invention, a good quality graphene layer can be obtained.

  In the above structure, the graphene layer can be formed by performing heat treatment on the upper surface of the silicon carbide layer.

  In the above configuration, the nitride semiconductor layer may be an aluminum nitride layer.

  The present invention is an electronic device comprising any of the above-described substrates.

  In the above structure, a structure including a gate electrode provided on the graphene layer and a source electrode and a drain electrode provided with the gate electrode interposed therebetween, and a channel is formed in the graphene layer under the gate electrode It can be.

  According to the present invention, a graphene layer with good film quality can be obtained.

FIG. 1 is a cross-sectional view illustrating the substrate according to the first embodiment. FIG. 2 is a diagram illustrating the relationship between the film thickness of the AlN layer and the full width at half maximum. FIG. 3 is a diagram showing the relationship between the growth temperature of the SiC layer and the full width at half maximum. FIG. 4 is a diagram showing the relationship between the growth temperature and the growth rate of the SiC layer. FIG. 5A is a measurement result of Raman spectroscopy for the graphene layer provided on the substrate of Example 1, and FIG. 5B is a measurement result of Raman spectroscopy for the graphene layer provided on the substrate of Comparative Example 1. is there. FIG. 6 is a cross-sectional view illustrating the electronic apparatus according to the second embodiment. FIG. 7 shows the experimental results of evaluating the insulating properties of the AlN layer. FIG. 8 shows a simulation result of calculating a current flowing from the SiC layer to the Si substrate.

  Hereinafter, modes for carrying out the present invention will be described.

  FIG. 1 is a cross-sectional view illustrating the substrate according to the first embodiment. As shown in FIG. 1, the substrate 100 of Example 1 has a structure in which a nitride semiconductor layer 12, a silicon carbide (SiC) layer 14, and a graphene layer 16 are stacked in this order on a silicon (Si) substrate 10. ing. The upper surface of the Si substrate 10 is a (111) plane. The nitride semiconductor layer 12 is provided in contact with the upper surface of the Si substrate 10 by crystal growth on the upper surface of the Si substrate 10. The nitride semiconductor layer 12 is a nitride semiconductor layer having a hexagonal crystal structure, for example, and has a (0001) plane (c plane) as a crystal growth plane. That is, the (0001) plane of the nitride semiconductor layer 12 exists on the (111) plane that is the upper surface of the Si substrate 10. The nitride semiconductor layer 12 is preferably an aluminum nitride (4H—AlN) layer having a hexagonal crystal structure, for example.

  The SiC layer 14 is provided in contact with the upper surface of the nitride semiconductor layer 12 by crystal growth on the upper surface of the nitride semiconductor layer 12. The SiC layer 14 is a cubic silicon carbide (3C—SiC) layer, for example, and has a (111) plane as a crystal growth surface. That is, the (111) plane of the SiC layer 14 exists on the (0001) plane that is the upper surface of the nitride semiconductor layer 12.

The graphene layer 16 is provided in contact with the upper surface of the SiC layer 14. The graphene layer 16 has a structure in which six-membered rings of carbon atoms are connected, and a sheet having such a structure is provided by being laminated in one layer or several layers. Graphene layer 16, the intensity ratio of D band relative to G band in Raman spectroscopy (D / G), i.e. the value of the ratio of the peak intensity D of around 1350 cm ^-1 to the peak intensity G in the vicinity of 1590 cm ^-1 is 1.1 or less It has become. Details of this point will be described later.

Here, an experiment in which a preferable film thickness of the nitride semiconductor layer 12 is examined in the case where the nitride semiconductor layer 12 is an AlN layer will be described. In the experiment, an AlN layer having a hexagonal crystal structure was formed on the (111) surface, which is the upper surface of the Si substrate, using a metal-organic vapor phase epitaxy (MOVPE) method under the following conditions. A plurality of substrates on which crystals were grown were used. The size of the Si substrate is 4 inches.
Source gas: trimethylaluminum (TMA), ammonia (NH ₃ )
Growth temperature: 1100 ° C
Growth pressure: 100 Torr (133 hPa)
Film thickness: 140 nm to 300 nm

  The full width at half maximum of the rocking curve in the X-ray analysis on the (0002) plane of the AlN layer was measured for the plurality of substrates manufactured by the above method. FIG. 2 is a diagram illustrating the relationship between the film thickness of the AlN layer and the full width at half maximum. The horizontal axis in FIG. 2 is the film thickness of the AlN layer, and the vertical axis is the half width of the rocking curve in the X-ray analysis on the (0002) plane of the AlN layer. As can be seen from FIG. 2, the full width at half maximum decreases as the thickness of the AlN layer increases. That is, it can be seen that as the AlN layer becomes thicker, the crystallinity of the AlN layer becomes better. This is presumably because when the AlN layer is thin, many defects are generated in the AlN layer, but when the AlN layer is thick, such defects are reduced. However, if the AlN layer becomes too thick, cracks are likely to occur in the AlN layer.

  From this, considering the deterioration of crystallinity due to defects in the AlN layer, the thickness of the AlN layer is preferably 100 nm or more, more preferably 150 nm or more, and further preferably 200 nm or more. Considering cracks generated in the AlN layer, the thickness of the AlN layer is preferably 700 nm or less, more preferably 500 nm or less, and further preferably 300 nm or less. Therefore, when the nitride semiconductor layer 12 is an AlN layer, the thickness of the nitride semiconductor layer 12 is preferably 100 nm or more and 700 nm or less, more preferably 150 nm or more and 500 nm or less, and further preferably 200 nm or more and 300 nm or less.

Next, an experiment for examining the influence on the SiC layer 14 by providing the nitride semiconductor layer 12 between the Si substrate 10 and the SiC layer 14 will be described. The substrate used in the experiment (hereinafter referred to as “experimental substrate 1”) was produced by the following manufacturing method. First, an AlN layer having a hexagonal crystal structure was grown on the (111) plane, which is the upper surface of the Si substrate, under the following conditions using the MOVPE method. The AlN layer is formed on the (111) plane, which is the upper surface of the Si substrate, with the (0001) plane as the crystal growth plane. The size of the Si substrate is 4 inches.
Source gas: TMA, NH ₃
Growth temperature: 1100 ° C
Growth pressure: 100 Torr (133 hPa)
Film thickness: 250nm

The SiC layer was crystal-grown on the upper surface of the AlN layer under the following conditions by using a gas source molecular beam epitaxy (GSMBE) method. Here, since the melting point of the Si substrate is low, it is difficult to grow the SiC layer at a high temperature. Therefore, the SiC layer is grown at a lower temperature. In this case, the SiC layer easily takes a cubic crystal structure. The SiC layer is formed on the (0001) plane that is the upper surface of the AlN layer with the (111) plane as the crystal growth plane.
Source gas: Monomethylsilane (MMS: CH ₃ SiH ₃ )
Growth temperature: 800 ° C to 1050 ° C
Growth pressure: 2.5 × 10 ⁻² Pa, 4.0 × 10 ⁻² Pa
Film thickness: 100 nm

The full width at half maximum of the rocking curve in the X-ray analysis on the (111) plane of the SiC layer was measured for the plurality of experimental substrates 1 manufactured by the above method. For comparison, the full width at half maximum of the rocking curve in the X-ray analysis on the (111) plane of the SiC layer was also measured for the experimental substrate 2 manufactured by the following manufacturing method. In the experimental substrate 2, a SiC layer was grown on the (111) plane, which is the upper surface of the Si substrate, using the GSMBE method without an AlN layer under the following conditions. The SiC layer is formed on the (111) plane, which is the upper surface of the Si substrate, with the (111) plane as the crystal growth plane.
Source gas MMS
Growth temperature 800 ℃ ～ 1050 ℃
Growth pressure 2.5 × 10 ⁻² Pa
Film thickness 100nm

FIG. 3 is a diagram showing the relationship between the growth temperature of the SiC layer and the full width at half maximum. The horizontal axis in FIG. 3 is the growth temperature of the SiC layer, and the vertical axis is the half width of the rocking curve in the X-ray analysis on the (111) plane of the SiC layer. The circles in FIG. 3 are the measurement results of the experimental substrate 1 where the growth pressure of the SiC layer is 4.0 × 10 ⁻² Pa, and the triangles are the growth pressure of the SiC layer as 2.5 × 10 ⁻² Pa. The square board is the measurement result of the experimental substrate 2. As shown in FIG. 3, the experimental substrate 1 in the case where the growth pressure is 2.5 × 10 ⁻² Pa and 4.0 × 10 ⁻² Pa is smaller in half width than the experimental substrate 2, and the SiC layer As a result, a good crystallinity was obtained. This is considered to be due to the following reasons.

Table 1 is a table showing lattice constants, thermal expansion coefficients, and energy band gaps of Si, 4H—AlN, and 3C—SiC. For reference, the lattice constant, thermal expansion coefficient, and band gap energy of GaN, sapphire, 4H—SiC, and 6H—SiC are also shown.

  As shown in Table 1, the lattice constant of Si is 5.43Å, and the lattice constant of 3C-SiC is 4.36Å. For this reason, when the (111) plane of the SiC layer having a cubic crystal structure is directly formed on the (111) plane, which is the upper surface of the Si substrate, as in the experimental substrate 2, it is between the Si substrate and the SiC layer. Causes lattice distortion of about 20%. On the other hand, in the experimental substrate 1, the (111) plane of the SiC layer 14 having the cubic crystal structure is formed on the (111) plane, which is the upper surface of the Si substrate, via the (0001) plane of the AlN layer having the hexagonal crystal structure. ) The surface is formed. In this case, the lattice strain between the AlN layer and the SiC layer is as small as about 1%. Therefore, it is considered that the experimental substrate 1 can reduce the lattice strain applied to the SiC layer as compared with the experimental substrate 2, and as a result, the crystallinity of the SiC layer is improved.

  Table 1 also shows that even when a GaN layer is used instead of the AlN layer, lattice strain applied to the SiC layer can be suppressed and the crystallinity of the SiC layer can be improved. Furthermore, it can be seen that the difference in thermal expansion coefficient between the Si substrate and the SiC layer can be reduced by forming the AlN layer or the GaN layer between the Si substrate and the SiC layer. From these, it can be seen that the crystallinity of the SiC layer can be improved by forming the nitride semiconductor layer between the Si substrate and the SiC layer.

The growth rate of the SiC layer on the experimental substrate 1 and the experimental substrate 2 will be described. FIG. 4 is a diagram showing the relationship between the growth temperature and the growth rate of the SiC layer. The upper side of the horizontal axis in FIG. 4 is the growth temperature of the SiC layer, and the lower side of the horizontal axis is a value obtained by dividing 1000 by the growth temperature. The vertical axis in FIG. 4 represents the growth rate of the SiC layer. The circles in FIG. 4 are the measurement results of the experimental substrate 1 where the growth pressure of the SiC layer is 4.0 × 10 ⁻² Pa, and the triangles are the growth pressure of the SiC layer as 2.5 × 10 ⁻² Pa. The square board is the measurement result of the experimental substrate 2. As shown in FIG. 4, in the experimental substrate 2, when the growth temperature of the SiC layer exceeds 900 ° C., the growth rate is reduced. On the other hand, in the experimental substrate 1, even when the growth pressure is 2.5 × 10 ⁻² Pa and 4.0 × 10 ⁻² Pa, the growth is possible even when the growth temperature of the SiC layer is a high temperature of 900 ° C. or higher. It can be seen that the decrease in speed is suppressed.

Based on the experimental results described above, a method for manufacturing the substrate 100 of Example 1 shown in FIG. 1 when the nitride semiconductor layer 12 is an AlN layer will be described. First, the Si substrate 10 whose top surface is the (111) plane is prepared. A nitride semiconductor layer 12 made of an AlN layer having a hexagonal crystal structure is grown on the upper surface of the Si substrate 10 using the MOVPE method under the following conditions. The nitride semiconductor layer 12 is formed on the (111) plane, which is the upper surface of the Si substrate, with the (0001) plane as the crystal growth plane.
Source gas: TMA, NH ₃
Growth temperature: 1100 ° C
Growth pressure: 100 Torr (133 hPa)
Film thickness: 100 nm to 700 nm

The SiC layer 14 is crystal-grown on the upper surface of the nitride semiconductor layer 12 using the GSMBE method under the following conditions. As described above, SiC layer 14 has a cubic crystal structure, and is formed on the (0001) plane that is the upper surface of nitride semiconductor layer 12 with the (111) plane as the crystal growth plane. Further, by growing the SiC layer 14 by the GSMBE method, it is possible to grow at a low pressure, which is preferable from the viewpoint of the crystallinity of the SiC layer 14.
Source gas: MMS
Growth temperature: 800 ° C to 1050 ° C
Growth ^{pressure: 2.5 × 10 -2 Pa~4.0 × 10} -2 Pa
Film thickness: 50 nm to 500 nm

  A heat treatment is performed on the upper surface of the SiC layer 14 at a temperature of, for example, about 1200 ° C. to 1300 ° C. in a high vacuum. As a result, on the upper surface of the SiC layer 14, Si sublimates and only C remains, and graphene formation occurs in which the remaining C is connected to a six-membered ring, and the graphene layer 16 is formed. The substrate 100 of Example 1 is formed including such a manufacturing process.

Next, an experiment for evaluating the film quality of the graphene layer 16 provided on the substrate 100 of Example 1 will be described. The substrate 100 used in the experiment was manufactured by the following manufacturing method. First, the nitride semiconductor layer 12 made of an AlN layer having a hexagonal crystal structure was grown on the (111) plane, which is the upper surface of the Si substrate 10, using the MOVPE method under the following conditions.
Source gas: TAM, NH ₃
Growth temperature: 1100 ° C
Growth pressure: 100 Torr (133 hPa)
Film thickness: 150nm

The SiC layer 14 having a cubic crystal structure was grown on the upper surface of the nitride semiconductor layer 12 using the GSMBE method under the following conditions.
Source gas: MMS
Growth temperature: 1050 ° C
Growth pressure: 2.5 × 10 ⁻² Pa
Film thickness: 100 nm

In a high vacuum of 1.0 × 10 ⁻⁸ Pa to 1.0 × 10 ⁻⁹ Pa, the Si substrate 10 is heated to 1200 ° C. for several seconds, and then cooled to 800 ° C. three times to Repeated about 5 times, the surface cleaning which removes the foreign material and the water | moisture content of the upper surface of the SiC layer 14 was performed. Thereafter, the upper surface of the SiC layer 14 was heat-treated at 1250 ° C. for 10 minutes to grapheneize the upper surface of the SiC layer 14 to form the graphene layer 16.

The film quality of the graphene layer 16 provided on the substrate 100 of Example 1 manufactured by the above method was evaluated using Raman spectroscopy. The film quality of the graphene layer 16 can be evaluated by the value of D / G, which is the intensity ratio of the D band to the G band in Raman spectroscopy for the graphene layer 16. That is, it is possible to evaluate the value of D / G is a ratio of the peak intensity D of around 1350 cm ^-1 to the peak intensity G in the vicinity of 1590 cm ^-1 in Raman spectroscopy. Since the spectrum attributed to the edge portion of the grain of the graphene layer 16 is the D band and the spectrum attributed to the center portion is the G band, the value of D / G decreases as the grain size increases. Therefore, it can be said that the smaller the D / G value, the better the film quality of the graphene layer 16. For comparison, the film quality of the graphene layer 16 provided on the substrate of Comparative Example 1 manufactured by the same method as described above, except that the nitride semiconductor layer 12 is not formed, is also evaluated using Raman spectroscopy. did. Note that the evaluation by Raman spectroscopy was performed using a 2.41 eV laser beam at room temperature.

  FIG. 5A is a measurement result of Raman spectroscopy for the graphene layer 16 provided on the substrate 100 of Example 1, and FIG. 5B is a graph of Raman spectroscopy for the graphene layer 16 provided on the substrate of Comparative Example 1. It is a measurement result. As shown in FIG. 5B, the D / G value of the graphene layer 16 provided in the substrate of Comparative Example 1 is 1.18. On the other hand, as shown in FIG. 5A, the D / G value of the graphene layer 16 provided in the substrate 100 of Example 1 is 1.03. As described above, the result of Example 1 that the film quality of the graphene layer 16 was improved as compared with Comparative Example 1 was obtained. The reason why the film quality of the graphene layer 16 is improved in Example 1 is considered as follows.

  The first reason is that the SiC layer 14 is directly formed on the Si substrate 10 by forming the SiC layer 14 on the Si substrate 10 via the nitride semiconductor layer 12 as described in FIG. Compared to the above, the crystallinity of the SiC layer 14 is improved. For this reason, it is considered that the film quality of the graphene layer 16 formed on the upper surface of the SiC layer 14 is also improved.

  The second reason is that the graphene layer 16 is formed by performing a heat treatment on the SiC layer 14. This is because, as described above, Si is sublimated by the heat treatment, and the remaining C is graphene. It is formed by forming. In this case, when the SiC layer 14 is directly formed on the Si substrate 10, Si of the Si substrate 10 is diffused into the SiC layer 14 by the heat treatment, and as a result, graphene formation is hindered, and the graphene layer having good film quality It may be difficult to form 16. On the other hand, when the nitride semiconductor layer 12 is formed between the Si substrate 10 and the SiC layer 14 as in the first embodiment, the nitride semiconductor layer 12 suppresses the diffusion of Si in the Si substrate 10. The For this reason, it is considered that the graphene layer 16 having good film quality was formed. In view of suppressing the diffusion of Si in the Si substrate 10, an oxide film layer may be formed between the Si substrate 10 and the SiC layer 14. However, in this case, it is conceivable that in the heat treatment for the SiC layer 14, oxygen (O) in the oxide film layer reacts with C to make it difficult to form the graphene layer 16 having good film quality. Therefore, the layer between the Si substrate 10 and the SiC layer 14 is preferably the nitride semiconductor layer 12.

  As described above, in the substrate 100 of Example 1, the nitride semiconductor layer 12 is provided on the upper surface of the Si substrate 10 that is the (111) plane, and the SiC layer 14 is provided on the upper surface of the nitride semiconductor layer 12. A graphene layer 16 is provided on the upper surface of the SiC layer 14. As a result, as described with reference to FIG. 5A, it is possible to obtain a graphene layer 16 having a good film quality such that the D / G value in Raman spectroscopy is 1.1 or less. As shown in FIG. 5A, in the substrate 100 having the above structure, the graphene layer 16 having a D / G value of 1.08 or less in the Raman spectroscopy, or the graphene having a D / G value of 1.05 or less. It is also possible to obtain a layer 16.

  Although the case where the graphene layer 16 on the upper surface of the SiC layer 14 is formed by performing heat treatment on the upper surface of the SiC layer 14 is shown as an example, it may be formed by other methods. For example, the graphene layer 16 may be formed using a GSMBE method or MBE method using a gas containing C or a solid as a raw material, and using crystals on the upper surface of the SiC layer 14 as a template. Examples of the raw material include methane, ethane, propane, fullerene and the like.

  The nitride semiconductor layer 12 may be a layer other than the AlN layer and the GaN layer shown in Table 1, for example, an AlGaN layer, an InN layer, an InGaN layer, an InAlGaN layer, or the like. The nitride semiconductor layer 12 is preferably a group III-V nitride semiconductor layer, and more preferably an AlN layer from the viewpoint of further reducing the lattice strain applied to the SiC layer 14.

The second embodiment is an example of an electronic device including the substrate 100 of the first embodiment. FIG. 6 is a cross-sectional view illustrating the electronic apparatus according to the second embodiment. In the second embodiment, a case of a field effect transistor as an electronic device will be described as an example. As shown in FIG. 6, in the electronic device 200 of Example 2, the gate electrode 22 is provided on the graphene layer 16 provided on the substrate 100 of Example 1 with the gate insulating film 20 interposed therebetween. The gate insulating film 20 is an insulating film in which an aluminum oxide (Al ₂ O ₃ ) layer having a thickness of 5 nm and a silicon oxide (SiO ₂ ) layer having a thickness of 30 nm are stacked from the graphene layer 16 side, for example. The Al ₂ O ₃ layer can be formed, for example, by depositing aluminum (Al) by vapor deposition and then natural oxidation. The SiO ₂ layer can be formed using, for example, a plasma enhanced chemical vapor deposition (PCVD) method. The gate electrode 22 is, for example, a metal film in which titanium (Ti) and gold (Au) are stacked from the gate insulating film 20 side.

  On both sides of the gate electrode 22, a source electrode 24 and a drain electrode 26 are provided on the graphene layer 16. The source electrode 24 and the drain electrode 26 are metal films made of nickel (Ni) with a film thickness of 15 nm, for example. The gate electrode 22, the source electrode 24, and the drain electrode 26 can be formed using, for example, a vapor deposition method. A channel 28 is formed in the graphene layer 16 below the gate electrode 22 and between the source electrode 24 and the drain electrode 26. A source pad 30 is provided on the source electrode 24, and a drain pad 32 is provided on the drain electrode 26. The source pad 30 and the drain pad 32 are, for example, metal films in which Ti and Au are stacked from the electrode side. The source pad 30 and the drain pad 32 can also be formed using a vapor deposition method, for example.

  The electronic device 200 according to the second embodiment includes a field effect transistor in which a gate electrode 22 is provided on the graphene layer 16 provided on the substrate 100 according to the first embodiment, and a source electrode 24 and a drain electrode 26 are provided with the gate electrode 22 interposed therebetween. The channel 28 is formed in the graphene layer 16 below the gate electrode 22. Since the film quality of the graphene layer 16 provided on the substrate 100 of the first embodiment is good, the electronic device 200 of the second embodiment can obtain good characteristics.

  Next, a leakage current generated in the electronic device 200 according to the second embodiment will be described. First, considering the case where an AlN layer is used for the nitride semiconductor layer 12, an experiment for evaluating the insulating properties of the AlN layer will be described. In the experiment, a substrate in which an AlN layer with a thickness of 150 nm was formed on a Si substrate was used, and two pads of 50 μm × 50 μm size were placed on the top surface of the AlN layer at 10 μm intervals, and the current flowing between the pads was measured. As a result, the insulating properties of the AlN layer were evaluated.

FIG. 7 shows the experimental results of evaluating the insulating properties of the AlN layer. The horizontal axis in FIG. 7 is the voltage between the pads, and the vertical axis is the current flowing between the pads. As shown in FIG. 7, when a voltage of −4 V to +4 V is applied between the pads, the current flowing between the pads is about 1.0 × 10 ⁻¹⁰ A / mm to 1.0 ×, which is substantially below the measurement limit. It was about 10 ⁻¹² A / mm. That is, the AlN layer has at least 1.0 × 10 ¹² Ω / sq. It was confirmed that the resistance was high.

  Next, in the substrate 100 provided in Example 2, the current flowing from the SiC layer 14 to the Si substrate 10 was calculated by simulation. In the simulation, a nitride semiconductor layer 12 made of an AlN layer having a thickness of 120 nm and an SiC layer 14 having a thickness of 100 nm are sequentially stacked on the Si substrate 10 having a thickness of 1 μm. Then, a pad having a size of 50 μm × 50 μm was provided on the lower surface of the Si substrate 10 and the upper surface of the SiC layer 14, and the current flowing between the pads was calculated. For comparison, a simulation for calculating a current by a similar method was performed for Comparative Example 2 having a structure in which a SiC layer having a thickness of 100 nm was provided on a Si substrate having a thickness of 1 μm.

  FIG. 8 shows a simulation result of calculating a current flowing from the SiC layer to the Si substrate. The horizontal axis in FIG. 8 is the voltage between the pads, and the vertical axis is the current flowing between the pads. The solid line in FIG. 8 is the simulation result of Example 2, and the broken line is the simulation result of Comparative Example 2.

  As shown in FIG. 8, Example 2 obtained a result in which the current flowing from SiC layer 14 to Si substrate 10 was reduced as compared with Comparative Example 2. This is because the nitride semiconductor layer 12 provided between the Si substrate 10 and the SiC layer 14 has a large band gap energy as shown in Table 1 (for example, AlN layer: 6.2 eV, GaN layer: 3.39). ). For this reason, it is considered that the current flowing from the SiC layer 14 to the Si substrate 10 is reduced by forming a potential barrier in the current path.

  Thus, by forming the nitride semiconductor layer 12 between the Si substrate 10 and the SiC layer 14, the film quality of the graphene layer 16 on the upper surface of the SiC layer 14 can be improved, and the characteristics of the electronic device 200 are improved. In addition to this, it can be seen that the effect of reducing the leakage current can be obtained.

  In the second embodiment, the case of the field effect transistor including the substrate 100 of the first embodiment has been described as an example.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 Si substrate 12 Nitride semiconductor layer 14 SiC layer 16 Graphene layer 20 Gate insulating film 22 Gate electrode 24 Source electrode 26 Drain electrode 28 Channel 30 Source pad 32 Drain pad 100 Substrate 200 Electronic device

Claims (10)

A nitride semiconductor layer provided on the upper surface of the silicon substrate having the (111) plane as an upper surface;
A silicon carbide layer provided on an upper surface of the nitride semiconductor layer;
And a graphene layer provided on an upper surface of the silicon carbide layer.   The substrate according to claim 1, wherein a value of an intensity ratio (D / G) of a D band to a G band in Raman spectroscopy for the graphene layer is 1.1 or less.   The substrate according to claim 1, wherein the nitride semiconductor layer is an aluminum nitride layer.   4. The substrate according to claim 3, wherein the thickness of the aluminum nitride layer is not less than 100 nm and not more than 700 nm.   The substrate according to any one of claims 1 to 4, wherein the silicon carbide layer is a cubic silicon carbide layer. Forming a nitride semiconductor layer on the upper surface of the silicon substrate having the (111) plane as an upper surface;
Forming a silicon carbide layer on the top surface of the nitride semiconductor layer;
And a step of forming a graphene layer on the upper surface of the silicon carbide layer.   The method for manufacturing a substrate according to claim 6, wherein the graphene layer is formed by performing a heat treatment on an upper surface of the silicon carbide layer.   The method for manufacturing a substrate according to claim 6, wherein the nitride semiconductor layer is an aluminum nitride layer.   An electronic device comprising the substrate according to claim 1. A gate electrode provided on the graphene layer;
A source electrode and a drain electrode provided across the gate electrode, and
The electronic device according to claim 9, wherein a channel is formed in the graphene layer under the gate electrode.

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