JP5917849B2 - Semiconductor substrate and electronic device - Google Patents

Description

  The present invention relates to a semiconductor substrate and an electronic device.

  Nitride semiconductors such as GaN and AlGaN have features such as a high breakdown voltage, a high saturation drift velocity, chemical and thermal stability, and a large band gap. Utilizing these features, application to various electronic devices is expected.

  However, high density dislocations are likely to occur in a nitride semiconductor produced by a conventional manufacturing method. When an electronic device is manufactured using such a nitride semiconductor having dislocations at a high density, the characteristics such as withstand voltage and electron mobility are often lower than expected theoretically.

  On the other hand, nitride semiconductors have different thermal expansion coefficients and lattice constants depending on their compositions. For this reason, when nitride semiconductor layers having different compositions are stacked, stress is generated in each layer, and the crystals are destroyed when the stress exceeds the elastic limit. In order to avoid crystal breakage, it is necessary to control the generated stress so as not to exceed the elastic limit.

  Non-Patent Document 1 discloses that when an AlGaN layer and a GaN layer are repeatedly epitaxially grown on a Si substrate, and an active layer made of InGaN multiple quantum wells is epitaxially grown thereon, the dislocation density of the active layer decreases. Patent Document 1 discloses a repetitive structure of a laminate in which crystal layers having different lattice constants or different thermal expansion coefficients are laminated, and controls the stress generated by controlling the combination of crystal layers constituting the repetitive structure. Disclosed is a technique capable of avoiding the destruction of the device. Non-Patent Document 2 discloses that when a GaN crystal is doped with silicon atoms, the lattice constant of the GaN crystal changes and the stress generated in the crystal layer increases.

  Patent Document 2 discloses a plate-like substrate having a substrate composed of a silicon substrate and a buffer region, and first, second, and third main semiconductor regions for constituting a light emitting diode. An n-type buffer region in which first and second nitride-based compound semiconductor layers are alternately stacked is described as the buffer region, and an n-type gallium nitride-based compound semiconductor such as GaN is described as the first main semiconductor region. ing.

JP 2009-289956 A JP-A-2005-159207

S.A.Nikishin, et.al., Jpn. J. Appl. Phys. 40 (2001) pp. L738-L740 L.T.Romano, et.al., J.A.P., 87 (2000) 7745-7752

  With the repeating structure described in Non-Patent Document 1, there is a possibility that the dislocation density of the active layer of the nitride semiconductor can be reduced. In addition, with the repetitive structure described in Patent Document 1, the stress of the nitride semiconductor crystal can be controlled, and a certain effect can be expected for the purpose of avoiding crystal breakdown.

  However, when silicon atoms, which are n-type impurity atoms, are doped into the active layer in order to make the conductivity type of the active layer made of a nitride semiconductor n-type, it is generated in the active layer as described in Non-Patent Document 2. Stress increases. As a result, dislocations in the nitride semiconductor crystal that is the active layer may increase, and the suppression of crystal breakage may not be sufficient. An object of the present invention is a technique capable of reducing dislocations generated in an active layer even when an active layer made of a nitride semiconductor is doped with n-type impurity atoms, or suppressing crystal breakdown of the active layer. It is to provide a technology that can do.

In order to solve the above problems, in a first aspect of the present invention, a base substrate, a stacked structure in which a plurality of first crystal layers and second crystal layers are alternately stacked, and a third crystal layer are provided. The base substrate, the stacked structure, and the third crystal layer are positioned in the order of the base substrate, the stacked structure, and the third crystal layer, and the first crystal layer is Al _x Ga _{1− xN} , (where 0 ≦ x ≦ 1), and the second crystal layer is composed of Al _y Ga _1-y N (where 0 ≦ y ≦ 1, x ≠ y), and the third crystal layer is And a semiconductor substrate comprising Al _z Ga _1-z N (where 0 ≦ z ≦ 1) and containing silicon atoms in the first crystal layer, the second crystal layer, and the third crystal layer.

Examples of the base substrate include those made of silicon crystals. The thickness of the third crystal layer is preferably not less than 0.5 μm and not more than 10 μm. The aluminum composition ratio z of the third crystal layer is preferably 0 or more and 0.05 or less. It is preferable that the aluminum composition ratio x of the first crystal layer and the aluminum composition ratio y of the second crystal layer satisfy a relationship of | y−x |> 0.5. The number of repetitions of the first crystal layer and the second crystal layer in the stacked structure is preferably 2 or more and 160 or less. It is preferable that the concentration of the silicon atoms is 1 × 10 ¹⁷ atoms / cm ³ or more.

  According to a second aspect of the present invention, there is provided an electronic device using the semiconductor substrate described above, wherein a part of the third crystal layer in the semiconductor substrate is an active region, and carriers in the active region are the semiconductor substrate. An electronic device having a vertical structure that moves in the vertical direction is provided.

A cross section of a semiconductor substrate 100 is shown.

  FIG. 1 shows a cross section of a semiconductor substrate 100. The semiconductor substrate 100 includes a base substrate 102, a buffer layer 104, a stacked structure body 110 including a first crystal layer 106 and a second crystal layer 108, and a third crystal layer 112. The base substrate 102, the stacked structure body 110, and the third crystal layer 112 are located in the order of the base substrate 102, the stacked structure body 110, and the third crystal layer 112.

Any material and structure can be selected for the base substrate 102 as long as the stacked structure 110 and the third crystal layer 112 can be formed thereon. That is, GaAs, InP, GaN, SiC, Si, sapphire (Al ₂ O ₃ ) or the like can be selected as the material of the base substrate 102, and the structure of the base substrate 102 is single crystal, polycrystalline or amorphous (amorphous). Can be selected. Examples of the base substrate 102 include a silicon substrate and an SOI (Silicon on Insulator) substrate. As the base substrate 102, a silicon crystal substrate (for example, a silicon wafer) is particularly preferable. By using a silicon crystal substrate, it is not necessary to use an expensive compound semiconductor crystal substrate, and an existing manufacturing apparatus and an existing manufacturing process can be used. Therefore, manufacturing cost can be reduced.

  The buffer layer 104 is a crystal layer formed between the base substrate 102 and the stacked structure 110 in order to increase the crystallinity of the stacked structure 110. The crystallinity of the buffer layer 104 is not necessarily high. An example of the buffer layer 104 is an AlN layer. The buffer layer 104 is preferably a non-doped layer that is not doped with impurity atoms. An example is a non-doped AlN layer. By using a non-doped AlN layer as the buffer layer 104, the electric resistance of the buffer layer 104 can be increased, and the electronic device formed in the third crystal layer 112 and the base substrate 102 can be electrically separated.

  The stacked structure 110 is a crystal layer in which a plurality of first crystal layers 106 and second crystal layers 108 are alternately stacked. The stacked structure 110 is a repetitive structure including the first crystal layer 106 and the second crystal layer 108, and improves the crystallinity of the third crystal layer 112 formed on the stacked structure 110. The dislocation density of 112 is reduced. In addition, the stress of the multilayer structure 110 is controlled by the repeated structure of the multilayer structure 110, thereby avoiding crystal breakdown of the multilayer structure 110 itself. As a result, crystal breakage of the third crystal layer 112 formed on the stacked structure 110 is avoided.

  The number of repetitions of the first crystal layer 106 and the second crystal layer 108 in the stacked structure 110 is preferably 2 or more and 160 or less. By setting the number of repetitions to 2 or more, a repeating structure can be formed. However, the number of repetitions is more preferably set to such a degree that the effects of the above-described repeating structure (an effect of reducing the dislocation density of the third crystal layer 112 and an effect of avoiding the crystal breakage of the stacked structure 110 itself) are exhibited. preferable. If the number of repetitions exceeds 160, the effect of the repeating structure is almost saturated, while the manufacturing cost increases. Therefore, it is appropriate that the number of repetitions is 160 or less.

  The laminated structure 110 is formed of the first crystal layer 106 / second crystal layer 108 /... / First crystal layer 106 / second crystal layer 108 along the direction from the base substrate 102 toward the third crystal layer 112. In the first case (in the case shown in FIG. 1) formed in order, the second crystal layer 108 / first crystal layer 106 /... / Second crystal layer 108 / first crystal layer 106 are formed in this order. In any of the cases (not shown).

  In the first case, when the composition and impurity concentration of the buffer layer 104 and the first crystal layer 106 match, the buffer layer 104 and the first crystal layer 106 cannot be distinguished. In this case, the thickness of the buffer layer 104 is slightly increased, and is grasped as a layer structure such as the base substrate 102 / buffer layer 104 / second crystal layer 108 /... / First crystal layer 106 / second crystal layer 108. it can. In the first case, if the composition and impurity concentration of the second crystal layer 108 and the third crystal layer 112 match, the second crystal layer 108 and the third crystal layer 112 cannot be distinguished. In this case, the thickness of the third crystal layer 112 is slightly increased, and the first crystal layer 106 / second crystal layer 108 /... / First crystal layer 106 / third crystal layer 112 is grasped as a layer structure. it can.

  In the second case, when the composition and impurity concentration of the buffer layer 104 and the second crystal layer 108 match, the buffer layer 104 and the second crystal layer 108 cannot be distinguished. In this case, the thickness of the buffer layer 104 is slightly increased, and is grasped as a layer structure such as the base substrate 102 / buffer layer 104 / first crystal layer 106 /... / Second crystal layer 108 / first crystal layer 106. it can. In the second case, if the compositions and impurity concentrations of the first crystal layer 106 and the third crystal layer 112 match, the first crystal layer 106 and the third crystal layer 112 cannot be distinguished. In this case, the thickness of the third crystal layer 112 is slightly increased, and the second crystal layer 108 / first crystal layer 106 /... / Second crystal layer 108 / third crystal layer 112 is grasped as a layer structure. it can.

The first crystal layer 106 is made of Al _x Ga _1-x N (where 0 ≦ x ≦ 1), and the second crystal layer 108 is Al _y Ga _1-y N (where 0 ≦ y ≦ 1, x ≠ y). Although the first crystal layer 106 and the second crystal layer 108 have different compositions, both are crystal layers of an aluminum / gallium nitrogen compound semiconductor. By controlling the composition and thickness of the first crystal layer 106 and the second crystal layer 108, the stress, crystallinity, and the like of the multilayer structure 110 can be controlled. In addition, the aluminum composition ratio of one of the first crystal layer 106 and the second crystal layer 108 can be increased to increase the band gap, and the insulating property of the stacked structure 110 can be increased. Alternatively, the composition ratio of the layer in contact with the third crystal layer 112 can be made closer to the third crystal layer 112 by increasing the other gallium composition ratio, and the dislocation density of the third crystal layer 112 can be reduced. For example, the aluminum composition ratio x of the first crystal layer 106 and the aluminum composition ratio y of the second crystal layer 108 can satisfy the relationship | y−x |> 0.5. If x and y differ from each other by more than 0.5, both the stress control of the laminated structure 110 and the reduction of the dislocation density of the third crystal layer 112 can be satisfied.

The third crystal layer 112 is made of Al _z Ga _1-z N (where 0 ≦ z ≦ 1). The third crystal layer 112 is a crystal layer that functions as an active layer of an electronic device, and is required to be a high-quality crystal with few dislocations. In consideration of functioning as an active layer, the aluminum composition ratio z of the third crystal layer 112 is preferably 0 or more and 0.05 or less.

  Examples of the thickness of the third crystal layer 112 include 0.5 μm or more and 10 μm or less. When the thickness of the third crystal layer 112 is 0.5 μm or more, the film stress of the third crystal layer 112 increases, and problems such as crystallinity degradation due to dislocations and film peeling (crystal breakdown) become obvious. . The present invention improves the crystallinity of the third crystal layer 112 and suppresses peeling even in such a situation, and the effect of the present invention is effective when the thickness of the third crystal layer 112 is 0.5 μm or more. It is more prominent. However, if the thickness of the third crystal layer 112 exceeds 10 μm, film peeling (crystal breakage) cannot be avoided. Therefore, the thickness of the third crystal layer 112 is preferably 10 μm or less.

  The first crystal layer 106, the second crystal layer 108, and the third crystal layer 112 contain silicon atoms. When the third crystal layer 112 functions as an n-type active layer, it is necessary to dope silicon atoms as impurity atoms exhibiting n-type conduction. In such a case, the stress of the third crystal layer 112 increases, and the crystallinity is lowered and film peeling is likely to occur. However, in the present invention, silicon atoms are also introduced into the first crystal layer 106 and the second crystal layer 108 (laminated structure 110). As a result, the stresses of the first crystal layer 106 and the second crystal layer 108 increase to a degree commensurate with the increase in stress of the third crystal layer 112, and the multilayer structure 110 and the third crystal layer 112 are easily lattice-matched. . As a result, the crystallinity of the third crystal layer 112 can be increased (dislocations can be reduced), and peeling of the third crystal layer 112 from the stacked structure 110 can be suppressed.

Note that introduction of silicon atoms into the first crystal layer 106 and the second crystal layer 108 may reduce the electrical resistance of the stacked structure 110, but as described above, the first crystal layer 106 or the second crystal layer 106 Decreasing the electrical resistance of the multilayer structure 110 can be suppressed by increasing the aluminum composition ratio of any one of the crystal layers 108 or increasing the number of repetitions of the repeating structure. The concentration of silicon atoms contained in the first crystal layer 106, the second crystal layer 108, and the third crystal layer 112 is preferably 1 × 10 ¹⁷ atoms / cm ³ or more. By setting it to 1 × 10 ¹⁷ atoms / cm ³ or more, necessary conductivity for the third crystal layer 112 can be ensured.

  According to the semiconductor substrate 100 described above, even if silicon atoms are included in the third crystal layer 112 as n-type impurity atoms, the first crystal layer 106 and the second crystal layer 108 (laminated structure 110) have silicon. Since it contains atoms, the crystallinity of the third crystal layer 112 functioning as an active layer can be improved. As a result, the performance of the electronic device formed in the third crystal layer 112 can be improved.

  The present invention can also be understood as an electronic device having a part of the third crystal layer 112 as an active region. In this case, the third crystal layer 112 has a vertical structure in which carriers in the active region move in the vertical direction of the semiconductor substrate 100, taking advantage of the fact that the thickness of the third crystal layer 112 can be formed as thick as 0.5 μm or more and 10 μm or less. It can be an electronic device. Examples of the electronic device having the vertical structure include a Schottky barrier diode, a PIN diode, and an insulated gate bipolar transistor.

The buffer layer 104, the first crystal layer 106, the second crystal layer 108, and the third crystal layer 112 can be formed by an epitaxial crystal growth method. When using a MOCVD (Metal Organic Chemical Vapor Deposition) method as an epitaxial crystal growth method, as a raw material gas, TMA (trimethyl aluminum), TMG (trimethyl gallium) may be used NH ₃ (the ammonia), Si as the silicon doping gas ₂ H ₆ (disilane) and SiH ₄ (silane) can be used, and H ₂ (hydrogen gas) and N ₂ (nitrogen gas) can be used as the carrier gas.

(Example)
The buffer layer 104, the first crystal layer 106, the second crystal layer 108, and the third crystal layer 112 of the semiconductor substrate 100 are respectively an AlN layer, an AlN layer, a GaN layer, and a GaN layer, and the thickness, silicon atom concentration, and repetition of each layer. A semiconductor substrate of Example 1 with the number as shown in Table 1 was prepared.

For comparison, a semiconductor substrate of Comparative Example 1 in which the third crystal layer 112 in the semiconductor substrate of Example 1 was not doped with silicon atoms was prepared (see Table 2).

In addition, a semiconductor substrate of Example 2 was prepared in which the thickness, silicon atom concentration, and number of repetitions of the AlN layer, AlN layer, GaN layer, and GaN layer were as shown in Table 3.

For comparison, a semiconductor substrate of Comparative Example 2 in which the first crystal layer 106 and the second crystal layer 108 in the semiconductor substrate of Example 2 were not doped with silicon atoms was formed (see Table 4).

実施例１と比較例１を比較すれば、クラック密度および転位密度の両方で実施例１の方が低い値を示している。これは、第３結晶層１１２にシリコン原子をドーピングしない比較例１に対し、第１結晶層１０６、第２結晶層１０８および第３結晶層１１２の全ての層にシリコン原子をドーピングした実施例１の結晶性改善の効果を示しているといえる。 Table 5 shows the results of measuring the crack density and the dislocation density for each of the semiconductor substrates of Example 1, Comparative Example 1, Example 2, and Comparative Example 2 described above.

Comparing Example 1 and Comparative Example 1, Example 1 shows lower values in both crack density and dislocation density. This is because the first crystal layer 106, the second crystal layer 108, and the third crystal layer 112 are all doped with silicon atoms, compared to the first comparative example in which the third crystal layer 112 is not doped with silicon atoms. It can be said that this shows the effect of improving crystallinity.

  Further, when Example 2 and Comparative Example 2 are compared, Example 2 shows lower values in both crack density and dislocation density. This is because, compared to Comparative Example 2 in which the second crystal layer 108 and the third crystal layer 112 are not doped with silicon atoms, all of the first crystal layer 106, the second crystal layer 108, and the third crystal layer 112 have silicon atoms. It can be said that the effect of improving the crystallinity of Example 2 doped with is shown.

  100 semiconductor substrate, 102 base substrate, 104 buffer layer, 106 first crystal layer, 108 second crystal layer, 110 stacked structure, 112 third crystal layer.

Claims (6)

A base substrate, a stacked structure in which a plurality of first crystal layers and second crystal layers are alternately stacked, and a third crystal layer functioning as an active layer of an electronic device,
The base substrate, the stacked structure, and the third crystal layer are positioned in the order of the base substrate, the stacked structure, and the third crystal layer,
The first crystal layer is made of Al _x Ga _1-x N (where 0 ≦ x ≦ 1),
The second crystal layer is made of Al _y Ga _1-y N (where 0 ≦ y ≦ 1, x ≠ y);
The third crystal layer is made of Al _z Ga _1-z N (where 0 ≦ z ≦ 1);
The first crystal layer, the second crystal layer, and the third crystal layer contain silicon atoms having a concentration of 1 × 10 ¹⁷ atoms / cm ³ or more and 2 × 10 ¹⁸ atoms / cm ³ or less ,
The semiconductor substrate, wherein the third crystal layer has a thickness of 1.4 μm or more and 10 μm or less. The semiconductor substrate according to claim 1, wherein the base substrate is made of silicon crystal. The semiconductor substrate according to claim 1, wherein an aluminum composition ratio z of the third crystal layer is 0 or more and 0.05 or less. 4. The semiconductor substrate according to claim 1, wherein an aluminum composition ratio x of the first crystal layer and an aluminum composition ratio y of the second crystal layer satisfy the relationship of Equation 1. 5.
(Equation 1)
| Y-x |> 0.5 The semiconductor substrate according to any one of claims 1 to 4, wherein a number of repetitions of the first crystal layer and the second crystal layer in the stacked structure is 2 or more and 160 or less. An electronic device using the semiconductor substrate according to any one of claims 1 to 5 ,
A part of the third crystal layer in the semiconductor substrate is an active region,
An electronic device comprising a vertical structure in which carriers in the active region move in the vertical direction of the semiconductor substrate.

Images