JP2003058133A - Image display device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide technology advantageous for downsizing a image display device by reducing an occupancy area of a signal line driving circuit. SOLUTION: N lines of (where n is a natural number equal to or greater than two) signal line are commonly used for a storage circuit and a D/A converting circuit in a signal line driving circuit. By dividing one horizontal scanning interval into n intervals, the storage circuit and the D/A converting circuit conduct processes for respective different signal lines in the divided intervals so that all signal lines are property driven. Thus, the number of the storage circuits in the signal line driving circuit and the number of the D/A converting circuits are reduced to 1/n of a conventional case.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method of an image display device for inputting a digital video signal, and to an image display device using the driving method. Furthermore, the present invention relates to an electronic device using the image display device.

[0002]

2. Description of the Related Art In recent years, research and development of thin film transistors (TFTs) using a polycrystalline silicon film as an active layer have been actively conducted. Since a TFT using a polycrystalline silicon film has a mobility higher than that of a TFT using an amorphous silicon film by two digits or more, even if the gate width of the TFT is made small, the current value necessary for the circuit operation can be reduced. You can secure enough. Therefore, it is possible to realize a system-on-panel in which a pixel portion of an active matrix type flat panel display and its driving circuit are integrally formed on the same substrate.

The realization of a system-on-panel makes it possible to reduce the cost by reducing the assembling process and the inspection process of the display, and also enables the miniaturization and high definition of the flat panel display.

By the way, in the drive circuit of the image display device,
Some are driven by using an analog video signal, and some are driven by using a digital video signal. The drive circuit driven by using a digital video signal can be input to the drive circuit as it is without converting the digital broadcasting radio waves into analog, and it can be applied to recent digital broadcasting, so it is a promising candidate. Has been done.

FIG. 20 shows a general structure of an active matrix type liquid crystal display device which is a kind of active matrix type image display device driven by using a digital video signal. As shown in FIG. 20, the liquid crystal display device includes a signal line driver circuit 9001, a scan line driver circuit 9002, a pixel portion 9003, a signal line 9004, a scan line 9005, and a pixel TF.
T9006, liquid crystal cell 9007 and the like. The liquid crystal cell 9007 includes a pixel electrode, a counter electrode,
It has a liquid crystal provided between the pixel electrode and the counter electrode.

A detailed configuration of the signal line driving circuit 9001 is shown in FIG. FIG. 22 is a timing chart in the signal line drive circuit shown in FIG. Here, an image display device having k (horizontal) × l (vertical) pixels will be described as an example. In order to make the description easy to understand, the case where the digital video signal has 3 bits is illustrated, but the number of bits is not limited to 3 in an actual image display device. In addition, FIG.
In FIG. 22, it is shown by using a specific numerical value of k = 640.

A general signal line drive circuit mainly includes a shift register 9100, first and second memory circuit groups 9101,
9102 and a D / A conversion circuit group 9103. The shift register 9100 has a plurality of delay flip-flops (DFF). The first memory circuit group 9101 and the second memory circuit group 9102 each include a plurality of first memory circuits and a plurality of second memory circuits. Note that in FIG. 21, a first latch (LAT1) is used as the first memory circuit and a second latch (LAT2) is used as the second memory circuit. And D / A conversion circuit group 9
Reference numeral 103 has a plurality of D / A conversion circuits (DAC).

The shift register 9100 sequentially shifts the pulse of the output signal in response to the input signal line drive circuit clock signal (S-CLK) and signal line drive circuit start pulse (S-SP). The first memory circuit group 9101 sequentially stores digital video signals in synchronization with the output signal of the shift register 9100. The second memory circuit group 9102 stores the output of the first memory circuit group 9101 in synchronization with the latch pulse. D / A conversion circuit group 9
103 converts the output signal of the second memory circuit group 9102 into an analog signal.

The detailed structure and operation of the signal line drive circuit will be described below. The number of DFF stages of the shift register 9101 (corresponding to the number of DFFs shown in FIG. 21) is k + 1 since the number of pixels in the horizontal direction is k. A control signal which is an output signal of the shift register (see FIG.
Then, SR-001 to SR-640) have pulses shifted by one cycle of S-CLK, as shown in FIG. Control signal (SR-001 to SR-640)
Is a first memory circuit group 91 directly or via a buffer.
01 is input to the first latch (LAT1).

The first latch (LAT1) stores the input 3-bit digital video signal (D0 to D2) in synchronization with the control signal. The pulse of the control signal output from the shift register 9100 is shifted by the same number as the number k of pixels for one line, so that the digital video signal corresponding to the pixels for one line is transferred to the first latch (LA).
Stored in T1). Therefore, the first latch (LAT
1) requires 3 (the number of bits of the digital video signal) × k (the number of pixels in the horizontal direction).

Next, during the blanking period, the input latch pulse (LP) causes the second latch (LAT2) of the second memory circuit group 9102 to operate and the first latch (L).
Digital video signal stored in AT1) (FIGS. 21 and 2)
2, L1-001 to L1-640) are stored in the second latch (LAT2). Therefore, the second latch (L
AT2) also requires 3 × k. In FIG. 21, L1-001 to L1-640 are shown by numbering corresponding pixels without distinguishing the number of bits.

When the retrace line period ends and the next horizontal scanning period starts, the shift register 9100 again starts operation and outputs a control signal, and the digital video signal (D0 to D2) to the first latch (LAT1). The input of is started. on the other hand,
The digital video signals (L2-001 to L2-640) stored in the second latch (LAT2) are converted into analog signals in the D / A conversion circuit (DAC) of the D / A conversion circuit group 9103, and Source signal line (S1 to S64
0) is input as an analog video signal. This analog video signal is written in the pixel electrode of the liquid crystal cell when the pixel TFT of each pixel is turned on.

By the above operation, the image display device displays.

[0014]

The digital drive circuit that performs the above operation has a drawback that its occupied area is much larger than that of an analog drive circuit. The digital method has an advantage that the signal can be represented by two values of “Hi” or “Lo”, but instead, the amount of data becomes enormous and the number of circuit elements also increases to process the data. Therefore, an increase in the occupied area of the drive circuit on the substrate cannot be suppressed, which greatly hinders downsizing of the image display device.

Further, in recent years, along with the rapid increase in the amount of information to be handled, the number of pixels and the definition of pixels have been increased. However, it is expected that as the number of pixels increases, the number of circuit elements included in the drive circuit also increases and the area of the drive circuit increases.

Here, an example of the display resolution of a commonly used computer is shown below by the number of pixels and the standard name. Number of pixels Standard name 640 × 480 VGA 800 × 600 SVGA 1024 × 768 XGA 1280 × 1024 SXGA 1600 × 1200 UXGA

For example, in the case of the SXGA standard, assuming that the number of bits is 8, in the above-described conventional drive circuit, for the 1280 signal lines, the first storage circuit and the second storage circuit each have 10240 (8 ×). 1280) are required. Further, high-definition television receivers such as high-definition TV (HDTV) have become widespread, and high-definition images are required not only in the computer world but also in the field of AV. Terrestrial digital broadcasting has begun in the United States, and the age of digital broadcasting will also begin in Japan. In digital broadcasting, the standard of 1920 × 1080 pixels is influential, and reduction of the drive circuit is urgently required.

However, as described above, the signal line drive circuit occupies a large area, which hinders downsizing of the image display device. In order to solve such a problem, the present invention reduces the area occupied by the signal line drive circuit and provides a technique advantageous for downsizing.

[0019]

In view of the above problems, the present invention provides a memory circuit and a D / A conversion circuit in a signal line driving circuit,
It is shared by the signal lines of the book (n is a natural number of 2 or more). Then, one horizontal scanning period is divided into n pieces, and in each of the divided periods, the memory circuit and the D / A conversion circuit perform processing on different signal lines, so that within one horizontal scanning period, Video signals can be input to all signal lines.
In this way, the number of storage circuits and D / A conversion circuits in the signal line drive circuit can be reduced to 1 / n of the conventional example.

Further, according to the present invention, the order of inputting the video signals to the n signal lines is changed every horizontal scanning period or every plural horizontal scanning periods.

Adjacent signal lines are capacitively coupled directly or indirectly. Therefore, when a video signal is written in one signal line, the potential held in the signal line adjacent to the signal line is affected and changes. That is, the signal line in which the video signal is written first is more likely to change due to the influence of the writing in the signal line in which the video signal is written later.

Therefore, when the order of inputting the video signals is fixed, only the potential of the specific signal line is largely deviated from its ideal value. Then, in the pixel connected to the signal line with the changed potential, the relative gradation expression is always different from the pixel connected to the other signal line, and vertical stripes parallel to the signal line are visually recognized by human eyes. Will be done.

However, according to the present invention, the position of the pixel modulated in the write potential in the horizontal direction changes every fixed period (specifically, every horizontal scanning period or every plural horizontal scanning periods). , Vertical stripes are hard to see by human eyes.

The order of the signal lines for inputting the video signals may be random or may have a certain regularity. Further, the order does not have to be changed for every one horizontal scanning period, and the order may be changed for every two horizontal scanning periods or every other horizontal scanning period. However,
It is important to set the number of horizontal scanning periods to the extent that vertical stripes are less visible to the human eye. Since vertical stripes are hard to see when the frame frequency is increased, it is preferable to set the number of horizontal scanning periods in which the order is changed in consideration of the frame frequency.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. Here, in general, an image display device in which the numbers of pixels in the horizontal direction and the number of pixels in the vertical direction are k and 1 respectively will be described as an example. In this embodiment, the case where the digital video signal has 3 bits will be described, but the present invention is not limited to 3 bits, and can be applied to 6 bits, 8 bits, or any other number of bits. Also, in the following description,
N is used as a parameter indicating the number of signal lines sharing one D / A conversion circuit, but when the number of pixels k in the horizontal direction is not a multiple of n, new pixels are appropriately added,
The number of pixels in the horizontal direction is set to a multiple k'of n larger than k. In this case, the number of pixels k ′ may be newly defined as k. If the added pixel is treated as a virtual one, it does not hinder the actual operation.

FIG. 1 shows the configuration of the signal line drive circuit of this embodiment, and FIG. 2 shows its timing chart. However, FIGS. 1 and 2 show a specific example in which the number of horizontal pixels k = 640. In the following, symbols such as k will be used for general description, but specific numbers in the case of k = 640 will be shown in []. Although FIG. 1 shows the case where n = 4, n is not limited to this numerical value as long as it is a natural number of 2 or more.

The signal line driver circuit of this embodiment mode has a shift register 101 having a plurality of delay flip-flops (DFF) and a first memory circuit having a plurality of first memory circuits.
Memory circuit group 102, a second memory circuit group 103 having a plurality of second memory circuits, and a plurality of D / A conversion circuits (D
AC) D / A conversion circuit group 104 and a plurality of signal line selection circuits (SEL) signal line selection circuit group 10
5 and 5. Note that in FIG. 1, a first latch (LAT1) is used as the first memory circuit and a second latch (LAT2) is used as the second memory circuit. In FIG. 1, FIG.
Unlike the image display device shown in, two types of latch signal lines (LPa, LPb) are supplied, and the first half of the second memory circuit (corresponding to the DFF in the 1st to 80th [1 to k / 2n] stage) The first latch signal line (LPa) is connected to the second latch signal line (LPa) and the second latch signal line (LATa corresponding to the DFF of the 81st to 160th [1+ (k / 2n) to k / n] stages) is connected to the second latch signal line L
Pb) are respectively connected. In the present invention, the number of latch signal lines may be one.

Specifically, in FIG. 1, the shift register 10
1, the DFF has (k / n) +1 stages [161 stages], the first memory circuit (LAT1) and the second memory circuit (LAT2) each have 3k / n [480], and D / A conversion. The circuit (DAC) is composed of k / n [160]. As can be seen from FIG. 1, the number of circuits forming the signal line drive circuit is about 1 / n [1/4] of that of the signal line drive circuit shown in FIG.

Next, the operation will be described with reference to FIG. To the shift register 101, a signal line driver circuit start pulse (S-SP) and a signal line driver circuit clock signal (S-CLK) are input. In FIG. 22, the S-SP pulse appears once in one horizontal scanning period, whereas in the present embodiment, it appears n times [4 times]. As in FIG. 22, the shift register 101 sequentially shifts the pulse of the output signal according to the input S-SP and S-CLK. The output signal is a control signal [SR-001 to SR-1
60] to the first memory circuit (LAT1).

The digital video signals (D0 to D) are synchronized with the pulses of the control signal output from the shift register 101.
2) are sequentially stored in the first storage circuit (LAT1).
The number of stages of the DFF is about 1 / n [1/4] of FIG. 21, and in the present invention, the first memory circuit performs n [4] memory operations during one horizontal scanning period. . In FIG. 1, digital video signals L1-001 to L1 input from the first memory circuit group 102 to the second memory circuit group 103.
-160 is shown by numbering each corresponding signal line without distinguishing the number of bits.

Unlike FIG. 21, the digital video signal L1-
Each of 001 to L1-160 corresponds to n signal lines. For example, in FIG. 2, the digital video signal L1-0
01 corresponds in order to the signal lines S1 to Sn [S1 to S4]. Similarly, digital video signals L1-001 to L1-
160 is represented by the numbers of the corresponding signal lines, in order, S1 to Sn, Sn + 1 to S2n, S2n + 1 to S3.
n, ..., Sk-n + 1 to Sk [S1 to S4, S5 to S
8, S9 to S12, ..., S637 to S640].

In one horizontal scanning period, the digital video signal L1
-I (i = 1 to 160) outputs the information of the corresponding n signal lines, but the order of the corresponding signal lines is not necessarily fixed. In the present invention, the order in which the digital video signal L1-i (i = 1 to 160) is output with respect to the signal line is changed every horizontal scanning period. In other words, the order of the signal lines corresponding to each of the digital video signals L1-001 to L1-160 is changed every horizontal scanning period. This order is realized by converting the data arrangement of the digital video signals (D0 to D2) so that it becomes the same as the selection order of the signal lines of the signal line selection circuit described later.

The number of latch pulses input to the second memory circuit group 103 via the two types of latch signal lines (LPa, LPb) in one horizontal scanning period is n, respectively, 2n in total [8]. The pulse of appears. The latch pulse is input not only during the blanking period but also during the period during which the digital video signal is being input.

In the present embodiment, the (k / 2n) th stage [8
0th stage] The first storage circuit (LAT1) is written to the first storage circuit (LAT1) at the first stage after the writing of the digital video signal corresponding to the preceding signal line is completed. The latch pulse is input to the first latch signal line (LPa) before the data is rewritten to the digital video signal corresponding to the next signal line. In addition, the (k / n) th stage [1
(60th stage), after writing of the digital video signal corresponding to the preceding signal line to the first storage circuit (LAT1) is completed, the first (k / 2n) + 1st stage (81st stage) The latch pulse is input to the second latch signal line (LPb) before the data written in the storage circuit (LAT1) is rewritten into the digital video signal corresponding to the next signal line.

That is, when the writing of the digital video signal to the first storage circuit in the first half is completed, the writing of the digital video signal to the first storage circuit in the second half is started. While the digital video signal is being written to the first storage circuit in the second half, the digital video signal written in the first storage circuit in the first half is transferred to the second storage circuit in the first half. . When the writing of the digital video signal to the first memory circuit in the latter half is completed,
Writing of the next digital video signal is started. While the digital video signal is being written to the first storage circuit in the first half, the digital video signal written in the first storage circuit in the second half is transferred to the second storage circuit in the second half. .

By these operations, the digital video signal corresponding to each signal line is sequentially transferred to the second memory circuit group 103.

Although FIG. 1 shows an example in which two latch pulse lines are provided and the latch pulse is input 2n times [8 times] in one horizontal scanning period, the present invention is not limited to this configuration. All the second memory circuits (LAT2) may be connected to one latch pulse line. In this case, it is necessary to provide a blanking period each time the shift register 101 finishes scanning once, and to interrupt the writing of the digital video signal to the first memory circuit in the blanking period. Then, in the blanking period, all the first memory circuits (LAT
Transfer from 1) to all the second storage circuits (LAT2). Then, the latch pulse is input n times [4 times] in one horizontal scanning period.

The 3-bit digital video signal output from the second storage circuit (LAT2) is a D / A conversion circuit (D
AC) and converted into an analog video signal. Note that a buffer circuit, a level shift circuit, an enable circuit for limiting the output period, or the like may be provided between the second memory circuit and the D / A conversion circuit. The converted analog video signal is written to an appropriate signal line through the signal line selection circuit (SEL) included in the signal line selection circuit group 105.

The timing at which the analog video signal is written to the appropriate signal line by the signal line selection circuit (SEL) is determined by the timing at which the latch pulse is input. Corresponding to the shift register scanning n times in one horizontal scanning period, the second memory circuit repeats the memory operation n times as described above. Therefore, while the digital video signal corresponding to a certain signal line is stored in the second storage circuit, D
Writing must be completed by selecting the corresponding signal line for the analog video signal output from the / A conversion circuit (DAC).

Input of an analog video signal from the signal line selection circuit (SEL) to the signal line is performed by the signal line selection circuit (SEL).
It is performed in synchronization with the pulse of the selection signal input to. The pulse of the selection signal appears n times in one horizontal scanning period.

In the present invention, the order of inputting the analog video signals of the n signal lines is changed for each horizontal scanning period or for each of a plurality of horizontal scanning periods. The order of selecting the signal lines is the selection signal S input to the signal line selection circuit (SEL).
It is controlled by S1 to SS4 [SS1 to SSn].

The order of the signal lines for inputting the analog video signal may be random or may have a certain regularity. Further, the order does not have to be changed for every one horizontal scanning period, and the order may be changed for every two horizontal scanning periods or every other horizontal scanning period. For example,
The order may be changed for each frame period. However, it is important to set the number of horizontal scanning periods to such an extent that vertical stripes are less visible to the human eye. Since vertical stripes are hard to see when the frame frequency is increased, it is preferable to set the number of horizontal scanning periods in which the order is changed in consideration of the frame frequency.

Table 1 shows the order of selecting the signal lines of this embodiment.

[0044]

[Table 1]

When the signal lines are selected in the order shown in Table 1, the order in which the analog video signals are written in the pixels is
A schematic view is shown in FIG. For comparison, the general order in which analog video signals are written to pixels is shown in FIG.
A schematic view is shown in FIG.

As shown in FIG. 3A, when the signal lines are selected in the order shown in Table 1, the signal line to which the analog video signal is first written differs every horizontal scanning period. On the other hand, as shown in FIG. 3B, when the selection order of the signal lines is fixed, the analog video signal is always written to the same signal line first in each horizontal scanning period.

Therefore, in the driving method shown in Table 1, even if the potential of the signal line to which the video signal is first written changes,
Since the position in the horizontal direction of the pixel to which the modulated potential is written changes every one horizontal scanning period, it is difficult for the human eye to visually recognize vertical stripes. In the driving example of FIG. 3A, the signal line in which the analog video signal is first written is
It may be different for each of a plurality of horizontal scanning periods.

The order of selecting the signal lines of the present invention is not limited to the order shown in Table 1. It may have a certain regularity as shown in Table 1 or may be random. Table 2 shows an example of the signal line selection order of the present invention different from that of Table 1.

[0049]

[Table 2]

Unlike Table 1, in Table 2, the number of the signal line selected first is different every horizontal scanning period, and all the signal lines are always first in any horizontal scanning period. It is selected. In the above configuration, since the first selected period is provided in all the signal lines, vertical stripes are more difficult to be visually recognized even if the frame frequency is the same, as compared with the driving method in Table 1.

Further, the selection order of the signal lines may be changed for each horizontal scanning period or for each of a plurality of horizontal scanning periods, and the selection order of the signal lines may be changed for each frame period. For example, the signal lines may be selected in the order shown in Table 1 in the previous frame period, and the signal lines may be selected in the order shown in Table 2 in the next frame period. With this configuration, vertical stripes are more difficult to be visually recognized even if the frame frequency is the same, as compared with a driving method in which the order is simply changed for each horizontal scanning period.

In the embodiments of the present invention, a signal line drive circuit (so-called digital signal line drive circuit) that inputs a digital video signal and outputs an analog video signal corresponding to each signal line is shown as an example. However, the present invention is not limited to this. For example, a signal line drive circuit (so-called analog signal line drive circuit) that inputs an analog video signal and outputs an analog video signal corresponding to each signal line may be used.

With the above structure, the present invention can reduce the number of circuit elements in the signal line drive circuit to 1 / n of the conventional example. Further, since the positions of pixels having different gradations in the horizontal direction are changed, it is difficult for the human eye to visually recognize vertical stripes without changing the frame frequency.

In the above description of the embodiment,
Although the shift register is used as a circuit for controlling the first memory circuit, a decoder circuit may be used instead of the shift register. Further, the D / A conversion circuit is a lamp type D / A
A conversion circuit may be used. In that case, the number of D / A conversion circuits is not limited to k / n.

[0055]

EXAMPLES Examples of the present invention will be shown below.

(Embodiment 1) In this embodiment, a detailed configuration of a signal line selection circuit used in the image display device of the present invention will be described.

FIG. 4A shows a circuit diagram of the signal line selection circuit (SEL) of this embodiment. In the present embodiment, n is used as a parameter indicating the number of signal lines sharing one D / A conversion circuit. However, FIG. 4 shows a case where one DAC corresponds to four signal lines in order to simplify the description. In the following, n is used for general description, but specific numbers in the case of n = 4 are shown in [].

In this embodiment, the analog switch has a p-channel type transistor and an n-channel type transistor. However, the present invention is not limited to this, and may be an analog switch using only p-channel type transistors or an analog switch using only n-channel type transistors.

The signal line drive circuit (SEL) of this embodiment is
n [four] analog switches 400_1 to 400_
n [400_1 to 400_4]. A selection signal for controlling switching is input to each analog switch.

A selection signal for controlling switching is supplied to the analog switches 400_1 to 400_ through the selection signal line.
n [400_1 to 400_4]. A selection signal having a different potential is input to each analog switch, and a selection signal line is provided for each analog switch.

In this embodiment, the analog switch has a p-channel type transistor and an n-channel type transistor, and a signal obtained by inverting the polarity of the selection signal is also input to the analog switch. Therefore, in this embodiment, the selection signal SS
1 to SSn [SS1 to SS4] and signals SSb1 to SSbn [SSb1 to SSb] in which the polarities of the selection signals are inverted.
4] is input to each analog switch. In the present embodiment, signals in which the polarities of the selection signals are inverted are also collectively referred to as selection signals.

FIG. 4B shows the signal lines Si to S (i + n-).
1) A timing chart of a selection signal when [S (i + 3)] is selected is shown. Note that the selection signals SSb1 to SS
Since b4 only reverses the polarities of the selection signals SS1 to SS4, only the selection signals SS1 to SS4 are shown here.

In FIG. 4B, n [4] signal lines Si, S (i + 1), S (i +) connected to the same DAC are used.
2) and S (i + n-1) [S (i + 3)] are selected in the order shown in Table 1. The order of selecting the signal lines in this embodiment is not limited to the order shown in Table 1.

First, when the horizontal scanning period is started, the signal line Si is selected in synchronization with the pulses of the selection signals SS1 and SSb1. Then, the analog video signal output from the DAC is transmitted through the analog switch 400_1 to the signal line Si.
Entered in.

Similarly, the selection signals SS2 to SSn
[SS2-SS4], SSb2-SSbn [SS2-S
S4] of the signal lines S (i + 1) to
S (i + n-1) [S (i + 3)] is selected. Then, the analog video signal output from the DAC is input to the signal lines S (i + 1) to S (i + 3) via the analog switches 400_2 to 400_4 [400_n].

When one horizontal scanning period ends and the next horizontal scanning period starts, the selection signals SSn and SSbn are selected.
In synchronization with the pulse of [SS4, SSb4], the signal line S (i
+ N-1) [S (i + 3)] is selected. And D
The analog video signal output from the AC is transmitted through the analog switch 400_n [400_4] to the signal line S (i + n).
-1) is input to [S (i + 3)].

Similarly, the selection signals SS (n-1) to
SS1 [SS3 to SS1], SSb (n-1) to SSb
1 [SS (n-1) to SS1] in synchronization with the signal lines S (i + n-2) to Si [S (i + 2) to S.
i] is selected. The analog video signal output from the DAC is analog switch 400_ (n-1).
Signal lines S (i +) via [400_3] to 400_1
2) to Si are input.

As described above, the selection order of the signal lines can be controlled by the selection signal.

(Embodiment 2) In this embodiment, the configuration of the controller of the image display apparatus of the present invention for generating various signals related to driving will be described.

FIG. 5 is a block diagram showing the arrangement of the image display apparatus of this embodiment. Reference numeral 500 denotes a pixel portion, 501 denotes a signal line driving circuit, and 502 denotes a scanning line driving circuit. A signal line selection circuit group 503 is included in the signal line driver circuit 501.

A controller 504 has various circuits. Specifically, it mainly has a buffer 505, a display memory 506, a timing generation circuit 507, a selection circuit timing generation circuit 508, and a format circuit 509. In addition to this, a bias voltage generating circuit, a serial interface, and the like may be included.

The controller 504 mainly outputs the video signal (Vi
deo Signals) and a reference clock signal (Do
t CLK), the horizontal synchronization signal (Hsync), and the vertical synchronization signal (Vsync) are input.

The video signal is amplified or buffer-amplified in the buffer 505 and written in the display memory 506. Note that the video signal does not necessarily have to be amplified or buffer-amplified in the buffer 505, and the provision of the buffer 505 is not essential.

The reference clock signal, the horizontal synchronizing signal (Hsync) and the vertical synchronizing signal (Vsync) are input to the timing generation circuit 507. In this embodiment, the reference clock signal is input from outside the image display device, but the present embodiment is not limited to this configuration. The reference clock signal may be generated based on the horizontal synchronizing signal (Hsync) input to the image display device without being input from the outside.

The timing generation circuit 507 generates a signal for determining the operation timing of various circuits according to the input reference clock signal, horizontal synchronization signal (Hsync) and vertical synchronization signal (Vsync).

Specifically, the clock signal (S-CLK) and the start pulse signal (S) for the signal line drive circuit 501 are used.
-SP), a clock signal (G-CLK) and a start pulse signal (G-SP) for the scan line driver circuit 502.
Are generated in the timing generation circuit 507.

Further, the timing generation circuit 507 determines the timing of writing the video signal to the display memory 506 and the timing of inputting the video signal held by the display memory 506 to the format circuit 509.

The timing at which the signal lines are selected in the signal line selection circuit group 503 is determined by the timing generation circuit 5.
It is decided at 07. In addition, within each horizontal scanning period, n
Since the book signal line is selected, the signal line selection timing appears n times in each horizontal scanning period. However, n
Means the number of signal lines sharing one DAC.
A signal that determines the timing for selecting the signal line is input from the timing generation circuit 507 to the selection circuit timing generation circuit 508.

The selection circuit timing generation circuit 508
It has a selection signal generation circuit 510 for generating a selection signal and a selection order determination register 511 in which data of the selection order of signal lines is accumulated. The selection signal generation circuit 510 includes
From the timing generation circuit 507, a signal that determines the timing for selecting the signal line is input. Further, the selection signal generation circuit 510 is supplied with data in the selection order of the signal lines from the selection order determination register 511.

The selection signal generation circuit 510 generates selection signals SS1 to SSn based on the data in the selection order of the signal lines and the signal that determines the selection timing of the signal line that appears n times. For each of the selection signals SS1 to SSn, a pulse appears once within one horizontal scanning period. The signal line is selected in synchronization with the pulse.

On the other hand, the data of the selection order of the signal lines stored in the selection order determination register 511 is also sent to the format circuit 509. Then, the format circuit 509
The video signals input to are rearranged according to the data of the selection order of the signal lines, and input to the first memory circuit group (not shown) of the signal line driver circuit 501. The format unit 509 may serial-parallel convert the video signal to divide the video signal into a plurality of signals, and then input the video signals to the first storage circuit group (not shown).

In FIG. 5, the timing generation circuit 507
However, the selection circuit timing generation circuit 508 may be regarded as a part of the timing generation circuit 507. Although the display memory 506 is shown as a part of the controller 504 in FIG. 5, the display memory 506 may be separated from the controller 504.

Further, in FIG. 5, the display memory is connected only to the controller 504 and is independent of the system bus managed by the CPU (not shown), but this embodiment is not limited to this configuration. . CPU and controller 504
And may share the same display memory.

The signal line selection order data stored in the selection order determination register 511 may be fixed data determined by the design of a mask or the like, or CPU.
Alternatively, the data may be rewritable by a DIP switch or the like.

The configuration of this embodiment can be implemented by freely combining it with that of the first embodiment.

(Embodiment 3) In this embodiment, a specific configuration of the first and second memory circuits used in the signal line driver circuit of the present invention will be described.

A concrete example of the memory circuit is shown in FIG. Figure 6
6A is a clock type inverter, FIG. 6B is an SRAM type, and FIG. 6C is a DR.
It is of the AM type. These are representative examples and the invention is not limited to these formats.

The control signal 2 corresponds to a signal obtained by inverting the polarity of the control signal 1. In the case of the second memory circuit, a latch pulse is input to the control signal.

The structure of this embodiment can be implemented by being freely combined with Embodiment 1 or 2.

(Embodiment 4) In this embodiment, a configuration of a signal line drive circuit when a ramp type D / A conversion circuit is adopted as a D / A conversion circuit will be described.

FIG. 7 shows a schematic diagram of a signal line drive circuit in the case of using a lamp type D / A conversion circuit. Although the present embodiment describes a case in which an XGA standard image display device is compatible with a 3-bit digital video signal, the present invention is not limited to 3-bit, and a case in which any other number of bits is supported or a case other than XGA is used. It is also effective for standard image display devices.

In this embodiment, the shift register 70
1, first memory circuit group 702, second memory circuit group 70
3. The configuration and operation of the signal line selection circuit group 706 are the same as those in the embodiment. In this embodiment, the second memory circuit 703 is used.
This is different from the case of the embodiment in that a bit comparison pulse width conversion circuit group 704 and an analog switch group 705 are provided in the lower stage. Two circuits of the bit comparison pulse width conversion circuit group 704 and the analog switch group 705 function as a ramp type D / A conversion circuit.

In this embodiment, the bit comparison pulse width conversion circuit group includes 256 bit comparison pulse width conversion circuits (BP).
C) is provided. The BPC has a 3-bit digital video signal stored in the second storage circuit group 703,
The count signal (C0 to C2) and the set signal (ST) are input.

The analog switch group 705 is provided with 256 analog switches (ASW) in this embodiment. The analog switch group 705 has outputs from the bit comparison pulse width conversion circuit group 704 (PW-i and i are 001).
~ 256), the gradation power source (VR) is input. The output of the analog switch group 705 and selection signals (SS1 to SS4) are input to the signal line selection circuit group 706.

The structure of the i-th stage BPC is illustrated in FIG. BPC is an exclusive OR gate, a 3-input NAND gate, an inverter, a set-reset flip-flop (R
S-FF). In FIG. 8, the output of the second memory circuit in the i-th stage is L2-i (0), L2 by distinguishing bits.
-I (1) L2-i (2) (bit numbers in parentheses).

Next, the operation of the signal line drive circuit of this embodiment will be described. FIG. 9 shows a timing chart of the signal system necessary for understanding the outline of the circuit operation of FIG.
The operation from the shift register 701 to the second memory circuit group 703 is also the same as that of the signal line driver circuit described in the embodiment. The selection signals (SS1 to SS4) input to the signal line selection circuit group 706 are also shown in FIG.
This is the same as the case of the signal line drive circuit shown in.

In FIG. 9, every time four signal lines are sequentially selected by the signal line selection circuit group 706, the count signal (C0 to C2), the set signal (ST), and the gradation power supply (VR) are cycled. Input As a result, it is possible to equally write information on all the signal lines.

To explain the detailed operation of the ramp type D / A conversion circuit, FIG. 10 shows a timing chart during a period in which one of the four signal lines is selected by the signal line selection circuit.

First, R is synchronized with the pulse of the set signal.
The S-FF 30 is set, and the output PW-i becomes Hi level. Next, the digital video signal stored in the second memory circuit group 703 is compared with the count signal (C0 to C2) by the exclusive OR gate for each bit. Three
When all the bits match, the output of all the exclusive OR gates becomes Hi level, and as a result, the 3-input NA
The output of the ND gate (inverted RC-i) becomes Lo level (hence RC-i becomes Hi level). This 3
The output of the input NAND is also input to the RS-FF 30, and RC
-I is reset to Hi level and reset, and output PW-i
Returns to Lo level. In FIG. 10, a 3-bit digital video signal {L2-i (0), L2-i (1) L2-i.
RC-i for the case (2)} is {0, 0, 1},
Output examples of PW-i and DA-i are shown. In this way, the information of the digital video signal is converted into the pulse width of the output PW-i of the BPC.

The output PW-i of the BPC controls the opening / closing of the analog switch group 705. In this embodiment, the analog switch group 705 is turned on only while the BPC output PW-i is at the Hi level, and is turned off when PW-i is at the Lo level. A gradation power supply (VR) having a stepwise voltage level synchronized with the count signals (C0 to C2) is applied to the analog switch group 705, and the gradation power supply (VR) at the moment when PW-i becomes Lo level is applied. ) Is written in the signal line via the signal line selection circuit in the subsequent stage.

By the above operation, the digital video signal is converted into the analog video signal and the signal line is driven. The gradation power supply (VR) does not have to be stepwise, and may be continuously and monotonously changing. Further, a buffer circuit, a level shift circuit, or the like may be provided between the output of the bit comparison pulse width conversion circuit group 704 and the analog switch group 705.

As described above, in the present invention, the ramp type D / A conversion circuit can be used as the D / A conversion circuit,
The circuit configuration is only about 1/4 of the conventional one, and the area occupied by the drive circuit and the number of elements can be greatly reduced.

The structure of this embodiment can be implemented by freely combining with Embodiments 1 to 3.

(Embodiment 5) In this embodiment, a method for manufacturing an active matrix type liquid crystal display device will be taken as an example of a specific method for manufacturing the image display device of the present invention. In particular, here, the pixel TF which is the switching element of the pixel unit
A method of manufacturing T and a TFT of a driver circuit (a signal line driver circuit, a scanning line driver circuit, or the like) provided around the pixel portion over the same substrate will be described in detail in accordance with steps. However,
For simplification of description, a CMOS circuit, which is a basic constituent circuit of the drive circuit section, and an n-channel type TFT are shown as the pixel TFT section.

In FIG. 11A, a low alkali glass substrate or a quartz substrate can be used as the substrate (active matrix substrate) 6001. In this example, a low alkali glass substrate was used. In this case, heat treatment may be performed in advance at a temperature lower than the glass strain point by about 10 to 20 ° C. A base film 6002 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 6001 on which the TFT is formed in order to prevent the diffusion of impurities from the substrate 6001. For example, plasma C
A silicon oxynitride film made of SiH ₄ , NH ₃ , and N ₂ O is formed to a thickness of 100 nm by the VD method, and a silicon oxynitride film made of SiH ₄ and N ₂ O is also formed to a thickness of 200 nm.

Next, 20 to 150 nm (preferably 30 nm)
To 80 nm) and a semiconductor film 60 having an amorphous structure
03a is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film having a thickness of 54 nm is formed by the plasma CVD method. The semiconductor film having an amorphous structure includes an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied.
Further, since the base film 6002 and the amorphous silicon film 6003a can be formed by the same film formation method, both may be formed continuously. In that case, after forming the base film,
By not exposing it to the air atmosphere once, it becomes possible to prevent the surface from being contaminated, and it is possible to reduce the variations in the characteristics of the TFT to be manufactured and the variations in the threshold voltage (FIG. 11).
(A)).

Then, the amorphous silicon film 6003a to the crystalline silicon film 6003 are formed by using a known crystallization technique.
b is formed. For example, a laser crystallization method or a thermal crystallization method (solid-phase growth method) may be applied, but here, according to the technique disclosed in Japanese Patent Laid-Open No. 7-130652, crystallization is performed by a crystallization method using a catalytic element. Quality silicon film 6003b
Was formed. Prior to the crystallization process, it may be possible to perform heat treatment at 400 to 500 ° C. for about 1 hour to reduce the content of hydrogen to 5 atom% or less before crystallization, depending on the content of hydrogen in the amorphous silicon film. desirable. When the amorphous silicon film is crystallized, atoms are rearranged and become dense, so that the thickness of the produced crystalline silicon film is smaller than the initial thickness of the amorphous silicon film (54 nm in this embodiment). Also 1
It is reduced by about 15% (FIG. 11 (B)).

Then, the crystalline silicon film 6003b is patterned into an island shape to form island-shaped semiconductor layers 6004-60.
07 is formed. After that, a mask layer 6008 made of a silicon oxide film with a thickness of 50 to 150 nm is formed by a plasma CVD method or a sputtering method. (Fig. 11
(C)).

Then, a resist mask 6009 is provided, and n
Island-shaped semiconductor layer 6 for forming a channel type TFT
1 × 10 ^{16 to} 5 × 10 ¹⁷ atom on the entire surface of 005 to 6007
Boron (B) is added as an impurity element imparting p-type at a concentration of about s / cm ³ . The boron (B) is added for the purpose of controlling the threshold voltage. The boron (B) may be added by an ion doping method, or may be added at the same time when the amorphous silicon film is formed. The addition of boron (B) here is not always necessary (FIG. 11 (D)). After that, the resist mask 6009 is removed.

LDD region of n-channel TFT of drive circuit
In order to form a region, an impurity element imparting n-type is formed into an island shape.
It is selectively added to the semiconductor layers 6010 to 6012. That
Therefore, the resist masks 6013 to 6016 are previously formed.
Form. As the impurity element imparting n-type, phosphorus
(P) or arsenic (As) may be used.
To add (P), phosphine (PH₃) Was used
The ion doping method was applied. Impurity region 60 formed
The phosphorus (P) concentration of 17,6018 is 2 × 10¹⁶~ 5 x 1
0¹⁹atoms / cm³The range should be In this specification,
Included in the impurity regions 6017 to 6019 formed here
The concentration of the impurity element imparting n-type ^-) And table
You Further, the impurity region 6019 functions as a storage capacitor of the pixel portion.
It is a semiconductor layer for forming, and the same concentration is
Phosphorus (P) is added at (FIG. 12 (A)). After that,
The ghost masks 6013 to 6016 are removed.

Next, after removing the mask layer 6008 with hydrofluoric acid or the like, a step of activating the impurity element added in FIGS. 11D and 12A is performed. Activation is 5
It can be carried out by a heat treatment for 1 to 4 hours in a nitrogen atmosphere at 00 to 600 ° C. or a laser activation method.
Alternatively, both may be used together. In this embodiment, a laser activation method is used. K for laser light
rF excimer laser light (wavelength 248 nm) is used.
In this embodiment, the shape of the laser beam is processed into a linear beam and used, and the oscillation frequency is 5 to 50 Hz and the energy density is 10
The entire surface of the substrate on which the island-shaped semiconductor layer is formed is processed by scanning the linear beam with an overlap ratio of 0 to 500 mJ / cm ² at 80 to 98%. The conditions for irradiating the laser light are not limited in any way and can be appropriately determined.

Then, the gate insulating film 6020 is formed of an insulating film containing silicon with a thickness of 10 to 150 nm by a plasma CVD method or a sputtering method. For example, 12
A silicon oxynitride film is formed to a thickness of 0 nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a laminated structure. (Fig. 12 (B))

Next, a first conductive layer is formed to form a gate electrode. The first conductive layer may be formed of a single layer, but may have a laminated structure of two layers or three layers as required. In this embodiment, a conductive layer (A) 6021 made of a conductive nitride metal film and a conductive layer (B) 6022 made of a metal film are laminated. Conductive layer (B) 602
2 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the above element as a main component, or an alloy film (typically, a combination of the above elements). The conductive layer (A) 6021 is made of tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, or molybdenum nitride (MoN). Form. In addition, the conductive layer (A) 6021 is used as an alternative material.
Tungsten silicide, titanium silicide, or molybdenum silicide may be applied. The impurity concentration of the conductive layer (B) is preferably reduced in order to reduce the resistance, and particularly, the oxygen concentration is preferably 30 ppm or less. For example, tungsten (W) has an oxygen concentration of 30 pp
By setting it to be m or less, a specific resistance value of 20 μΩcm or less can be realized.

The conductive layer (A) 6021 has a thickness of 10 to 50 nm.
(Preferably 20 to 30 nm) and the conductive layer (B) 60
22 is 200 to 400 nm (preferably 250 to 350 nm)
nm). In this embodiment, the conductive layer (A) 60
21 was a tantalum nitride film having a thickness of 30 nm, and the conductive layer (B) 6022 was a Ta film having a thickness of 350 nm. In the film formation by this sputtering method, if an appropriate amount of Xe or Kr is added to Ar, which is a gas for sputtering, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, it is effective to form a silicon film doped with phosphorus (P) in a thickness of about 2 to 20 nm under the conductive layer (A) 6021. Accordingly, the adhesion of the conductive film formed thereon is improved and the oxidation is prevented, and at the same time, a small amount of the alkali metal element contained in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 6020. Can be prevented (FIG. 12 (C)).

Next, resist masks 6023-6027.
To form a conductive layer (A) 6021 and a conductive layer (B) 602
2 and are collectively etched to form gate electrodes 6028-60
31 and a capacitor wiring 6032 are formed. Gate electrode 602
8 to 6031 and the capacitor wiring 6032 are integrally formed of conductive layers (A) 6028a to 6032a and conductive layers (B) 6028b to 6032b. At this time, the gate electrode 6 of the TFT that constitutes the drive circuit
028 to 6030 are formed so as to overlap with part of the impurity regions 6017 and 6018 with the gate insulating film 6020 interposed therebetween (FIG. 12D).

Then, in order to form the source region and the drain region of the p-channel TFT of the driving circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity region is formed in a self-aligned manner using the gate electrode 6028 as a mask. At this time, the n-channel TFT
The region in which is formed is covered with a resist mask 6033. Then, the impurity region 6034 was formed by an ion doping method using diborane (B ₂ H ₆ ). The boron (B) concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . After that, the resist mask 6033 is removed. In this specification, the impurity region 6 formed here is used.
The concentration of the impurity element imparting p-type contained in 034 is represented by (p ⁺⁺ ) (FIG. 13A).

Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 6035 to 6037 were formed, and an impurity element imparting n-type was added to form impurity regions 6039 to 6042. This is performed by an ion doping method using phosphine (PH ₃ ), and the phosphorus (P) concentration in this region is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / c.
m ³ In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 6039 to 6042 formed here is expressed as (n ⁺ ) (FIG. 13B).

The impurity regions 6039 to 6042 already contain phosphorus (P) or boron (B) added in the previous step, but phosphorus (P) is added at a sufficiently higher concentration than that. Therefore, it is not necessary to consider the influence of phosphorus (P) or boron (B) added in the previous step.
The concentration of phosphorus (P) added to the impurity region 6038 is 1/2 of the concentration of boron (B) added in FIG.
Since it is ⅓, p-type conductivity is ensured and the characteristics of the TFT are not affected at all.

After removing the resist masks 6035 to 6037, an impurity adding step for imparting n-type for forming the LDD region of the n-channel TFT in the pixel portion was performed. Here, an impurity element imparting n-type in a self-aligning manner is added by an ion doping method using the gate electrode 6031 as a mask. The concentration of phosphorus (P) added is 1 × 10 ^{16 to} 5 ×
10 ¹⁸ atoms / cm ^3, which is shown in FIGS.
By adding at a concentration lower than that of the impurity element added in FIGS. 13A and 13B, the impurity region 60 is substantially added.
Only 43 and 6044 are formed. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 6043 and 6044 is represented by (n ⁻ ). (Fig. 13
(C))

Then, a heat treatment step is performed to activate the impurity element imparting n-type or p-type added at each concentration. This step is a furnace annealing method,
It can be performed by a laser annealing method or a rapid thermal annealing method (RTA method). Here, the activation process was performed by the furnace annealing method. The heat treatment is performed at 400 to 800 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, typically 500 to 60.
The heat treatment is performed at 0 ° C., and in this embodiment, the heat treatment is performed at 500 ° C. for 4 hours. Further, when a substrate having heat resistance such as a quartz substrate is used as the substrate 6001, 800
The heat treatment may be performed at 1 ° C. for 1 hour, so that the activation of the impurity element and the junction between the impurity region to which the impurity element is added and the channel formation region can be favorably formed. In addition,
This effect may not be obtained when an interlayer film is formed to prevent peeling of Ta that is the gate electrode.

In this heat treatment, the gate electrode 6028
To 6031 and the metal film 602 forming the capacitor wiring 6032.
8b to 6032b, conductive layers (C) 6028c to 6032c are formed with a thickness of 5 to 80 nm from the surface. For example, when the conductive layers (B) 6028b to 6032b are tungsten (W), tungsten nitride (WN) is formed, and when the conductive layers (B) 6028b to 6032b are tantalum (Ta), tantalum nitride (Ta) is formed.
N) can be formed. In addition, the conductive layer (C) 60
28c to 6032c are gate electrodes 6028 to 6028 in a plasma atmosphere containing nitrogen using nitrogen or ammonia.
The same can be formed by exposing 6031 and the capacitor wiring 6032. Further, heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing hydrogen of 3 to 100% to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating the dangling bond of the semiconductor layer by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma or hydrogen plasmatized) may be performed.

The island-shaped semiconductor layer is touched by the amorphous silicon film.
When made by the crystallization method using a medium element, the island-shaped half
A trace amount of catalytic element remained in the conductor layer. Of course
It is possible to complete the TFT even in such a state,
Remove residual catalytic elements from at least the channel formation region.
It was better to leave. Remove this catalytic element
Utilizing the gettering action by phosphorus (P) as one of the means
There was a way to do it. Of phosphorus (P) necessary for gettering
The concentration is the impurity region (n ⁺Same as
The heat treatment of the activation process performed here is
Of the n-channel TFT and p-channel TFT
It is possible to getter the catalytic element from the channel formation region.
It was possible (FIG. 13 (D)).

When the activation and hydrogenation steps are complete,
A second conductive film to be a gate wiring (scanning line) is formed.
This second conductive film is made of aluminum (A
l) or a conductive layer (D) containing copper (Cu) as a main component and a conductive layer (E) made of titanium (Ti), tantalum (Ta), tungsten (W), or molybdenum (Mo). good. In the present embodiment, titanium (Ti) is added to 0.
An aluminum (Al) film containing 1 to 2% by weight is used as the conductive layer (D) 6045, and a titanium (Ti) film is used as the conductive layer (E).
Formed as 6046. The conductive layer (D) 6045 is 20
The thickness may be 0 to 400 nm (preferably 250 to 350 nm), and the conductive layer (E) 6046 may be 50 to 200 (preferably 100 to 150 nm). (Fig. 1
4 (A))

Then, the conductive layer (E) 6046 and the conductive layer (D) 6045 are etched to form gate wirings (scanning lines) connected to the gate electrodes, and gate wirings (scanning lines) 6047 and 6048. A capacitor wiring 6049 was formed. The etching treatment is first performed by dry etching using a mixed gas of SiCl ₄ , Cl ₂ and BCl ₃ to remove from the surface of the conductive layer (E) to the middle of the conductive layer (D).
After that, the conductive layer (D) was removed by wet etching with a phosphoric acid-based etching solution, whereby the gate wiring (scanning line) could be formed while maintaining the selective workability with the base.

The first interlayer insulating film 6050 is 500 to 15
A contact hole reaching a source region or a drain region formed in each island-shaped semiconductor layer is formed with a silicon oxide film or a silicon oxynitride film with a thickness of 00 nm, and source wiring (signal line) 6051 to
6054 and drain wirings 6055 to 6058 are formed. Although not shown, in this embodiment, this electrode is
The film is 100 nm, and the aluminum film containing Ti is 300 n
m and a Ti film having a thickness of 150 nm were continuously formed by a sputtering method to form a laminated film having a three-layer structure.

Next, as the passivation film 6059, a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is 50 to 500 nm (typically 100 to 3).
It is formed with a thickness of 00 nm). When hydrogenation treatment is performed in this state, favorable results are obtained for improving the characteristics of the TFT. For example, in an atmosphere containing 3 to 100% hydrogen,
The same effect can be obtained by performing heat treatment at 300 to 450 ° C. for 1 to 12 hours, or by using the plasma hydrogenation method. Note that an opening may be formed in the passivation film 6059 at a position where a contact hole for connecting the pixel electrode and the drain wiring will be formed later. (Figure 14 (C))

Then, a second interlayer insulating film 6060 made of organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide,
Polyimide amide, BCB (benzocyclobutene), etc. can be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate is used, and is baked at 300 ° C. Then, a contact hole reaching the drain wiring 6058 is formed in the second interlayer insulating film 6060, and pixel electrodes 6061 and 6062 are formed. For the pixel electrode, a transparent conductive film may be used in the case of a transmissive liquid crystal display device, and a metal film may be used in the case of a reflective liquid crystal display device. In this embodiment, an indium tin oxide (ITO) film having a thickness of 100 n is used to form a transmissive liquid crystal display device.
The thickness of m was formed by the sputtering method. (Figure 15)

Thus, the TFT of the drive circuit is formed on the same substrate.
It was possible to complete the substrate having the pixel TFT of the pixel portion. The drive circuit includes a p-channel TFT 6101,
A first n-channel TFT 6102, a second n-channel TFT 6103, a pixel TFT 6104 and a storage capacitor 6105 were formed in the pixel portion. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the p-channel TFT 6101 of the driver circuit, the channel formation region 610 is formed in the island-shaped semiconductor layer 6004.
6, source regions 6107a and 6107b, and drain regions 6108a and 6108b. In the first n-channel TFT 6102, an L-shaped semiconductor layer 6005 is overlapped with a channel formation region 6109 and a gate electrode 6029.
DD area 6110 (hereinafter, such an LDD area is referred to as Lov
Source region 6111 and drain region 6112.
have. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm. The second n-channel TFT 6103 has a channel formation region 6113, LDD regions 6114 and 6115, a source region 6116, and a drain region 6117 in the island-shaped semiconductor layer 6006. This LDD region is an LDD region that does not overlap the Lov region and the gate electrode 6030 (hereinafter,
Such an LDD region is referred to as Loff) is formed,
The length of this Loff region in the channel length direction is 0.3 to 2.
It is 0 μm, preferably 0.5 to 1.5 μm. Pixel T
In the FT 6104, the island-shaped semiconductor layer 6007 has channel formation regions 6118 and 6119 and Loff regions 6120 to 61.
23, and has source or drain regions 6124 to 6126. The length of the Loff region in the channel length direction is 0.
It is 5 to 3.0 μm, preferably 1.5 to 2.5 μm. Furthermore, the capacitor wirings 6032 and 6049, an insulating film made of the same material as the gate insulating film, and the pixel TFT 6104.
Of the semiconductor layer 6127 to which the impurity element imparting n-type is added and which is connected to the drain region 6126 of the storage capacitor 6
105 is formed. In FIG. 15, the pixel TFT 610 is shown.
Although 4 has a double gate structure, it may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

As described above, in this embodiment, the structure of the TFTs forming each circuit is optimized in accordance with the specifications required by the pixel TFT and the driving circuit, and the operation performance and reliability of the image display device are improved. It can be possible.

Next, a process of manufacturing a transmissive liquid crystal display device based on the active matrix substrate manufactured by the above process will be described.

Referring to FIG. An alignment film 6201 is formed on the active matrix substrate in the state of FIG. In this embodiment, polyimide is used for the alignment film 6201. Next, a counter substrate is prepared. The counter substrate is a glass substrate 62.
02, a light-shielding film 6203, and a counter electrode 6 made of a transparent conductive film.
And an alignment film 6205.

In this embodiment, the alignment film is a polyimide film in which liquid crystal molecules are aligned in parallel with the substrate. After forming the alignment film, a rubbing process was performed so that the liquid crystal molecules were aligned in parallel with a certain pretilt angle.

Next, the active matrix substrate and the counter substrate which have undergone the above steps are subjected to a known cell assembling step.
It attaches via a sealing material and a spacer (both are not shown). After that, liquid crystal 6206 is injected between both substrates and completely sealed with a sealant (not shown). Thus, the transmissive liquid crystal display device as shown in FIG. 16 is completed.

A TFT manufactured by the above process
Is a top gate structure, but a bottom gate structure TF
The present invention can be applied to TFTs having T and other structures.

Although the image display device produced by the above process is a transmissive liquid crystal display device, the present invention can be applied to a reflective liquid crystal display device.

The structure of this embodiment can be implemented by freely combining with Embodiments 1 to 4.

(Embodiment 6) As electronic equipment using the image display device of the present invention, a video camera, a digital camera, a goggle type display (head mount display), a navigation system, a sound reproducing device (car audio system, audio component system, etc.) , Notebook personal computers, game machines, personal digital assistants (mobile computers, mobile phones, portable game machines, electronic books, etc.), image reproducing devices equipped with recording media (specifically, digital video discs (DVDs), etc.) Play the recording medium,
A device including a display capable of displaying the image) and the like. Specific examples of these electronic devices are shown in FIGS.

FIG. 17A shows a liquid crystal display device, which includes a housing 2001, a supporting base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The image display device of the present invention can be used for the display portion 2003. The liquid crystal display device includes all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.

FIG. 17B shows a digital still camera including a main body 2101, a display portion 2102, an image receiving portion 2103,
An operation key 2104, an external connection port 2105, a shutter 2106 and the like are included. The image display device of the present invention includes the display unit 2.
102 can be used.

FIG. 17C shows a laptop personal computer, which has a main body 2201, a housing 2202, and a display section 2.
203, keyboard 2204, external connection port 220
5, including a pointing mouse 2206 and the like. The image display device of the present invention can be used for the display portion 2203.

FIG. 17D shows a mobile computer, which has a main body 2301, a display portion 2302, and a switch 230.
3, an operation key 2304, an infrared port 2305 and the like. The image display device of the present invention can be used for the display portion 2302.

FIG. 17E shows a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a casing 2402, a display portion A2403, a display portion B2404, a recording medium ( DVD, etc.) reading unit 240
5, an operation key 2406, a speaker portion 2407, and the like. The display unit A2403 mainly displays image information, and the display unit B2404 mainly displays character information. However, the image display device of the present invention has these display units A, B2403, and 24.
04 can be used. Note that the image reproducing device provided with the recording medium includes a home game machine and the like.

FIG. 17F shows a goggle type display (head mounted display), which is a main body 250.
1, a display portion 2502 and an arm portion 2503 are included. The image display device of the present invention can be used for the display portion 2502.

FIG. 17G shows a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, and an image receiving portion 260.
6, a battery 2607, a voice input unit 2608, operation keys 2609, and the like. The image display device of the present invention includes the display unit 2.
602 can be used.

[0146] Here, FIG. 17H shows a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, a voice input portion 2704, a voice output portion 2705, operation keys 2706,
An external connection port 2707, an antenna 2708, and the like are included.
The image display device of the present invention can be used for the display portion 2703.

Next, a projector (rear type or front type) using the image display device of the present invention will be described. Examples of these are shown in FIGS. 18 and 19.

FIG. 18A shows a front type projector, which includes a light source optical system, a display portion 7601, and a screen 7.
602. The present invention can be applied to the display portion 7601.

FIG. 18B shows a rear type projector, which is composed of a main body 7701, a light source optical system and display portion 7702, a mirror 7703, a mirror 7704, and a screen 7705. The present invention can be applied to the display portion 7702.

Note that FIG. 18C shows the light source optical system and the display section 760 in FIGS. 18A and 18B.
It is the figure which showed an example of the structure of 1,7702. The light source optical system and display portions 7601 and 7702 are the light source optical system 780.
1, mirrors 7802, 7804 to 7806, dichroic mirror 7803, optical system 7807, display unit 780
8, a retardation plate 7809, and a projection optical system 7810. The projection optical system 7810 is composed of a plurality of optical lenses including a projection lens. This configuration has a display portion 7808.
It is called three-plate type because it uses three. Also,
The practitioner may appropriately provide an optical lens, a film having a polarization function, a film for adjusting the phase difference, an IR film, or the like in the optical path indicated by the arrow in FIG. 18C.

Further, FIG. 18D is a diagram showing an example of the structure of the light source optical system 7801 in FIG. 18C. In this embodiment, the light source optical system 7801 includes a reflector 7811, a light source 7812, lens arrays 7813, 7
814, a polarization conversion element 7815, and a condenser lens 7816. Note that the light source optical system shown in FIG. 18D is an example, and the present invention is not limited to this configuration. For example, the practitioner may appropriately provide an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like in the light source optical system.

FIG. 18C shows an example of a three-plate type, whereas FIG. 19A shows an example of a single-plate type. FIG. 19
The light source optical system and the display unit shown in FIG.
901, a display portion 7902, a projection optical system 7903, and a retardation plate 7904. The projection optical system 7903 is composed of a plurality of optical lenses including a projection lens. FIG. 19
The light source optical system and the display unit shown in FIG. 18A are the light source optical system and the display unit 760 in FIGS. 18A and 18B.
1,7702 can be applied. Also, the light source optical system 7901
May use the light source optical system shown in FIG. Note that the display portion 7902 is provided with a color filter (not shown) so that a display image is colorized.

The light source optical system and display section shown in FIG. 19B is an application example of FIG. 19A. Instead of providing a color filter, an RGB rotating color filter disk 7905 is used. The display image is colorized.
The light source optical system and the display unit shown in FIG.
It can be applied to the light source optical system and the display portions 7601 and 7702 in (A) and FIG.

The light source optical system and the display section shown in FIG. 19C are called a color filterless single plate type. In this system, a microlens array 7915 is provided on the display portion 7916, and a dichroic mirror (green) 791
2. A display image is colorized using a dichroic mirror (red) 7913 and a dichroic mirror (blue) 7914. The projection optical system 7917 is composed of a plurality of optical lenses including a projection lens. The light source optical system and the display portion shown in FIG. 19C are shown in FIGS. 18A and 18B.
It can be applied to the light source optical system and the display portions 7601 and 7702 in the inside. Further, as the light source optical system 7911, an optical system using a coupling lens and a collimator lens in addition to the light source may be used.

As described above, the applicable range of the image display device of the present invention is extremely wide, and the image display device of the present invention can be applied to electronic devices in all fields. Further, the electronic device of the present embodiment can be realized by using any configuration of the first to fifth embodiments.

[0156]

According to the present invention, with the above configuration, the number of circuit elements in the signal line drive circuit can be reduced to 1 / n of the conventional example. Therefore, the area of the signal line driver circuit can be significantly reduced, which is effective for downsizing the image display device.
This is effective in reducing the cost and improving the yield of the image display device. Further, since the positions of pixels having different gradations in the horizontal direction are changed, it is difficult for the human eye to visually recognize vertical stripes without changing the frame frequency.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a signal line driver circuit of the present invention.

FIG. 2 is a diagram showing a timing chart of a signal line driver circuit of the present invention.

FIG. 3 is a schematic diagram showing the order of inputting analog video signals to pixels.

4A and 4B are a circuit diagram and a timing chart of a signal line selection circuit.

FIG. 5 is a block diagram of an image display device of the present invention.

FIG. 6 illustrates a specific example of a memory circuit.

FIG. 7 is a diagram showing a configuration of a signal line driver circuit of the present invention.

FIG. 8 is a diagram showing a configuration of a bit comparison pulse width conversion circuit (BPC).

9 is a diagram showing a timing chart of the drive circuit in FIG.

FIG. 10 is a diagram illustrating an operation of a ramp type D / A conversion circuit.

FIG. 11 is a diagram showing an example of a manufacturing process of an active matrix liquid crystal display device according to a third embodiment.

FIG. 12 is a diagram showing an example of a manufacturing process of an active matrix liquid crystal display device according to a third embodiment.

FIG. 13 is a diagram showing an example of a manufacturing process of an active matrix liquid crystal display device according to a third embodiment.

FIG. 14 is a diagram showing an example of a manufacturing process of an active matrix type liquid crystal display device according to a third embodiment.

FIG. 15 is a diagram showing an example of a manufacturing process of an active matrix type liquid crystal display device according to a third embodiment.

FIG. 16 is a diagram showing an example of a manufacturing process of an active matrix liquid crystal display device according to a third embodiment.

FIG. 17 is a diagram showing an example of an electronic device using the present invention.

FIG. 18 is a diagram showing a configuration of a projection type liquid crystal display device.

FIG. 19 is a diagram showing a configuration of a projection type liquid crystal display device.

FIG. 20 is a configuration diagram of an active matrix liquid crystal display device.

FIG. 21 is a configuration diagram of a conventional digital signal line drive circuit.

FIG. 22 is a timing chart of a conventional digital signal line drive circuit.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 623G 623V (72) Inventor Yasushi Kubota 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka No. 22 within Sharp Co., Ltd. (72) Inventor Hajime Washio 22-22 Nagaike-cho, Abeno-ku, Osaka City, Osaka Prefecture (Reference) 2H092 KA03 KA04 PA06 2H093 NB07 NC11 NC22 NC24 NC26 NC34 ND42 ND49 5C006 AA01 AC21 AF43 AF82 BB16 BC12 BC16 BC23 BF03 BF04 BF24 BF26 BF27 BF34 EB05 FA41 FA52 5C080 AA10 BB05 DD22 DD27 EE29 FF11 JJ02 JJ03 JJ04 JJ06 KK02 KK07 KK43 KK47

Claims (34)

[Claims] 1. An image display device having a signal line drive circuit and n × k (n and k are natural numbers) signal lines, wherein the signal line drive circuit has the n × k signals. An image display device, comprising: a signal line selection circuit for selecting k lines each for inputting an analog video signal, wherein a selection order of the n × k signal lines is variable. 2. The signal line selection circuit according to claim 1, wherein the signal line selection circuit has an analog switch, and an order in which the n × k signal lines are selected is determined by a selection signal input to the analog switch. An image display device characterized by the above. 3. A signal line drive circuit, a controller, and n ×
An image display device having k signal lines (n and k are both natural numbers), wherein the signal line drive circuit selects k of the n × k signal lines and inputs an analog video signal. The signal line selection circuit for selecting the n × k signal lines is different from each other in a horizontal scanning period that appears consecutively, and the n × k signal lines are selected. The image display device is characterized in that the order of turning is determined by a selection signal generated in the controller. 4. A signal line drive circuit, a controller, and n ×
An image display device having k signal lines (n and k are both natural numbers), wherein the signal line drive circuit selects k of the n × k signal lines and inputs an analog video signal. The selection order of the n × k signal lines is different from each other in consecutively appearing frame periods, and the n × k signal lines are selected. The image display device, wherein the order is determined by a selection signal generated in the controller. 5. A signal line drive circuit, a controller, and n ×
An image display device having k signal lines (n and k are both natural numbers), wherein the signal line drive circuit selects k of the n × k signal lines and inputs an analog video signal. The selection order of the n × k signal lines is different from each other in consecutive horizontal scanning periods, and the n × k signal lines are selected. The order in which the n × k signal lines are selected is different from each other in consecutively appearing frame periods, and the order in which the n × k signal lines are selected is determined by a selection signal generated in the controller. Image display device. 6. A signal line drive circuit, a controller, and n ×
An image display device having k signal lines (n and k are both natural numbers), wherein the signal line drive circuit selects k of the n × k signal lines and inputs an analog video signal. The signal line selection circuit for selecting the n × k signal lines is different from each other in a horizontal scanning period that appears consecutively, and the n × k signal lines are selected. The order in which the n × k signal lines are selected is stored as data in a register included in the controller, and the order in which the n × k signal lines are selected is selected by the controller according to the data stored in the register. An image display device characterized by being determined by. 7. A signal line drive circuit, a controller, and n ×
An image display device having k signal lines (n and k are both natural numbers), wherein the signal line drive circuit selects k of the n × k signal lines and inputs an analog video signal. The signal line selection circuit has an analog switch, and the order in which the n × k signal lines are selected is different from each other in the horizontal scanning period that appears consecutively. The order in which the n × k signal lines are selected is determined by a selection signal generated in the controller, and the selection signal is input to the analog switch. apparatus. 8. A signal line drive circuit, a controller, and n ×
An image display device having k signal lines (n and k are both natural numbers), wherein the signal line drive circuit selects k of the n × k signal lines and inputs an analog video signal. The signal line selection circuit has an analog switch, and the order in which the n × k signal lines are selected is different from each other in the horizontal scanning period that appears consecutively. The order in which the n × k signal lines are selected is stored as data in a register included in the controller, and the order in which the n × k signal lines are selected is stored in the register. The image display device is characterized in that it is determined by a selection signal generated in the controller according to the stored data, and the selection signal is input to the analog switch. 9. A signal line drive circuit, a controller, and n ×
An image display device having k signal lines (n and k are both natural numbers), wherein the signal line drive circuit selects k of the n × k signal lines and inputs an analog video signal. A signal line selection circuit for selecting the signal line selected from among the n × k signal lines, the signal line selected first in one horizontal scanning period is different in the horizontal scanning periods that appear consecutively. The image display device, wherein the order in which the × k signal lines are selected is determined by a selection signal generated in the controller. 10. A signal line drive circuit, a controller, and n.
An image display device having × k (n and k are both natural numbers) signal lines, wherein the signal line drive circuit selects k × n number of the signal lines for each analog video signal. A signal line selection circuit for inputting, wherein among the n × k signal lines, a signal line selected first in one horizontal scanning period is different in a horizontal scanning period that appears consecutively, The order in which the n × k signal lines are selected is stored as data in the register included in the controller, and the order in which the n × k signal lines are selected is the data stored in the register. According to the above, the image display device is determined by the selection signal generated in the controller. 11. A signal line drive circuit, a controller, and n.
An image display device having × k (n and k are both natural numbers) signal lines, wherein the signal line drive circuit selects k × n number of the signal lines for each analog video signal. A signal line selection circuit for inputting, and the order of selecting the n × k signal lines in one horizontal scanning period among the n × k signal lines is random in each horizontal scanning period. The image display device is different in that the order in which the n × k signal lines are selected is determined by a selection signal generated in the controller. 12. A signal line drive circuit, a controller, and n.
An image display device having × k (n and k are both natural numbers) signal lines, wherein the signal line drive circuit selects k × n number of the signal lines for each analog video signal. A signal line selection circuit for inputting, and the order of selecting the n × k signal lines in one horizontal scanning period among the n × k signal lines is random in each horizontal scanning period. The order in which the n × k signal lines are selected is stored as data in a register included in the controller, and the order in which the n × k signal lines are selected is different in the register. An image display device characterized by being determined by a selection signal generated in the controller according to stored data. 13. The image according to claim 9, wherein the signal line selection circuit has an analog switch, and the selection signal is input to the analog switch. Display device. 14. The D according to claim 1, wherein a digital video signal is converted into the analog video signal.
An image display device having an A / A conversion circuit. 15. A signal line drive circuit, a controller, and n.
An image display device having × k (n and k are both natural numbers) signal lines, wherein the signal line drive circuit stores a m-bit (m is a natural number) digital video signal. A second memory circuit for storing an output signal of the first memory circuit;
D that converts the output signal of the memory circuit of to the analog video signal
An A / A conversion circuit, and a signal line selection circuit that selects k of the n × k signal lines and inputs the analog video signal, the first storage circuit and the second storage circuit , M × k, and the selection order of the n × k signal lines is different from each other in the horizontal scanning period that appears continuously, and the n × k signal lines are selected. The image display device according to claim 1, wherein the order to be performed is determined by a selection signal generated in the controller. 16. A signal line drive circuit, a controller, and n.
An image display device having × k (n and k are both natural numbers) signal lines, wherein the signal line drive circuit stores a m-bit (m is a natural number) digital video signal. A second memory circuit for storing an output signal of the first memory circuit;
D that converts the output signal of the memory circuit of to the analog video signal
An A / A conversion circuit, and a signal line selection circuit that selects k of the n × k signal lines and inputs the analog video signal, the first storage circuit and the second storage circuit Of the n × k signal lines, the signal line selected first in one horizontal scanning period is different in consecutive horizontal scanning periods. The image display device, wherein the order of selecting n × k signal lines is determined by a selection signal generated in the controller. 17. A signal line drive circuit, a controller, and n.
An image display device having × k (n and k are both natural numbers) signal lines, wherein the signal line drive circuit stores a m-bit (m is a natural number) digital video signal. A second memory circuit for storing an output signal of the first memory circuit;
D that converts the output signal of the memory circuit of to the analog video signal
An A / A conversion circuit, and a signal line selection circuit that selects k of the n × k signal lines and inputs the analog video signal, the first storage circuit and the second storage circuit Is m × k, and the order in which the n × k signal lines are selected from the n × k signal lines in one horizontal scanning period is random in each horizontal scanning period. The image display device is different in that the order in which the n × k signal lines are selected is determined by a selection signal generated in the controller. 18. The method according to any one of claims 15 to 17.
The image display device according to the item 1, wherein the first memory circuit and the second memory circuit are latches. 19. The image display device according to claim 18, wherein the latch includes an analog switch and a storage capacitor. 20. The image display device according to claim 18, wherein the latch comprises a clocked inverter. 21. The image display device according to claim 18, wherein the latch includes an analog switch and a plurality of inverters. 22. Any one of claims 14 to 21.
The image display device according to the item 1, wherein the D / A conversion circuit is a lamp type D / A conversion circuit. 23. The image display device according to claim 1, wherein the signal line drive circuit is composed of a polysilicon thin film transistor. 24. The image display device according to claim 1, wherein the signal line drive circuit is composed of a single crystal transistor. 25. An electronic device using the image display device according to claim 1. 26. A method of driving an image display device for displaying an image by an analog video signal, wherein the analog video signals are all n × k (n and k are natural numbers) in one horizontal scanning period. Driving of an image display device, characterized in that k lines are sequentially input to signal lines and the order of selecting the n × k signal lines is different in two consecutive horizontal scanning periods. Method. 27. A driving method of an image display device for displaying an image by an analog video signal, wherein the analog video signals are all n × k (n and k are natural numbers) in one horizontal scanning period. A method for driving an image display device, characterized in that the order of inputting k lines to signal lines in order and selecting the n × k signal lines is different from each other in two consecutive frame periods. . 28. A driving method of an image display device for displaying an image by an analog video signal, wherein the analog video signals are all n × k (n and k are natural numbers) in one horizontal scanning period. The order of inputting k lines to the signal lines in order and selecting the n × k signal lines is different in two consecutive horizontal scanning periods, and the n × k signal lines are input. The driving method of the image display device, wherein the selection order is different from each other in two consecutive frame periods. 29. A method of driving an image display device for displaying an image by an analog video signal, wherein the analog video signals are all n × k (n and k are natural numbers) in one horizontal scanning period. The k signal lines are sequentially input to the signal lines, and the signal line selected first in one horizontal scanning period among the n × k signal lines is different from each other in two consecutive horizontal scanning periods. A method for driving an image display device, characterized in that 30. A method of driving an image display device for displaying an image by an analog video signal, wherein all of the analog video signals are n × k (n and k are natural numbers) in one horizontal scanning period. K lines are sequentially input to the signal lines, and among the n × k signal lines, the n × k signal lines are selected at random in each horizontal scanning period in one horizontal scanning period. A method for driving an image display device, which is characterized by being changed. 31. Any one of claims 26 to 30.
In the item, the order in which the n × k signal lines are selected is determined by a selection signal generated by a controller. 32. Any one of claims 26 to 30.
In the item, the order in which the n × k signal lines are selected is determined by a selection signal generated in the controller in accordance with data stored in a register included in the controller. Driving method of display device. 33. Any one of claims 26 to 30.
In the section, the order in which the n × k signal lines are selected is that the selection signal generated in the controller is set to the analog switch included in the signal line selection circuit according to the data stored in the register included in the controller. A method for driving an image display device, which is determined by being input. 34. Any one of claims 26 to 33.
Item 3. A driving method of an image display device, wherein the analog video signal is obtained by converting a digital video signal by a D / A conversion circuit.