JP2006154808A - Liquid crystal display device, projector device, mobile terminal device, and driving method of liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate unevenness in longitudinal stripes accompanying time-division writing as to a liquid crystal display device and a driving method thereof that write a video signal of one pixel line on a time-division basis, and a projector device and a mobile terminal device mounted with the liquid crystal display device. <P>SOLUTION: Order of pulses applied to control lines SP1 to SP3 within a horizontal period are applied in different for each horizontal period or each vertical period, and a data driver circuit 3 writes signals to data lines D within the horizontal period in different order for each horizontal period or each vertical period. Consequently, potential variation of the data lines caused during sampling is made temporally uniform to make longitudinally striped unevenness hard to view. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a liquid crystal display device that writes a video signal of one pixel row in a time-sharing manner, a driving method thereof, a projector device on which the liquid crystal display device is mounted, and a portable terminal device.

  A liquid crystal projector having three liquid crystal display devices corresponding to the three primary colors of red (R), green (G), and blue (B) can display a high-brightness, high-definition, large-screen image. , Has become the mainstream of projectors. In general, a liquid crystal display device used in such a liquid crystal projector uses a monochrome display liquid crystal display device having a display screen diagonal of 2 inches or less in order to reduce the size and cost of the device. In particular, a liquid crystal display device using a P-Si (polysilicon) -TFT (Thin Film Transistor) as a pixel transistor formed in each pixel has a high mobility of the P-Si-TFT. A part of the circuit can be formed using TFTs on the same glass substrate as the pixel. Thereby, the liquid crystal display device provided with the P-Si-TFT can be miniaturized and the interface can be simplified. Therefore, the liquid crystal display device for projectors has become the mainstream. One of the driving methods for such a liquid crystal display device is a block division driving method (see, for example, Patent Document 1). The block division driving method is a method in which a plurality of data lines of a liquid crystal display device are grouped into a plurality of blocks (groups), and video signals are written in units of blocks.

  FIG. 28 is a block diagram showing a conventional liquid crystal display device using P-Si-TFT. As shown in FIG. 28, in this liquid crystal display device, a TFT side glass substrate (not shown) and a counter side glass substrate (not shown) are provided in parallel to each other, and a liquid crystal layer is provided between the two substrates. (Not shown) is arranged. As shown in FIG. 28, data lines D1 to D9 (also collectively referred to as data lines D) extending in the row direction, that is, the vertical direction shown in the figure, are provided on the TFT side glass substrate. On the glass substrate, gate lines G1 to G6 (also collectively referred to as data lines G) extending in the column direction, that is, in the illustrated horizontal direction are provided. A pixel is formed at each closest point between the data lines D1 to D9 and the gate lines G1 to G6. That is, a plurality of pixels are arranged in a matrix.

  Each pixel is provided with one pixel thin film transistor TFT, a storage capacitor Cs, and a pixel electrode Ep. One of the source and drain of the pixel thin film transistor TFT is connected to the data line D, the other is connected to one electrode of the storage capacitor Cs and the pixel electrode Ep, and the gate is connected to the gate line G. A ground potential is applied to the other electrode of the storage capacitor Cs. Further, a counter electrode Eo is provided at a position corresponding to each pixel on the counter side glass substrate, and a pixel capacitor Clc is formed between the pixel electrode Ep and the counter electrode Eo.

  In addition, a data driver circuit 101 that drives the data line D and a gate driver circuit 102 that drives the gate line G are formed outside a region where a plurality of pixels are formed on the TFT side glass substrate. In the data driver circuit 101, a shift register 103 and analog switches SW1-1 to SW3-3 (hereinafter also collectively referred to as ASW) are provided. Each data line D is connected to one of the video signal lines V1 to V3 via the ASW. Specifically, the data line D1 is connected to the video signal line V1 via the switch SW1-1, and the data line D2 is connected to the video signal line V2 via the switch SW1-2. The data line D3 is connected to the video signal line V3 via the switch SW1-3, and the data line D4 is connected to the video signal line V1 via the switch SW2-1. The data line D5 is connected to the video signal line V2 via the switch SW2-2, and the data line D6 is connected to the video signal line V3 via the switch SW2-3. The data line D7 is connected to the video signal line V1 via the switch SW3-1, and the data line D8 is connected to the video signal line via the switch SW3-2. It is adapted to be connected to two data lines D9 is adapted to be connected to the video signal line V3 via the switch SW3-3.

  A plurality of, for example, three data lines D adjacent to each other form a block, and the ASWs in the same block are controlled by the same control signal. FIG. 28 shows an example in which three data lines belong to one block and there are three such blocks. Output signals SR1 to SR3 of the shift register 103 are used as control signals for controlling the ASW. For example, the switches SW1-1 to SW1-3 belonging to one block are controlled by the control signal SR1.

  On the other hand, the gate driver circuit 102 is provided with a shift register 104, and an output terminal of the shift register 104 is connected to each gate line G.

  Next, the operation of this liquid crystal display device will be described. FIG. 29 is a timing chart showing the operation of the data driver circuit shown in FIG. 28, and FIG. 30 is a timing chart showing the operation of the gate driver circuit shown in FIG. In FIG. 29, a period TH indicates one horizontal period in which a video signal is written to pixels for one row whose writing is controlled by one gate line of the liquid crystal display device.

  In the horizontal period TH, the gate driver circuit 102 outputs a high-level signal to one gate line Gn, and selects this one gate line Gn. The shift register 103 of the data driver circuit 101 sequentially outputs a control signal for controlling the ASW of each block in synchronization with the horizontal synchronization signal HSYNC input from the outside. In addition, since the video signal is supplied to the video signal wirings VD1 to VD3 in synchronization with the output of the shift register 103, the video signal is sampled on the data line D in units of blocks. In FIG. 29, since three data lines D are included in one block, a video signal is written for each of the three data lines D. At this time, since the potential that makes the pixel transistor TFT conductive is written in the selected one gate line G, the video signal sampled on the data line passes through the pixel transistor TFT to the pixel capacitance Clc. And written in the storage capacitor Cs.

  A period TV shown in FIG. 30 indicates one vertical period in which a video signal for one screen of the liquid crystal display device is written. During the vertical period TV, the gate driver circuit 102 sequentially writes a voltage for sequentially turning on the pixel transistors TFT to the gate line G one by one in synchronization with the vertical synchronization signal VSYNC input from the outside. By performing these operations, a two-dimensional image can be displayed on the liquid crystal display device.

  Thus, the advantage of the block division driving method is that the number of connection terminals between the liquid crystal display device and the external circuit can be greatly reduced. The number of terminals necessary for operating the data driver circuit and the gate driver circuit is 10 or less including the power supply, and the number of video signal wirings is also higher than the resolution of the liquid crystal display device XGA (width 1024 × length 768). Even if it is 30 or less. That is, by connecting about 50 terminals in total, it is possible to drive a liquid crystal display device having a resolution exceeding XGA. On the other hand, in a liquid crystal display device using an a-Si (amorphous silicon) TFT used for a display of a notebook personal computer, 3000 terminals or more must be connected in order to drive a liquid crystal display device having the same resolution. . Compared to this, the number of terminal connections can be significantly reduced by performing block division driving.

  In addition to the block division drive method described above, as a method to reduce the number of connection terminals to the liquid crystal display device, an IC (Integrated Circuit) that supplies video signals to the data lines is directly connected to the glass substrate of the liquid crystal display device. A method using a COG (chip on glass) connection is also conceivable. FIG. 31 is a block diagram showing a conventional liquid crystal display device using a COG connection. A liquid crystal display device using COG is a system that is currently widely used as a display for portable devices.

  As shown in FIG. 31, in this liquid crystal display device, the configuration of the gate lines, data lines, pixels, and gate driver circuits is the same as that of the liquid crystal display device shown in FIG. In place of the data driver circuit 101 shown in FIG. 28, a data line driving IC 111 is mounted on a TFT side glass substrate (not shown). The data line driving IC 111 is provided with a plurality of video signal lines V1 to V3, and each video signal line is connected to a plurality of data lines D via ASW. A plurality of ASWs connected to one output terminal (video signal line V) of the data line driving IC 111 are controlled by different control lines SP1 to SP3, respectively. Although not particularly illustrated, a signal and power for operating the data line driving IC 111 are supplied from the outside through an electric wiring arranged on the glass substrate of the liquid crystal display device.

  With such a configuration, the number of connection terminals necessary to operate the liquid crystal display device is about 10 for operating the gate driver circuit 102 and about 100 for operating the data line driver IC 111. Yes, compared to an a-Si TFT liquid crystal display device, the number of terminals is overwhelmingly small.

  Next, the operation of this liquid crystal display device will be described. FIG. 32 is a timing chart showing the operation of the data line driving IC shown in FIG. 31, and is a diagram showing the operation in one horizontal period. As shown in FIG. 32, one horizontal period TH is divided into three periods TB1 to TB3. In the period TB1, the potential of the control line SP1 becomes a potential that makes the ASW conductive, the ASW connected to the control line SP1 becomes conductive, and a video signal is written to the data line D. After that, the ASW connected to the control line SP2 becomes conductive in the period TB2, and the ASW connected to the control line SP3 becomes conductive in the period TB3, and the video signal is written to the data line D connected to each ASW. Go. As described above, when a plurality of data lines connected to one output terminal of the data line driving IC 111 via the ASW are made one block, video signals are sequentially written to the data lines in the block in a time division manner. The operation will be performed simultaneously in all blocks.

Japanese Patent Publication No. 6-80477 (Fig. 4) Japanese Patent No. 3428511 (paragraph 0016)

  However, the conventional techniques described above have the following problems. It is clear that the liquid crystal display device that performs block division driving and the liquid crystal display device that uses COG connection have a problem that display image quality deteriorates.

  In the case of the block division driving method, even when a video signal with the same luminance is written between the end portion of the block where the video signal is written in units of blocks and the other portions, a luminance difference is generated, which results in uneven vertical stripes. Will be recognized. FIG. 33 is an equivalent circuit diagram showing a configuration in the vicinity of ASW of the liquid crystal display device that performs block division driving shown in FIG. As already described, in this liquid crystal display device, video signals are written to the data lines in units of blocks in one horizontal period. Note the block controlled by the control signal SR2. In the period TB2, video signals are written to the data lines D4, D5, and D6 belonging to this block, and the ASW (switches SW2-1 to SW2-3) is returned to the non-passing state at the end of the period. Next, in a period TB3, writing of video signals to the data lines D7, D8, and D9 is started.

  At this time, there is capacitive coupling due to the parasitic capacitance Cp6-7 between the data line D6 and the data line D7. When a signal is written to the data line D7 and its potential fluctuates, the potential of the data line D6 also changes accordingly. It will fluctuate. Since this phenomenon occurs in all the blocks, the potential of the data line at the block boundary is shifted from the potential of the written signal. Of course, the parasitic capacitance between data lines exists not only between adjacent data lines, but also between data lines that are further away from each other. Strictly speaking, there is an error in the potential of all data lines. However, since the magnitude of the parasitic capacitance is the largest between the adjacent wirings, the error voltage of the data line located at the boundary of the block becomes the largest. This error voltage causes a luminance difference between the pixels, which affects all the pixels on the same data line, causing vertical stripes along the data line.

  In order to solve this problem, the present inventor has developed a method of reducing the vertical stripe unevenness by reducing the parasitic capacitance between the data lines by shielding the data lines, and disclosed in Patent Document 2. However, it is difficult to eliminate the parasitic capacitance at all, and when the number of gradations displayed on the liquid crystal display device is increased, the vertical stripe unevenness may be slightly visible.

  Also in a liquid crystal display device using a COG connection, a pixel column connected to one data line out of a plurality of data lines connected to one output terminal of the data line driving IC is different from other pixel columns. Therefore, there is a problem in that the brightness is different and it appears as vertical stripes. The cause of this will be described with reference to FIG. FIG. 34 is an equivalent circuit diagram showing a configuration in the vicinity of the ASW unit of the liquid crystal display device by the COG connection shown in FIG. As already described, one output of the data line driving circuit performs an operation of writing three data lines in a time division manner in one horizontal period.

  Attention is paid to the data lines D4 to D6 connected to the video signal line V2 of the data line driver IC 111 (see FIG. 31). In the period TB1, a signal is written to the data line D4. After that, the ASWSW2-1 becomes inactive and the data line D4 becomes floating. Next, a signal is written to the data line D5 in the period TB2. Then, due to the parasitic capacitance Cp4-5, potential fluctuation caused by signal writing of the data line D5 causes potential fluctuation of the data line D4 due to capacitive coupling.

  Next, in the period TB3, a signal is written to the data line D6. Due to the influence of this writing, potential fluctuation occurs in the data lines D5 and D7. In addition, during this period, signal writing is also performed on the data line D3, so that the data line D4 is also affected by this. That is, the data line D4 is subjected to potential fluctuation due to signal writing of the data lines D5 and D3, and the data line D5 is affected by potential fluctuation due to signal writing of the data line D6. The data line D6 is not affected by potential fluctuation because the signal writing of the adjacent data lines D5 and D7 is not performed after the signal writing is completed. Also in this case, strictly speaking, the parasitic capacitance between the data lines is not generated only between the adjacent data lines. However, it is the parasitic capacitance between adjacent data lines that has the greatest influence on the potential of a certain data line.

  As described above, since the manner of receiving potential fluctuations due to signal writing of other data lines differs among a plurality of data lines driven by the same output terminal of the data line driving circuit, it is similar to a liquid crystal display device that performs block division driving. As a result, vertical stripes are generated. However, at present, the liquid crystal display device by COG connection is used for a direct-view display for small portable terminals provided with R, G, B color filters, and in particular, the color filters are arranged in stripes along the data lines, and When the number of data lines driven by one output of the data line driving IC is 3, even if the voltage variation due to the parasitic capacitance of the data line occurs, the luminance change is equal between the data lines of the same color. It has been difficult to see as vertical streaks, and has not been viewed as a problem so far. However, when the number of time divisions is set to 3 or more (for example, a multiple of 3), and when it is used in a three-plate projector without adding a color filter, it becomes a big problem as in a liquid crystal display device that performs block division driving. .

  The present invention has been made in view of such problems, and a liquid crystal display device that writes video signals of one pixel row in a time-sharing manner, a driving method thereof, and a projector device and a portable terminal equipped with the liquid crystal display device An object of the present invention is to eliminate vertical streaks associated with time division writing.

  The liquid crystal display device according to the present invention includes (n × m) (n and m are integers of 2 or more) data lines divided into m groups for every n adjacent to each other extending in the row direction. , A plurality of gate lines extending in the column direction, a plurality of pixels provided at adjacent points between the data lines and the gate lines, and the gate lines within one vertical period for displaying an image for one screen. And a data driver circuit that outputs a video signal for one pixel row to the data line in one horizontal period when the gate driver circuit selects one of the gate lines. The data driver circuit includes m output terminals provided for each set for outputting the video signal, and a kth data line (k is an integer from 1 to n) in each set as the output terminal. K-th switch that switches whether to connect or not An n-th k-th control line commonly connected to the k-th switch; and a drive circuit for sequentially outputting a control signal for conducting the k-th switch to the k-th control line, The circuit is characterized in that the order in which the control signals are output to the n control lines within the horizontal period is varied for each predetermined period.

  In the present invention, by changing the order in which the control signals are output to the n control lines belonging to each group within the horizontal period for each predetermined period, the video signal is transmitted to the data lines belonging to each group within the horizontal period. The output order is different for each vertical period, and the data lines whose potentials fluctuate are dispersed every predetermined period, so that only the potentials of the data lines arranged at specific positions in each group can be prevented from fluctuating. Thereby, when the whole image is seen, unevenness of the vertical stripe shape can be eliminated. The predetermined period may be a vertical period or one or a plurality of horizontal periods.

  Further, it is preferable that the drive circuit changes the order of outputting the control signals to the n control lines within the horizontal period for each of the horizontal periods. As a result, the order can be varied not only for each vertical period but also for one or a plurality of horizontal periods, so that uneven vertical stripes can be more effectively eliminated.

  In another liquid crystal display device according to the present invention, (n × m) (n and m are integers of 2 or more) data divided into m groups every n adjacent to each other extending in the row direction. A line, a plurality of gate lines extending in the column direction, a plurality of pixels provided at each proximity point of the data line and the gate line, and a vertical period for displaying an image for one screen. A gate driver circuit for sequentially selecting gate lines; a data driver circuit for outputting a video signal for one pixel row to the data line in one horizontal period when the gate driver circuit selects one of the gate lines; And the data driver circuit outputs m output terminals provided for each set and outputs the video signal, and the kth data line (k is an integer from 1 to n) in each set. The k-th switch that switches whether or not to connect to the terminal, and all N k-th control lines commonly connected to the k-th switch, and a drive circuit for sequentially outputting a control signal for conducting the k-th switch to the k-th control line, The drive circuit is characterized in that the order in which the control signals are output to the n control lines within the horizontal period is varied for each of the one or more horizontal periods.

  In the present invention, by changing the order in which the control signals are output to the n control lines in the horizontal period for each one or a plurality of horizontal periods, the data line whose potential is changed is changed to one or a plurality of horizontal lines. It is possible to prevent the fluctuation of only the potential of the data line arranged at a specific position in each group by varying the period. Thereby, vertical stripe-like unevenness can be eliminated.

  Further, the liquid crystal display device stores at least one screen of a video signal input from the outside, and stores the stored video signal for the one screen during a period in which the video signal for the next one screen is input. It is preferable to have a signal processing circuit that reads out at a frequency t times (t is an integer of 2 or more) the frequency when input from the outside, and outputs the read video signal to the data driver circuit t times. As a result, the order of outputting the control signals to the n control lines in the horizontal period is changed more frequently by performing display based on the temporally compressed video signal output from the signal processing circuit. be able to. Thereby, vertical stripe-shaped unevenness can be more reliably prevented.

  At this time, the liquid crystal display device includes a first substrate on which the data lines and the gate lines are formed, a second substrate that sandwiches a liquid crystal layer between the first substrate, and the first substrate. A pixel electrode provided for each pixel on one substrate to which the video signal is applied from the data line, and a counter electrode provided on the second substrate, and the data driver circuit includes: The video signal having the same polarity with respect to the counter electrode may be output to the data line every vertical period.

  Further, the liquid crystal display device is irradiated by a light source that sequentially emits light of a plurality of colors during the vertical period, and the gate driver circuit is synchronized with the operation of the light source during the vertical period. The gate line may be scanned a plurality of times, and the data driver circuit may sequentially output video signals corresponding to a plurality of color images during the vertical period in synchronization with the operation of the light source. . Thereby, a color image can be displayed by a time division method without providing a color filter.

  A projector device according to the present invention includes the liquid crystal display device.

  Another projector device according to the present invention includes a light source, a separating unit that separates light emitted from the light source into light of a plurality of colors, and the separated light interposed in each optical path of the separated light. A plurality of liquid crystal display devices that are not provided with a color filter that adds an image to the separated light by transmitting the light, and a prism that combines the light transmitted through the plurality of liquid crystal display devices. And

  A portable terminal device according to the present invention includes a liquid crystal display device that displays a color image by the above-described time division method or a liquid crystal display device provided with a color filter.

  The driving method of the liquid crystal display device according to the present invention includes (n × m) (n and m are integers of 2 or more) divided into m groups for every n adjacent to each other extending in the row direction. In the method of driving a liquid crystal display device comprising: a data line; a plurality of gate lines extending in a column direction; and a plurality of pixels provided at each proximity point between the data line and the gate line. By sequentially selecting lines and outputting the video signal to the data lines, a vertical period in which an image for one screen is displayed on the pixels is repeatedly performed, and one gate line is provided for each vertical period. A horizontal period for outputting a video signal for one pixel row to the data line is sequentially performed for all the gate lines, and the kth data line in each set (for each horizontal period) is selected. k is an integer from 1 to n) Output, a sequence for outputting the video signal to the n data lines in said horizontal period, and wherein the varied for each of the vertical period.

  In another liquid crystal display device driving method according to the present invention, (n × m) (n and m are integers of 2 or more) divided into m groups for every n adjacent to each other extending in the row direction. ) Data lines, a plurality of gate lines extending in the column direction, and a plurality of pixels provided at each proximity point of the data lines and the gate lines. By sequentially selecting the gate lines and outputting the video signal to the data lines, a vertical period for displaying an image for one screen on the pixels is repeatedly performed, and one vertical line is displayed for each vertical period. A horizontal period in which a video signal for one pixel row is output to the data line while the gate line is selected is sequentially performed for all the gate lines, and the kth data in each set is output for each horizontal period. The video signal on a line (k is an integer from 1 to n) Sequentially outputs, the n number of the order to output the video signals to the data lines, and wherein the varied for each of the horizontal period of one or more times within said horizontal period.

  According to the present invention, the order in which the video signals are output to the data lines belonging to each group within the horizontal period is varied for each vertical period, thereby causing the data lines whose potentials vary to vary for each vertical period. Only the potential of the data line arranged at a specific position in the group can be prevented from changing. Thereby, vertical stripe-like unevenness can be eliminated.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. First, a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing a liquid crystal display device according to this embodiment. As shown in FIG. 1, in this liquid crystal display device 1, a TFT side glass substrate (not shown) and a counter side glass substrate (not shown) are provided in parallel to each other, and between the two substrates. A liquid crystal layer (not shown) is disposed.

  On the TFT side glass substrate, data lines D1 to D9 (collectively referred to as data lines D) extending in the row direction, that is, in the illustrated vertical direction are provided, and on the same TFT side glass substrate, the column direction That is, gate lines G1 to G6 (collectively referred to as data lines G) extending in the illustrated horizontal direction are provided. A pixel 2 is formed at each proximity point between the data lines D1 to D9 and the gate lines G1 to G6. That is, in this liquid crystal display device, a plurality of pixels are arranged in a matrix.

  Each pixel 2 is provided with one pixel thin film transistor TFT, a storage capacitor Cs, and a pixel electrode Ep. One of the source and drain of the pixel thin film transistor TFT is connected to the data line D, the other is connected to one electrode of the storage capacitor Cs and the pixel electrode Ep, and the gate is connected to the gate line G. A ground potential is applied to the other electrode of the storage capacitor Cs. Further, a counter electrode Eo is provided at a position corresponding to each pixel on the counter side glass substrate, and a pixel capacitor Clc is formed between the pixel electrode Ep and the counter electrode Eo. In the present embodiment, the ground potential is applied to the other electrode of the storage capacitor Cs, but it is not necessarily required to be the ground potential.

  Further, a data driver circuit 3 for driving the data line D and a gate driver circuit 4 for driving the gate line G are formed outside the region where the plurality of pixels 2 are formed on the TFT side glass substrate. . In the data driver circuit 3, a data line driving circuit 5 and analog switches (ASW) SW1-1 to SW3-3 (hereinafter also collectively referred to as ASW) are provided. The output terminal of the data line driving circuit 5 is connected to the video signal lines V1 to V3. The data line driving circuit 5 outputs video signals to the video signal lines V1 to V3.

  Further, a plurality of, for example, three data lines D adjacent to each other form one block (set). For example, the data lines D1 to D3 belong to the first group, the data lines D4 to D6 belong to the second group, and the data lines D7 to D9 belong to the third group. The data line driving circuit 5 is provided with a total of three output terminals, one for each of the above-described data line groups, and these three output terminals are video signal lines V1 to V3, respectively. It is connected to the.

  Each video signal line is connected to each data line D via an ASW. Specifically, the video signal line V1 is connected to the data lines D1 to D3 via the switches SW1-1 to SW1-3, respectively, and the video signal line V2 is connected to the switches SW2-1 to SW2-3. Are connected to the data lines D4 to D6, respectively, and the video signal line V3 is connected to the data lines D7 to D9 via the switches SW3-1 to SW3-3, respectively. .

  Expressing this generally, in the data line driving circuit 5, n data lines D (three in this embodiment) belong to each group, and the k-th (k is 1 through 1) in each group. There is provided a k-th switch for switching whether or not to connect the data line D (integer of n) to the video signal line. The number of the k-th switch is the same as the number of sets, for example, 3. That is, if the number of sets is m, the number of output terminals, video signal lines, and k-th switches is m, and the total number of switches is the same as the number of data lines D (m × n). Nine.

  The data line driving circuit 5 is provided with a total of n k-th control lines commonly connected to the k-th switch in each group. For example, in the present embodiment, three control lines SP1 to SP3 are provided. The control line SP1 is connected to the switches SW1-1, SW2-1 and SW3-1, the control line SP2 is connected to the switches SW1-2, SW2-2 and SW3-2, and the control line SP3 is The switches SW1-3, SW2-3, and SW3-3 are connected. Further, the data line driving circuit 5 is provided with a driving circuit 6, and control lines SP 1 to SP 3 are connected to output terminals of the driving circuit 6.

  The switches SW1-1 to SW3-3 are constituted by, for example, thin film transistors (TFTs). The data line driving circuit 5 is connected to one of the source and drain of each TFT, and the data line D is connected to the other. The control lines SP1 to SP3 are connected to the gate. Thereby, for example, when the potential of the control line SP1 becomes high level, the switches SW1-1, SW2-1, and SW3-1 are turned on, and the video signal lines V1, V2, and V3 are respectively connected to the data line D1, When connected to D4 and D7 and the potential of the control line SP1 becomes low level, the switches SW1-1, SW2-1 and SW3-1 become non-conductive, and the data lines D1, D4 and D7 become floating. .

  In this embodiment, there are nine data lines, six gate lines, and three adjacent data lines belong to one set, and are connected to one output terminal of the data line driving circuit 5 via the ASW. However, the present invention is not limited to this, and the number of data lines, the number of gate lines, and the number of data lines belonging to one set do not affect the essence of the present invention.

  Next, the operation of the liquid crystal display device according to this embodiment configured as described above, that is, the driving method of the liquid crystal display device according to this embodiment will be described. 2 to 4 are timing charts showing the operation of the liquid crystal display device according to the present embodiment, where time is taken on the horizontal axis and the potential of each wiring is taken on the vertical axis, and FIG. 2 shows the operation in a certain vertical period. 3 shows the operation in the vertical period next to the vertical period shown in FIG. 2, and FIG. 4 shows the operation in the vertical period next to the vertical period shown in FIG.

  In the present embodiment, the gate driver circuit 4 sequentially selects all the gate lines G, and the data driver circuit 3 outputs a video signal to all the data lines D, whereby a screen composed of a plurality of pixels 2 is formed. A vertical period for displaying an image for one screen is repeatedly performed. In each vertical period, a horizontal period in which a video signal for one pixel row is output to the data line D while one gate line G is selected is sequentially performed for all the gate lines G.

  A period TH shown in FIG. 2 indicates one horizontal period in which one gate line G1 is selected by the gate driver circuit 4 and a video signal is written in one pixel row connected to the one gate line G1. In each period TB1 to TB3 obtained by dividing the horizontal period into approximately three equal parts, the drive circuit 6 sets the potential of any of the control lines SP1 to SP3 for controlling the ASW to a potential at which the ASW becomes conductive, for example, a high level. Level potential. That is, a pulse is applied to the control lines SP1 to SP3. In the vertical period shown in FIG. 2, a pulse is applied to the control line SP1 in the period TB1, a pulse is applied to the control line SP2 in the period TB2, and a pulse is applied to the control line SP3 in the period TB3. Thereby, in the period TB1, the switches SW1-1, SW2-1, and SW3-1 are turned on, and the data lines D1, D4, and D7 are connected to the video signal lines V1, V2, and V3, respectively. In the period TB2, the switches SW1-2, SW2-2, and SW3-2 are turned on, and the data lines D2, D5, and D8 are connected to the video signal lines V1, V2, and V3, respectively. Further, in the period TB3, the switches SW1-3, SW2-3, and SW3-3 are turned on, and the data lines D3, D6, and D9 are connected to the video signal lines V1, V2, and V3, respectively. In this embodiment, one horizontal period is roughly divided into three periods TB1 to TB3. However, it is not always necessary to equally divide the period.

  On the other hand, the data line driving circuit 5 outputs a signal to be written to a pixel at the intersection of the data line D1 and the gate line G1 (hereinafter abbreviated as pixels (D1, G1)) to the video signal line V1 in the period TB1. The pixel (D4, G1) is output to V2, and a signal to be written to the pixel (D7, G1) is output to the video signal line V3. Similarly, in the period TB2, signals to be written to the pixels (D2, G1), the pixels (D5, G1), and the pixels (D8, G1) are output to the video signal lines V1, V2, and V3, respectively, and in the period TB3, The signals to be written to the pixels (D3, G1), the pixels (D6, G1), and the pixels (D9, G1) are output to the video signal lines V1, V2, and V3, respectively.

  At this time, since a voltage pulse for making the pixel TFT conductive is applied to the gate line G1 during this horizontal period, the video signal voltage held in the data line is written to each pixel connected to the gate line G1. . That is, the pixel thin film transistor TFT connected to the gate line G1 becomes conductive, the data line D is connected to one of the pixel electrode Ep and the storage capacitor Cs via the pixel thin film transistor TFT, and the pixel capacitor Clc and the storage capacitor Cs. In addition, charges corresponding to the video signal are accumulated, and the liquid crystal layer between the pixel electrode Ep and the counter electrode Eo is aligned to form a part of the image. Then, by performing the operation in the horizontal period described above for all the gate lines, the video signal for one screen can be written to all the pixels 2 and one screen can be displayed on the entire screen.

  Next, as shown in FIG. 3, in the vertical period following the vertical period shown in FIG. 2, a pulse is applied to the control line SP2 in the period TB1, and the switches SW1-2, SW2-2, and SW3-2 are turned on. The video signal is written to the data lines D2, D5, D8, a pulse is applied to the control line SP3 in the period TB2, the switches SW1-3, SW2-3, SW3-3 are turned on, and the data lines D3, D6, A video signal is written to D9, a pulse is applied to the control line SP1 in the period TB3, the switches SW1-1, SW2-1, and SW3-1 are turned on, and the video signals are written to the data lines D1, D4, and D7.

  Next, as shown in FIG. 4, in the vertical period following the vertical period shown in FIG. 3, a pulse is applied to the control line SP3 in the period TB1, video signals are written to the data lines D3, D6, and D9, and the period TB2 A pulse is applied to the control line SP1, a video signal is written to the data lines D1, D4, and D7, a pulse is applied to the control line SP2 in the period TB3, and a video signal is written to the data lines D2, D5, and D8.

  In the vertical period shown in FIGS. 3 and 4, only the video signal writing order in one horizontal period is different from the vertical period shown in FIG. 2, and the other operations are the operations in the vertical period shown in FIG. And display a video signal for one screen each. By the above-described operation, an operation is realized in which the order in which the data line driving circuit performs time-division writing of each data line is changed every three consecutive vertical periods. That is, there are three orders for outputting video signals to the data lines, and the three orders are repeatedly performed for each period composed of three consecutive vertical periods.

  Next, the effect of this embodiment will be described. According to the present embodiment, it is possible to significantly reduce the vertical stripe-shaped luminance unevenness along the data line. The reason will be described below. As described above, in the driving method in which signals are sequentially written in time division on a data line in one horizontal period, fluctuations in potential caused through parasitic capacitance when signals are written on other data lines as described above. Occurs because the data lines differ depending on the order in which signals are written. However, according to the present embodiment, the order in which signals are written to the data lines within one horizontal period changes every vertical period, so that it is possible to prevent large potential fluctuations from always occurring on the same data line, and vertical stripe unevenness. Can be reduced.

  Further, since the cycle in which the order is changed makes a round in 3 vertical periods equal to the number of data lines driven by one output of the data line driving circuit, the potential fluctuations of the data lines are made uniform in each data line. The resulting luminance difference is also averaged and becomes difficult to be visually recognized as vertical stripes.

  Next, a second embodiment of the present invention will be described. 5 to 7 are timing charts showing the operation of the liquid crystal display device according to this embodiment, with time on the horizontal axis and the potential of each wiring on the vertical axis. FIG. 6 shows the operation of a plurality of horizontal periods, FIG. 6 shows the operation of a plurality of consecutive horizontal periods in the next vertical period shown in FIG. 5, and FIG. 7 shows the next vertical period of the vertical period shown in FIG. The operation | movement of several continuous horizontal periods in is shown. The configuration of the liquid crystal display device according to the present embodiment is the same as that of the first embodiment, and only the signal generation order of the drive circuit 6 is different from that of the first embodiment.

  Periods TH3k, TH3k + 1, TH3k + 2 and TH3 (k + 1) shown in FIG. 5 each indicate a horizontal period, and each horizontal period is divided into three periods TB1, TB2 and TB3 divided into approximately three equal parts. In the period TB1 of the horizontal period TH3k, a pulse having a potential at which the ASW becomes conductive is applied to the control line SP1, and a video signal is written to the data lines D1, D4, and D7. In the period TB2, a pulse is applied to the control line SP2, and video signals are written to the data lines D2, D5, and D8. Further, in the period TB3, a pulse is applied to the control line SP3 and a video signal is written to the data lines D3, D6, and D9. In the next horizontal period TH3k + 1, video signals are written in the data lines D2, D5, and D8 in the period TB1, video signals are written in the data lines D3, D6, and D9 in the period TB2, and the data lines D1, D4, Write the video signal to D7. In this manner, in the vertical period shown in FIG. 5, the order in which signals are written to the data lines is changed for each horizontal period.

  Next, in the vertical period shown in FIG. 6, in the horizontal period TH3k, video signals are written to the data lines D2, D5, and D8 in the period TB1, and video signals are written to the data lines D3, D6, and D9 in the period TB2, and the period TB3 Then, the video signal is written to the data lines D1, D4, and D7. In the period T3k + 1 and the period T3k + 2, the data line to which the signal is written is changed for each of the three divided periods. Further, in the vertical period shown in FIG. 7 following this vertical period, in the horizontal period Tk3, video signals are written in the data lines D3, D6, D9 in the period TB1, and in the period TB2, the video signals are written in the data lines D1, D4, D7. In the period TB3, video signals are written to the data lines D2, D5, and D8. In the subsequent horizontal periods T3k + 1 and T3k + 2, the data line to which the signal is written is changed for each of the three divided periods. That is, in this operation, the order in which signals are written to the data lines changes every three consecutive horizontal periods, and the order changes in three consecutive vertical periods.

  In the present embodiment, by performing the operation as described above, the order in which signals are written to the data lines is changed for each continuous vertical period, and is changed for each continuous horizontal period even within the same vertical period. . As a result, a data line that receives a lot of potential fluctuation due to parasitic capacitance with an adjacent data line changes in a cycle in which the horizontal period is repeated, so that it becomes more difficult for humans to visually recognize the luminance difference between pixels due to the potential fluctuation. As a result, it is possible to make the vertical stripe-shaped unevenness more difficult to visually recognize as compared with the first embodiment. In the present embodiment, the order in which signals are written to the data lines is changed for each successive vertical period, and is changed for each successive horizontal period even within the same vertical period. If the order of writing is changed, it is not always necessary to change every writing period.

  Next, a third embodiment of the present invention will be described. FIG. 8 is a block diagram showing the liquid crystal display device according to the present embodiment. As shown in FIG. 8, in the liquid crystal display device 1a according to this embodiment, a signal processing circuit 7 is attached to the liquid crystal display device 1 according to the first embodiment described above. The signal processing circuit 7 generates a video signal and a control signal to be supplied to the liquid crystal display device 1 from a video signal and a synchronization signal input from the outside, and supplies these signals to the liquid crystal display device 1 together with a power supply voltage. is there. The signal processing circuit 7 is provided with a memory 8 that can hold a video signal to be displayed on the liquid crystal display device 1 for at least one screen, preferably two screens.

  Next, the operation of the liquid crystal display device according to this embodiment configured as described above, that is, the driving method of the liquid crystal display device according to this embodiment will be described. FIG. 9 is a timing chart showing the operation of the liquid crystal display device according to this embodiment, with the horizontal axis representing time and the vertical axis representing the potential of each wiring. In FIG. 9, signals VSYNC_IN and VIDEO_IN respectively indicate a vertical synchronization signal and a video signal of a video signal supplied from the outside to the signal processing circuit 7, and the signals VSYNC and VIDEO are a vertical signal supplied to the liquid crystal display device 1. A synchronization signal and a video signal are shown.

  A video signal for one screen is supplied to the signal processing circuit 7 for each vertical period TVin, and the memory 8 temporarily stores this video signal. Next, the signal processing circuit 7 compresses the time width of the video signal for one screen stored in the memory 8 by, for example, (1/3) times. Next, the signal processing circuit 7 outputs the compressed video signal to the liquid crystal display device 1 at a frequency, for example, three times the frequency supplied from the outside. Then, the liquid crystal display device 1 displays an image by the same operation as that of the first embodiment based on the video signal input at the triple frequency. For this reason, the vertical period TV of the video signal supplied to the liquid crystal display device 1 is a period of one third of the vertical period TVin of the video signal supplied to the signal processing circuit 7.

  Thus, in the present embodiment, the same video signal is displayed a plurality of times in one vertical period of the video signal supplied from the outside. The number of times that the same video signal is displayed is most desirably equal to the number of data lines (three in this embodiment) driven by time division in one output of the data line driving circuit in the liquid crystal display device.

  Next, the effect of this embodiment will be described. In the present embodiment, compared with the first and second embodiments described above, the cycle for changing the order of writing to the data lines can be further shortened. Thereby, it is possible to make the vertical stripe-shaped unevenness less visible. As a result, it becomes possible to make the vertical streak unevenness almost completely invisible.

  Further, the number of times the same video signal is displayed within one vertical period of the external signal is made equal to the number of data lines connected to one output terminal of the data line driving circuit, that is, the number of data lines belonging to one set. As a result, the potential fluctuations occurring in all the data lines can be made substantially equal within one vertical period of the video signal inputted to the signal processing circuit 7 from the outside. Can do.

  In the present embodiment, an example is shown in which the video signal supplied from the outside to the signal processing circuit 7 is an analog signal, and the video signal supplied from the signal processing circuit 7 to the liquid crystal display device 1 is also an analog signal. However, there is no problem even if these video signals are exchanged as digital signals. Further, in the present embodiment, an example in which the operation of the liquid crystal display device 1 is the same as that of the above-described first embodiment has been described, but it may be the same as that of the above-described second embodiment.

  Next, a fourth embodiment of the present invention will be described. FIG. 10 is a block diagram showing a liquid crystal display device according to this embodiment, FIG. 11 is a circuit diagram showing a gate driver circuit in this embodiment, and FIG. 12 shows a data line driving circuit in this embodiment. FIG. 13 is a cross-sectional view showing the liquid crystal display device according to this embodiment. The fourth embodiment describes the first embodiment described above in more detail.

  As shown in FIG. 10, in the liquid crystal display device according to the present embodiment, a connection terminal 9 for inputting an external signal is provided on the TFT side glass substrate 12 (see FIG. 13). The connection terminal 9 is connected to the data driver circuit 3, the gate driver circuit 4, and the counter electrode provided on the counter glass substrate 13 (see FIG. 13). Signals supplied to the data line driving circuit 5 and the driving circuit 6, the gate driver circuit 4, and the counter electrode of the data driver circuit 3 are supplied from the outside via the connection terminal 9. In general, an FPC (Flexible Printed Circuit) is used for this connection.

  As shown in FIG. 11, the gate driver circuit 4 is composed of a CMOS-type static shift register and a buffer circuit using an inverter. That is, in the gate driver circuit 4, a plurality of circuit blocks 10 are connected in series in a number of stages. The start signal GST is input to the first stage circuit block 10, and the output signal of the previous stage circuit block is input to the second and subsequent circuit blocks 10. ing. In FIG. 11, only the first-stage and second-stage circuit blocks 10 are shown.

  In each stage circuit block 10, a clock inverter CIV1 to which a start signal GST or an output signal from the preceding stage circuit block 10 is input is provided at its input terminal. In addition, an inverter IV1 whose input terminal is connected to the output terminal of the clock inverter CIV1 is provided, a clock whose input terminal is connected to the output terminal of the inverter IV1, and whose output terminal is connected to the input terminal of the inverter IV1. An inverter IV2 is provided. A clock inverter CIV3 whose input terminal is connected to the output terminal of the inverter IV1 is provided, and an inverter IV2 whose input terminal is connected to the output terminal of the clock inverter CIV3 is provided. A clock inverter IV4 is provided which is connected to the output terminal of the inverter IV2 and whose output terminal is connected to the input terminal of the inverter IV2. The output terminal of the inverter IV2 is an output terminal of the circuit block 10 and is connected to the input terminal of the clock inverter CIV1 of the circuit block 10 at the next stage. Further, the inverters IV3 to IV6 are connected in series in this order, the input terminal of the inverter IV3 is connected to the output terminal of the inverter IV2, and the output terminal of the inverter IV6 is connected to the gate line G. That is, the output terminal of the inverter IV6 of the first-stage circuit block 10 is connected to the gate line G1, and the output terminal of the inverter IV6 of the k-th circuit block 10 is connected to the gate line Gk. The clock inverter is controlled by two clock signals GCLK and / GCLK having different phases.

  On the other hand, the data line driving circuit 5 samples a video signal supplied from the outside, converts the video signal from digital to analog, and outputs it. In addition, one of a plurality of signals held inside is selected and output. The data line driving circuit 5 is COG-connected on the TFT side glass substrate 12 (see FIG. 13). At this time, the number of data lines that one output of the data line driving circuit 5 drives is often determined by the terminal pitch at the time of COG connection and the pixel pitch. At present, the terminal pitch of the COG connection is about 60 μm at the minimum, and the resolution of the liquid crystal display device used for the projector is 1024 in the vertical direction and 768 in the horizontal direction, so the display diagonal is 1 inch (about 25.4 mm). In some cases, the pixel pitch is about 20 μm. Therefore, if one output of the data line driving circuit drives three data lines, the wiring area connecting the data line driving circuit and the data lines can be reduced, which is advantageous for downsizing of the liquid crystal display device.

  As shown in FIG. 12, the data line driving circuit 5 is provided with a shift register 11. The shift register 11 receives a start signal DSTP and a clock signal DCLK, and sequentially outputs signals from nine output terminals DSR1 to DSR9. Further, the data line driving circuit 5 is provided with nine data sampling switches DSP1 to DSP9 each of which is selected to be conductive / non-conductive by signals output from the output terminals DSR1 to DSR9, and the data sampling switches DSP1 to DSP1 to The video signal VIDEO is applied to one end of the DSP 9 from the outside via the connection terminal 9 (see FIG. 10).

  Further, memories M11 to M19 are connected to the other ends of the data sampling switches DSP1 to DSP9, respectively. The memories M11 to M19 constitute a first memory group. The first memory group samples an externally supplied video signal according to the output of the shift register 11. Data transfer switches DTR1 to DTR9 are connected to the memories M11 to M19, respectively. These data transfer switches DTR1 to DTR9 are selected to be conductive / non-conductive by a common control signal TR. The data transfer switches DTR1 to DTR9 are for transferring the signals held in the first memory group all at once.

  Further, memories M21 to M29 are connected to the other ends of the data transfer switches DTR1 to DTR9, respectively. The memories M21 to M29 constitute a second memory group. The second memory group holds the video signal transferred from the first memory group. The memories M21 to M29 are connected to one ends of the data selection switches DSL1 to DSL9, respectively. The other ends of the data selection switches DSL1 to DSL3 are connected to the DAC circuit DAC1 for digital-analog conversion of the contents of the second memory, and the other ends of the data selection switches DSL4 to DSL6 are connected to the DAC circuit DAC2. The other ends of the data selection switches DSL7 to DSL9 are connected to the DAC circuit DAC3.

  Furthermore, conduction / non-conduction of the data selection switches DSL1, DSL4, DSL7 is selected by a common control signal SL1, and conduction / non-conduction of the data selection switches DSL2, DSL5, DSL8 is common. The selection is made by the control signal SL2, and the conduction / non-conduction of the data selection switches DSL3, DSL6 and DSL9 is selected by the common control signal SL3.

  Furthermore, the data line drive circuit 5 is provided with amplifiers AMP1 to AMP3 for amplifying the output of the DAC circuit, and the input terminals of the amplifiers AMP1 to AMP3 are connected to the DAC circuits DAC1 to DAC3, respectively, and the output terminals Are connected to video signal lines V1 to V3, respectively.

  As shown in FIG. 13, in the liquid crystal display device 1 according to the present embodiment, a TFT side glass substrate 12 and a counter side glass substrate 13 are provided and arranged in parallel to each other. A liquid crystal layer 14 is disposed between the TFT side glass substrate 12 and the opposite side glass substrate 13.

A lower light shielding film 15 made of WSi is provided on a part of the TFT side glass substrate 12, and an interlayer made of SiO ₂ is formed on the entire surface of the TFT side glass substrate 12 so as to embed the lower light shielding film 15. A membrane 16 is provided. A part of the interlayer film 16 is provided with a semiconductor layer 17 made of impurity-doped P-Si (polysilicon). The semiconductor layer 17 serves as one electrode of the TFT source region, channel region, drain region, and storage capacitor Cs. A gate insulating film 18 made of SiO ₂ is provided on the entire surface of the interlayer film 16 so as to embed the semiconductor layer 17. A gate metal film 19 made of WSi is provided in a part of the region immediately above the semiconductor layer 17 on the gate insulating film 18. The region immediately below the gate metal film 19 in the semiconductor layer 17 becomes a channel region of the TFT, and the regions on both sides thereof become source / drain regions. The gate metal film 19 is connected to the gate line G (see FIG. 10). Further, a capacitive metal film 20 made of WSi is provided in the same layer as the gate metal film 19. This capacitive metal film 20 becomes the other electrode of the storage capacitor Cs.

  An interlayer film 21 made of SiN is provided on the entire surface of the gate insulating film 18 so as to embed the gate metal film 19 and the capacitor metal film 20, and a part of the interlayer film 21 is made of Al. First-layer metal wiring films 22a to 22d made of are provided. The metal wiring film 22 a is connected to the lower light shielding film 15 through a via 23 a penetrating the interlayer film 21, the gate insulating film 18, and the interlayer film 16. The metal wiring film 22a is connected to a ground potential wiring (not shown). The metal wiring film 22 b is connected to one of the source / drain regions in the semiconductor layer 17 through a via 23 b penetrating the interlayer film 21 and the gate insulating film 18. The metal wiring film 22b is connected to the data line D (see FIG. 10). The metal wiring film 22 c is connected to the other of the source / drain regions in the semiconductor layer 17 through a via 23 c that penetrates the interlayer film 21 and the gate insulating film 18. The metal wiring film 22 d is connected to the capacitive metal film 20 through a via 23 d that penetrates the interlayer film 21.

  Further, an interlayer film 24 made of SiN is provided on the entire surface of the interlayer film 21 so as to embed the first metal wiring films 22a to 22d, and a part of the interlayer film 24 is made of Al. An upper light shielding film 25 is provided. A second-layer metal wiring film 26 made of Al is provided in the same layer as the upper light shielding film 25. The metal wiring film 26 is connected to the metal wiring film 22 d through a via 27 that penetrates the interlayer film 24. The metal wiring film 26 is also connected to a ground potential wiring (not shown). An interlayer film 28 made of SiN is provided on the entire surface of the interlayer film 24 so as to embed the upper light shielding film 25 and the metal wiring film 26.

  Furthermore, a transparent pixel electrode Ep made of ITO (Indium tin oxide) is provided on a part of the interlayer film 28. The pixel electrode Ep is connected to the metal wiring film 22 c through a through hole 29 formed in the interlayer films 28 and 26. An alignment film 30 is provided on the entire surface of the interlayer film 28 and the pixel electrode Ep.

  On the other hand, a counter electrode Eo made of ITO is provided on the counter-side glass substrate 13, and an alignment film 31 is provided on the counter electrode Eo. The liquid crystal layer 14 is disposed so as to be in contact with the alignment films 30 and 31. Other configurations in the present embodiment are the same as those in the first embodiment.

  Next, the operation of the liquid crystal display device according to this embodiment configured as described above, that is, the driving method of the liquid crystal display device according to this embodiment will be described. FIG. 14 is a timing chart showing the operation of the gate driver circuit of the liquid crystal display device according to the present embodiment, with time on the horizontal axis and the potential of each wiring on the vertical axis. FIG. 15 to FIG. 17 are timing charts showing the operation of the data driver circuit of the liquid crystal display device according to the present embodiment, with time on the horizontal axis and the potential of each wiring on the vertical axis. FIG. 16 shows the operation in the next vertical period of FIG. 15, and FIG. 17 shows the operation in the next vertical period of FIG.

  As shown in FIG. 14, the gate driver circuit 4 is controlled by a start signal GST and two clock signals GCLK and / GCLK having different phases. When the start signal GST synchronized with the clock signal is supplied to the first stage circuit block 10 (see FIG. 11) of the gate driver circuit 4, the gate driver circuit 4 has a length corresponding to one clock cycle in synchronization with the clock signal. The pulses are output sequentially. At this time, if the period of the clock signal GCLK is made equal to the period of the horizontal period of the liquid crystal display device, the gate driver circuit 4 performs an operation of sequentially outputting pulses to the gate line G every horizontal period. That is, the start signal GST becomes a high level at the beginning of the vertical period TV shown in FIG. 14, and using this as a trigger, the gate lines G sequentially become a high level, but one gate line G becomes a high level. The period during which the period is horizontal is TH.

  Then, as shown in FIG. 15, in a certain vertical period, the start signal DSTP becomes a high level at the beginning of each horizontal period. A video signal VIDEO for displaying an image on the liquid crystal display device is sequentially supplied from the outside to the shift register 11 of the data driver circuit 5 in synchronization with the clock signal DCLK using the start signal DSTP as a trigger. Then, the shift register 11 sequentially outputs pulses to the output terminals DSR1 to DSR9 in synchronization with the clock signal DCLK, and sequentially turns on the data sampling switches DSP1 to DSP9. As a result, the first memory group (memory M11 to M19) sequentially samples and holds the supplied video signal VIDEO. After all the signals are held in the first memory group, the data transfer switches DTR1 to DTR9 are simultaneously turned on by the control signal TR, and the signals held in the first memory group are transferred to the second memory group (memory M21 to M21). M29), and the second memory group holds this.

  In the held video signal, the control signals SL1 to SL3 are sequentially set to the high level in the next horizontal period, so that the data selection switches DSL1, DSL4, and DSL7 are turned on in the period TB1, and the data selection switches DSL2 and DSL2 in the period TB2. DSL5 and DSL8 are turned on, and the data selection switches DSL3, DSL6 and DSL9 are turned on in the period TB3. Thus, in the period TB1, the video signals held in the memories M21, M24, and M27 are output to the DAC circuits DAC1 to DAC3, respectively, are converted from digital to analog by the DAC circuit, and are amplified by the amplifiers AMP1 to AMP3, respectively. And output to the video signal lines V1 to V3. At this time, since the signal SP1 for controlling the ASW by the driving circuit 6 (see FIG. 10) is set to a potential (high level) that makes the ASW conductive, the signals output to the video signal lines V1 to V3 are the data lines, respectively. It is written in D1, D4 and D7.

  Similarly, in the period TB2, the video signals held in the memories M22, M25, and M28 are converted into analog signals, amplified, and output to the video signal lines V1 to V3. Since the signal SP2 becomes high level, the signals output to the video signal lines V1 to V3 are written to the data lines D2, D5, and D8, respectively. In the period TB3, the video signals held in the memories M23, M26, and M29 are converted into analog signals, amplified and output to the video signal lines V1 to V3, and the signal SP3 becomes high level, so that the data lines D3, It is written in D6 and D9.

  As described above, since the gate driver circuit 4 outputs a pulse for turning on the pixel thin film transistor TFT to one gate line every horizontal period, the signal written to the data line D is converted into the pixel capacitance Clc and the storage capacitance Cs. Is written to. By performing this operation for all the pixel rows, a two-dimensional image can be displayed.

  As shown in FIG. 16, in the vertical period next to the vertical period shown in FIG. 15, in one horizontal period, first, video signals are written to the data lines D2, D5, and D8 in the period TB1, and then Video signals are written to the data lines D3, D6, and D9 in the period TB2, and finally, signals are written to the data lines D1, D4, and D7 in the period TB3.

  Further, as shown in FIG. 17, in the vertical period next to the vertical period shown in FIG. 16, in one horizontal period, first, video signals are written to the data lines D3, D6, D9 in the period TB1, and then Video signals are written to the data lines D1, D4, and D7 in the period TB2, and finally, signals are written to the data lines D2, D5, and D8 in the period TB3.

  In the liquid crystal display device according to the present embodiment, the following effects are obtained. That is, the vertical stripe-like luminance unevenness along the data line is greatly reduced. The reason will be described below. Vertical stripe-like luminance unevenness In a drive in which data lines are sequentially written in time division in one horizontal period, the potential generated through parasitic capacitance when signals are written to other data lines depends on the order of signal writing This occurs because the data lines are different. However, in the driving method of the liquid crystal display device of this embodiment, since the order of writing signals to the data lines changes within one horizontal period every vertical period, a large potential fluctuation does not always occur on the same data line. In addition, since the cycle of changing the order makes a round in three vertical periods equal to the number of data lines driven by one output of the data line driving circuit, the potential fluctuations of the data lines are made uniform in each data line. As a result, the difference in brightness is also averaged, so that it becomes difficult to be visually recognized as vertical stripe unevenness.

  In the present embodiment, an example in which each stage of the shift register in the gate driver circuit 4 is configured by four clocked inverters and two inverters has been described, but the present invention is not limited to this, Even if it is a structure, there will be no problem if it is a circuit which outputs sequentially in synchronization with the clock signal.

  Further, in the present embodiment, the data driver circuit 5 converts the contents of the first memory group (memory M11 to M19), the second memory group (memory M21 to M29), and the second memory group into digital-analog conversion. The DAC circuit DAC1 to DAC3, the amplifiers AMP1 to AMP3 that amplify the output of the DAC circuit, and the data selection switches DSL1 to DSL9 that connect the second memory group and the DAC circuit are shown. There is no problem as long as the circuit has the above-described function even if the configuration is other than this.

  Furthermore, in the liquid crystal display device according to the present embodiment, the materials for forming the wiring metal film, the light-shielding metal film, and the interlayer film have little relevance to the essence of the present invention, and any material other than those described above may be used. No problem.

  Furthermore, in this embodiment, an example is shown in which there are nine data lines, six gate lines, and three data lines connected to one output of the data line driving circuit. The values are not limited, and these values can be arbitrarily selected according to the required specifications of the liquid crystal display device.

  Furthermore, in this embodiment, an example in which the pixel TFT is formed on the TFT side glass substrate on which the pixel is arranged is shown, but a signal for driving each gate line is supplied from the outside. May be. However, a liquid crystal display device for a projector needs to be made as small as possible, so that it is desirable to produce it on the same substrate as the pixels.

  Furthermore, in this embodiment, an example in which the gate driver circuit is arranged only on one side of the pixel matrix is shown, but the gate driver circuit may be arranged on both sides of the pixel matrix. At this time, when one gate line is driven from two directions by two gate driver circuits arranged on both sides, there is an advantage that the rise and fall times of the pulses supplied to the gate line are shortened. In addition, when different gate lines are driven by two gate driver circuits arranged on both sides, the pitch of the output terminals in each gate driver circuit can be widened, and the liquid crystal display device can be reduced in size and definition. It is advantageous.

  Furthermore, the signal and power supply voltage required for the gate driver circuit 4 and the power supply voltage supplied to the counter electrode may be supplied from the data line driving circuit 5.

  Next, a fifth embodiment of the present invention will be described. This embodiment explains the above-mentioned 2nd embodiment in detail. Since the configuration of the liquid crystal display device according to the present embodiment is the same as the configuration of the liquid crystal display device according to the above-described fourth embodiment, the description thereof is omitted. Hereinafter, the operation of the liquid crystal display device according to the present embodiment will be described. FIG. 18 is a timing chart showing the operation of the data driver circuit of the liquid crystal display device according to the present embodiment, with time on the horizontal axis and the potential of each wiring on the vertical axis. As shown in FIG. 18, in each vertical period, in a certain horizontal period TH3k, the drive circuit 6 (see FIG. 10) sets the potential of the control line SP1 to the high level in the period TB1, whereby the data lines D1, D4, D7 The video signal is written in Next, in the period TB2, the potential of the control line SP2 becomes high level, and a video signal is written to the data lines D2, D5, and D8. Next, in the period TB3, the potential of the control line SP3 becomes a high level, and a video signal is written to the data lines D3, D6, and D7. The operation until a signal is taken in and output to the data line driving circuit within the horizontal period is the same as the operation described in the fourth embodiment.

  In the next horizontal period TH3k + 1, video signals are written in the data lines D2, D5, and D8 in the period TB1, then video signals are written in the data lines D3, D6, and D9 in the period TB2, and the data line D1 in the period TB3. , D4 and D7 are written video signals. In the next horizontal period TH3k + 2, video signals are written in the data lines D3, D6, D9 in the period TB1, video signals are written in the data lines D1, D4, D7 in the period TB2, and the data lines D2, D5 are written in the period TB3. , D8 is written. As described above, in this embodiment, the order in which the video signals are written to the data lines is changed every horizontal period.

  In the liquid crystal display device according to the present embodiment, the following effects are obtained. This is an effect of making it difficult to visually recognize the uneven stripes. The reason why this effect can be obtained is that the order in which signals are written to the data lines changes every successive horizontal period, and the data lines that receive a lot of potential fluctuations of the data lines change at the frequency of the horizontal period. This is because it is difficult for humans to visually recognize the luminance difference between pixels.

  Next, a sixth embodiment of the present invention will be described. Since the configuration of the liquid crystal display device according to the present embodiment is the same as the configuration of the liquid crystal display device according to the above-described fourth embodiment, the description thereof is omitted. Hereinafter, the operation of the liquid crystal display device according to the present embodiment will be described. In the present embodiment, the method for driving the liquid crystal display device according to the fifth embodiment is further improved. In the driving method of the liquid crystal display device according to the present embodiment, the operation in a certain vertical period is the same as the operation shown in FIG. 19 and 20 are timing charts showing the operation of the data driver circuit of the liquid crystal display device according to this embodiment, with time on the horizontal axis and the potential of each wiring on the vertical axis. Shows the operation in the vertical period next to the vertical period shown in FIG. 18, and FIG. 20 shows the operation in the vertical period next to the vertical period shown in FIG.

  As shown in FIG. 19, the operation in the vertical period next to the vertical period shown in FIG. 18 is as follows. In a certain horizontal period TH3k, first, video signals are written to the data lines D2, D5, D8, then video signals are written to the data lines D3, D6, D9, and finally, video signals are written to the data lines D1, D4, D7. Written. In the next horizontal period TH3k + 1, video signals are first written to the data lines D3, D6, D9, then video signals are written to the data lines D1, D4, D7, and finally to the data lines D2, D5, D8. In the next horizontal period TH3k + 2, first, signals are written to the data lines D1, D4, D7, then video signals are written to the data lines D2, D5, D8, and finally to the data lines D3, D6, D9.

  As shown in FIG. 20, in the next vertical period, in the horizontal period TH3k, video signals are first written to the data lines D3, D6, and D9, then to the data lines D1, D4, and D7, and finally to the data line D2. , D5 and D8 are written video signals. In the next horizontal period TH3k + 1, video signals are first written to the data lines D1, D4, and D7, then video signals are written to the data lines D2, D5, and D8, and finally to the data lines D3, D6, and D9. In the next horizontal period TH3k + 2, video signals are first written to the data lines D2, D5, and D8, then video signals are written to the data lines D3, D6, and D9, and finally to the data lines D1, D4, and D7. Operations other than those described above in the present embodiment are the same as those in the fifth embodiment described above.

  According to the present embodiment, the order in which signals are written to the data lines is different for each vertical period and for each horizontal period as compared to the fourth and fifth embodiments described above. The data line that receives the potential fluctuation can be made different for each vertical period and each horizontal period. Thereby, it becomes difficult for a human to visually recognize the luminance difference of the pixel due to the potential fluctuation, and the vertical stripe unevenness can be more reliably eliminated. The effects of the present embodiment other than those described above are the same as the effects of the fourth and fifth embodiments described above.

  Next, a seventh embodiment of the present invention will be described. FIG. 21 is a block diagram showing a liquid crystal display device according to this embodiment. As shown in FIG. 21, a liquid crystal display device 1a according to this embodiment is obtained by attaching a signal processing circuit 7 to the liquid crystal display device 1 according to the above-described fourth embodiment. In the sixth embodiment, the third embodiment will be described in more detail. The configuration of the liquid crystal display device 1 is as described in the fourth embodiment.

  The signal processing circuit 7 is supplied with an input video signal and a synchronization signal from a signal source (not shown) that supplies a video signal, and supplies the video signal and the control signal to the liquid crystal display device 1. Various power supply voltages required in the above are also supplied. The signal processing circuit 7 is provided with a memory 32 that can hold at least one screen of a video signal supplied from a signal source. The memory 32 is provided with frame memories 33 and 34 each capable of holding a video signal for one screen. Further, the memory 32 is provided with a switch 35 for selecting whether the video signal input from the external signal source is input to the frame memory 33 or the frame memory 34, and is stored in the frame memory 33. A switch 36 is provided for selecting whether to output a video signal to the liquid crystal display device 1 or to output a video signal stored in the frame memory 34 to the liquid crystal display device 1.

  The signal processing circuit 7 receives a synchronization signal from a signal source, outputs a memory control signal MW for controlling the switch 35, and outputs a memory control signal MR for controlling the switch 36, and the liquid crystal display device 1. Is provided with a control circuit 37 for outputting a control signal. Further, the signal processing circuit 7 is provided with a power supply circuit 38 that generates various power supply voltages and outputs them to the liquid crystal display device 1.

  Next, the operation of the liquid crystal display device according to this embodiment configured as described above, that is, the driving method of the liquid crystal display device according to this embodiment will be described. FIG. 22 is a timing chart showing the operation of the signal processing circuit 7 in this embodiment, with time on the horizontal axis and the potential of each wiring on the vertical axis. FIG. 23 is a diagram showing the polarity of a video signal applied to the pixel electrode of each pixel in a certain vertical period, and FIG. 24 is applied to the pixel electrode of each pixel in the next vertical period of FIG. It is a figure which shows the polarity of a video signal.

  As shown in FIG. 22, the video signal VIDEO_IN output from the signal source is input to the signal processing circuit 7 in synchronization with the synchronization signal VSYNC_IN output from the signal source. The video signal VIDEO_IN is an analog signal, and the synchronization signal VSYNC_IN is a digital signal that becomes a high level only at the beginning of each vertical period of the video signal VIDEO_IN. The memory control signals MW and MR are signals that determine which one of the frame memories 33 and 34 writes a signal and from which the signal is read out by controlling the switches 35 and 36, respectively.

  In a certain vertical period TVin (2m), the memory control signal MW is at the high level and the memory control signal MR is at the low level. Therefore, the video signal VIDEO_IN from the signal source is written into the frame memory 33, and the video from the frame memory 34 Assume that the signal VIDEO_IN is read. Then, in the vertical period TVin (2m + 1) following the vertical period TVin (2m), the levels of the memory control signals MW and MR are inverted, signals are written to the frame memory 34, and signals are read from the frame memory 33. By performing such an operation, it is possible to perform frequency conversion in which a video signal supplied from a signal source is read out at a different frequency. In the example shown in FIG. 22, the video signal input from the signal source and stored in the frame memory is read at a triple frequency, and the same signal is read from the signal source three times within one vertical period of the video signal to the liquid crystal display device 1. Supply. Thereby, the time width of the video signal VIDEO_IN is compressed to (1/3) times, and the video signal VIDEO having a frequency three times the frequency of the video signal VIDEO_IN can be supplied to the liquid crystal display device 1.

  In the liquid crystal display device 1, the video signal supplied from the signal source is displayed three times each at a triple speed. The operation in the liquid crystal display device 1 at this time may be any of the methods shown in the fourth to sixth embodiments. At this time, as shown in FIGS. 23 and 24, in the liquid crystal display device 1, a signal having the same polarity is written to the counter electrode in all the pixel electrodes in one vertical period in which the video signal of one screen is displayed. Frame inversion driving may be performed to invert this polarity every vertical period. That is, in the vertical period shown in FIG. 23, a signal having a positive polarity with respect to the counter electrode is written to the pixel electrode, and in the next vertical period shown in FIG. You may write in an electrode.

  Next, the effect of this embodiment will be described. In this embodiment, since the vertical period is shorter than in the fourth to sixth embodiments, the period for changing the order in which video signals are written to the data lines is shorter, and the vertical streaks are more uneven. It becomes difficult to see. As a result, it is possible to make the vertical streak unevenness almost completely invisible.

  In addition, since the number of times the same video signal is displayed within one vertical period of the external signal is equal to the number of data lines on which one output of the data line driving circuit performs time division writing (3 in this embodiment), the external signal Thus, the potential fluctuations occurring in all the data lines within one vertical period can be made almost equal, and the luminance difference of the pixels due to the potential fluctuations can be made difficult to visually recognize.

  Further, when a driving method is used in which a signal with the same polarity with respect to the counter electrode is written to all pixels in a period in which the liquid crystal display device displays a signal for one screen, the aperture ratio of the liquid crystal display device can be increased. Light utilization efficiency can be improved. In general, a liquid crystal display device uses a driving method in which the polarity of the voltage applied to each pixel is reversed for each pixel for each frame in order to prevent deterioration of the liquid crystal, and signals having different polarities are applied to adjacent pixels. The driving method to apply is generally used. In particular, liquid crystal display devices for projectors often use gate line inversion driving in which signals having the same polarity are written for each pixel row and signals having different polarities between adjacent pixel rows are applied. It reduces the flicker by changing the polarity for each adjacent pixel row, and arranges the TFT and the storage capacitor at positions along the gate line, thereby controlling the alignment of liquid crystal molecules generated between adjacent pixels. This is because the position of the light leakage due to the disturbance is set near the region where the TFT and the storage capacitor are arranged and the portion is shielded to eliminate the influence of the light leakage due to the disturbance of the orientation. However, in a liquid crystal display device with a pixel pitch smaller than 20 μm, the area ratio of the region where the alignment of liquid crystal molecules is disturbed with respect to the pixel region increases, the aperture ratio cannot be increased, and the light utilization efficiency is low. There was a problem of becoming something.

  On the other hand, when frame inversion driving is performed at a fast frequency as in the present embodiment, signals having the same polarity can be written to all the pixel electrodes in a certain frame while avoiding the problem of flicker. Accordingly, signals having different polarities are not written between adjacent pixel electrodes, so that light leakage does not occur and the aperture ratio can be increased. For this reason, it becomes possible to improve the utilization efficiency of light.

  In the present embodiment, an example in which the video signal is an analog signal has been described, but there is no problem even if it is processed as a digital signal.

  Next, an eighth embodiment of the present invention will be described. FIG. 25 is a timing chart showing the operation of the liquid crystal display device according to the eighth embodiment of the present invention, where time is taken on the horizontal axis and the potential of each wiring is taken on the vertical axis. The liquid crystal display device according to the present embodiment emits red (R), green (G), and blue (B) light sequentially emitted from a light source (not shown). Since the configuration of the liquid crystal display device according to the present embodiment is the same as that of the above-described fourth embodiment, the description thereof is omitted. A period TV shown in FIG. 25 indicates a vertical period in which a signal for one screen of a video signal supplied from the outside to the liquid crystal display device is supplied.

  In the present embodiment, the vertical period TV is divided into at least three subframe periods, and each subframe period is divided into at least two periods. That is, the vertical period TV is divided into subframe periods TSVR, TSVG, TSVB, the subframe period TSVR is divided into periods TWR and TLR, the subframe period TSVG is divided into periods TWG and TLG, and the subframe period TSVGB is divided into periods. Divide into TWB and TLB. In the period TWR, a red component signal of the video signal to be displayed on the liquid crystal display device is written. In the period TLR, the light source irradiates the liquid crystal display device with red light. Similarly, a green component video signal is written in the period TWG, and in the period TLG, the light source irradiates the liquid crystal display device with green light. In the period TWB, a blue component video signal is written, and in the period TLB, the light source irradiates the liquid crystal display device with blue light.

  In the liquid crystal display device according to the present embodiment, by performing field sequential driving, a color image can be displayed in a time division manner without providing a color filter in the liquid crystal display device. The effects of the present embodiment other than those described above are the same as those of the fourth embodiment described above.

  Next, a ninth embodiment of the present invention will be described. This embodiment is an embodiment of a projector apparatus. FIG. 26 is a block diagram showing a projector apparatus according to this embodiment. As shown in FIG. 26, the projector device according to the present embodiment is a liquid crystal projector device using three liquid crystal display devices for light of three primary colors of R, G, and B. The projector device 41 is provided with a lamp 42 as a light source, and color separation that transmits red light and reflects green and blue light at a position interposed in the optical path of light emitted from the lamp 42. A mirror 43 is provided. Between the lamp 42 and the color separation mirror 43, an optical component (not shown) for making the light uniform and an optical component (not shown) for aligning the polarization of the light are provided.

  Further, a mirror 44 for totally reflecting light and a red liquid crystal display device 45 are provided in this order so as to be interposed in the optical path of the light transmitted through the color separation mirror 43. Further, a color separation mirror 46 that reflects green light and transmits blue light is provided so as to be interposed in the optical path of the light reflected by the color separation mirror 43, and is reflected by the color separation mirror 46. A green liquid crystal display device 47 is provided so as to be interposed in the optical path of light. Furthermore, a mirror 48 for totally reflecting light, a mirror 49 and a blue liquid crystal display device 50 are provided in this order so as to be interposed in the optical path of the light transmitted through the color separation mirror 46.

  Furthermore, a composite prism 51 that combines light transmitted through the red liquid crystal display device 45, the green liquid crystal display device 47, and the blue liquid crystal display device 50 is provided, and the combined light emitted from the composite prism 51 is expanded. A projection lens 52 is provided for projecting light onto an external screen (not shown). The red liquid crystal display device 45, the green liquid crystal display device 47, and the blue liquid crystal display device 50 are all monochromatic liquid crystal display devices, and are liquid crystal display devices according to any of the above-described embodiments.

  Next, the operation of the projector apparatus according to this embodiment will be described. The red liquid crystal display device 45, the green liquid crystal display device 47, and the blue liquid crystal display device 50 display the red image, the green image, and the blue image, respectively, and the lamp 42 is turned on in this state. As a result, the white light emitted from the lamp 52 is made uniform and polarized, and then reaches the color separation mirror 43. The red component of the white light passes through the color separation mirror 43, and the green component and The blue component is reflected. And the red light which permeate | transmitted the color separation mirror 43 is reflected by the mirror 44, permeate | transmits the liquid crystal display device 45 for red, and the image for red is added.

  The light reflected by the color separation mirror 43 reaches the color separation mirror 46, the green component is reflected by the color separation mirror 46, and the blue component is transmitted. Then, the green light reflected by the color separation mirror 46 is transmitted through the green liquid crystal display device 47 and a green image is added. On the other hand, the blue light transmitted through the color separation mirror 46 is reflected by the mirror 48, reflected by the mirror 49, transmitted through the blue liquid crystal display device 50, and a blue image is added.

  Then, red light to which a red image is added by the red liquid crystal display device 45, green light to which a green image is added by the green liquid crystal display device 47, and a blue image by the blue liquid crystal display device 50. The added blue light is combined by the combining prism 51 to form a color image, and is expanded by the projection lens 52 and projected onto the screen.

  In the projector device according to the present embodiment, the vertical streak unevenness along the data line hardly occurs in the liquid crystal display device incorporated in the projector device, so that the vertical streak unevenness hardly occurs even in the projected image. For this reason, even when the number of display gradations is increased as compared with the conventional liquid crystal projector device, a high-quality image without unevenness can be obtained.

  The projector device of the present invention may be a front type liquid crystal projector device or a rear type liquid crystal projector device.

  Next, a tenth embodiment of the present invention will be described. FIG. 27 is a block diagram showing a liquid crystal display device according to this embodiment. The symbols “R”, “G”, and “B” in FIG. 27 indicate the colors of the color filters arranged in each pixel. As shown in FIG. 27, in the liquid crystal display device according to this embodiment, each pixel is provided with a red (R), green (G), or blue (B) color filter. This color filter may be provided on either the TFT side glass substrate or the counter side glass substrate. Further, color filters of the same color are arranged along the row direction, that is, the direction in which the data line D extends, and color filters of different colors are arranged along the column direction, that is, the direction in which the gate line G extends. Yes. In this embodiment, the number of data lines D driven by one output of the data line driving circuit 5, that is, the number of data lines D belonging to one set is 6, and the number of colors of the color filter is 3 or more. It has become. The driving method of the liquid crystal display device according to this embodiment is the same as that of the above-described fourth embodiment. Note that it may be the same as any one of the fifth to eighth embodiments described above.

  When a conventional liquid crystal display device is used, if the number of data lines driven by one output of the data line driving circuit is 3, which is the same as the number of colors, even if potential fluctuations due to sampling occur, The amount of variation is equal. For this reason, as compared with the case where the number of data lines driven by one output of the data line driving circuit is different from the number of colors, the vertical stripe-shaped unevenness is less visible. However, if the number of data lines driven by one output of the data line driving circuit is larger than the number of colors, for example, if the number of data lines driven by one output is 4 or more and the number of colors is 3, the same color is used. Even in such a case, data lines with different potential fluctuations are generated, and vertical stripe-shaped unevenness becomes remarkable. On the other hand, in this embodiment, even if the number of data lines driven by one output of the data line driving circuit is larger than the number of colors, the potential fluctuations of the data lines are made uniform over time. Streaky irregularities are hardly visible.

  In this embodiment, a plurality of color filters extending in the column direction are provided, and pixels provided with the same color filter are arranged along the column direction, that is, the direction in which the gate lines extend, and the row direction. That is, pixels provided with color filters of different colors may be arranged along the direction in which the data lines extend. Thereby, the effect of eliminating the vertical stripe-like unevenness can be obtained. This is because, when pixels with color filters of the same color are arranged along the direction in which the gate line extends, even if attention is paid to only a specific color, the pixels for displaying that color are different in one horizontal period. This is because the signal is written at the timing. This principle is the same as that of the above-described monochrome display liquid crystal display device. As a result, if the liquid crystal display device according to the present embodiment is used, it is possible to greatly reduce the vertical stripe unevenness.

  In the present embodiment, an example in which the color types of the color filter are three colors of R, G, and B is shown. However, the present invention is not limited to this, and for example, R, G, B, W ( White) may be used.

  In addition, the liquid crystal display device according to each of the above-described embodiments can be used as a display device of a mobile terminal device such as a mobile phone, a PDA (Personal Digital Assistance), a game machine, a digital camera, or a video camera. it can. The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope grasped from the description of the scope of claims of the present invention.

  Examples of utilization of the present invention include a front type liquid crystal projector device, a rear type liquid crystal projector device, and a portable terminal device.

1 is a block diagram showing a liquid crystal display device according to a first embodiment of the present invention. FIG. 5 is a timing chart showing the operation of the liquid crystal display device according to the present embodiment, with time on the horizontal axis and the potential of each wiring on the vertical axis, showing the operation in a certain vertical period. 3 is a timing chart showing the operation of the liquid crystal display device according to the present embodiment with time on the horizontal axis and the potential of each wiring on the vertical axis, showing the operation in the vertical period next to the vertical period shown in FIG. . FIG. 4 is a timing chart showing the operation of the liquid crystal display device according to the present embodiment with time on the horizontal axis and the potential of each wiring on the vertical axis, showing the operation in the vertical period next to the vertical period shown in FIG. 3. . 6 is a timing chart showing the operation of the liquid crystal display device according to the second embodiment of the present invention, where time is taken on the horizontal axis and the potential of each wiring is taken on the vertical axis, showing the operation in a certain vertical period. FIG. 6 is a timing chart showing the operation of the liquid crystal display device according to the present embodiment with time on the horizontal axis and the potential of each wiring on the vertical axis, showing the operation in the vertical period next to the vertical period shown in FIG. 5. . FIG. 7 is a timing chart showing the operation of the liquid crystal display device according to the present embodiment with time on the horizontal axis and the potential of each wiring on the vertical axis, showing the operation in the vertical period next to the vertical period shown in FIG. 6. . It is a block diagram which shows the liquid crystal display device which concerns on the 3rd Embodiment of this invention. 4 is a timing chart showing the operation of the liquid crystal display device according to the present embodiment, with time on the horizontal axis and the potential of each wiring on the vertical axis. It is a block diagram which shows the liquid crystal display device which concerns on the 4th Embodiment of this invention. It is a circuit diagram which shows the gate driver circuit in this embodiment. It is a block diagram which shows the data line drive circuit in this embodiment. It is sectional drawing which shows the liquid crystal display device which concerns on this embodiment. 6 is a timing chart showing the operation of the gate driver circuit of the liquid crystal display device according to the present embodiment, with time on the horizontal axis and the potential of each wiring on the vertical axis. 6 is a timing chart showing the operation of the data driver circuit of the liquid crystal display device according to the present embodiment, with time on the horizontal axis and the potential of each wiring on the vertical axis, showing the operation in a certain vertical period. FIG. 16 is a timing chart showing the operation of the data driver circuit of the liquid crystal display device according to the present embodiment, with time on the horizontal axis and the potential of each wiring on the vertical axis, showing the operation in the next vertical period of FIG. . FIG. 17 is a timing chart showing the operation of the data driver circuit of the liquid crystal display device according to the present embodiment with time on the horizontal axis and the potential of each wiring on the vertical axis, showing the operation in the next vertical period of FIG. . 10 is a timing chart showing the operation of the data driver circuit of the liquid crystal display device according to the fifth embodiment of the present invention, with time on the horizontal axis and the potential of each wiring on the vertical axis. FIG. 19 is a timing chart showing the operation of the data driver circuit of the liquid crystal display device according to the sixth embodiment of the present invention, with time on the axis and the potential of each wiring on the vertical axis, and the next vertical period in FIG. The operation in is shown. FIG. 20 is a timing chart showing the operation of the data driver circuit of the liquid crystal display device according to the present embodiment, with time on the horizontal axis and the potential of each wiring on the vertical axis, showing the operation in the next vertical period of FIG. . It is a block diagram which shows the liquid crystal display device which concerns on the 7th Embodiment of this invention. 4 is a timing chart showing the operation of the signal processing circuit in the present embodiment, with time on the horizontal axis and the potential of each wiring on the vertical axis. It is a figure which shows the polarity of the video signal applied to the pixel electrode of each pixel in a certain vertical period. It is a figure which shows the polarity of the video signal applied to the pixel electrode of each pixel in the next vertical period of FIG. It is a timing chart which shows operation | movement of the liquid crystal display device based on the 8th Embodiment of this invention, taking time on a horizontal axis and taking the electric potential of each wiring on a vertical axis | shaft. It is a block diagram which shows the projector apparatus which concerns on the 9th Embodiment of this invention. It is a block diagram which shows the liquid crystal display device which concerns on the 10th Embodiment of this invention. It is a block diagram which shows the conventional liquid crystal display device which uses P-Si-TFT. FIG. 29 is a timing chart showing an operation of the data driver circuit shown in FIG. 28. FIG. FIG. 29 is a timing chart showing an operation of the gate driver circuit shown in FIG. 28. FIG. It is a block diagram which shows the conventional liquid crystal display device using a COG connection. 32 is a timing chart showing an operation of the data line driving IC shown in FIG. 31. FIG. 29 is an equivalent circuit diagram showing a configuration in the vicinity of ASW of the liquid crystal display device that performs block division driving shown in FIG. 28. FIG. 32 is an equivalent circuit diagram showing a configuration in the vicinity of an ASW unit of the liquid crystal display device by the COG connection shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1a; Liquid crystal display device 2; Pixel 3; Data driver circuit 4; Gate driver circuit 5; Data line drive circuit 6; Drive circuit 7; Signal processing circuit 8; Memory 9; 12; TFT side glass substrate 13; Opposite side glass substrate 14; Liquid crystal layer 15; Lower light shielding film 16, 21, 24, 28; Interlayer film 17; Semiconductor layer 18; Gate insulating film 19; Gate metal film 20; 22a to 22d; metal wiring films 23a to 23d, 27; via 25; upper light shielding film 26; metal wiring film 29; through hole 30, 31; alignment film 32; memory 33, 34; frame memory 35, 36 switch 37; Circuit 38; Power supply circuit 41; Projector device 42; Lamps 43 and 46; Color separation mirrors 44, 48 and 49; Mirror 45; Red The liquid crystal display device 47; the green liquid crystal display device 50; the blue liquid crystal display device 51; synthesizing prism 52; projection lens 101; a data driver circuit 102; a gate driver circuits 103 and 104; the shift register 111; data line driving IC
AMP1 to AMP3; amplifiers CIV1 to CIV4; clock inverter Clc; pixel capacitance Cs; storage capacitors D1 to D9; data lines DAC1 to DAC3; DAC circuit DCLK; clock signals DSL1 to DSL9; Data transfer switch DSTP; Start signal Eo; Counter electrode Ep; Pixel electrodes G1 to G6; Gate lines GCLK and / GCLK; Clock signal GST; Start signal HSYNC; Horizontal synchronization signals IV1 to IV6; Inverters M11 to M19 and M21 Memory MW, MR; Memory control signals SL1 to SL3; Control signals SP1 to SP3; Control lines SR1 to SR3; Output signals SW1-1 to SW3-3; Analog switch (ASW)
TB1, TB2, TB3; period TFT; pixel thin film transistor TH; horizontal period TR; control signal TV; vertical period V1 to V3; video signal line VIDEO, VIDEO_IN; video signal VSYNC;

Claims (27)

(N × m) (n and m are integers greater than or equal to 2) data lines and a plurality of gates extending in the column direction divided into m groups for every n adjacent to each other extending in the row direction A gate driver circuit that sequentially selects the gate lines within one vertical period for displaying an image for one screen; a plurality of pixels provided for each proximity point of the data line and the gate line; A data driver circuit that outputs a video signal for one pixel row to the data line in one horizontal period in which the gate driver circuit selects one of the gate lines, and the data driver circuit includes: M number of output terminals provided for each group for outputting the video signal and kth data line for switching whether to connect the kth data line (k is an integer from 1 to n) in each group to the output terminal. And all the kth switches are connected in common. an n-th k-th control line; and a drive circuit that sequentially outputs a control signal for turning on the k-th switch to the k-th control line. A liquid crystal display device characterized in that the order in which the control signals are output to n control lines is varied every predetermined period. 2. The liquid crystal display device according to claim 1, wherein the drive circuit changes an order of outputting the control signals to the n control lines in the horizontal period for each vertical period. . There are n orders of outputting the control signals, and the n ways are n orders in which the last selected switch among n consecutive horizontal periods is different, and the drive circuit is n times 3. The liquid crystal display device according to claim 2, wherein the n orders are repeatedly performed every one cycle of the vertical period. 2. The drive circuit according to claim 1, wherein an order of outputting the control signals to the n control lines in the horizontal period is changed for each of the horizontal periods one or more times. The liquid crystal display device described. There are n orders of outputting the control signals, and the n ways are n orders in which the last selected switch among n consecutive horizontal periods is different, and the drive circuit is n times 5. The liquid crystal display device according to claim 4, wherein the n orders are repeatedly performed for each sub period including the horizontal period. 2. The drive circuit according to claim 1, wherein an order of outputting the control signals to the n control lines in the horizontal period is changed for each of the horizontal periods one or more times. The liquid crystal display device described. The video signal input from the signal processing circuit is stored for at least one screen, and the stored video signal for one screen is input from the signal processing circuit during a period in which the video signal for the next one screen is input. And a signal processing circuit for reading out the read video signal to the data driver circuit t times at a frequency t times (t is an integer equal to or greater than 2). The liquid crystal display device according to any one of 1 to 6. A first substrate on which the data line and the gate line are formed, a second substrate with a liquid crystal layer sandwiched between the first substrate, and the pixel on the first substrate. A pixel electrode to which the video signal is applied from the data line; and a counter electrode provided on the second substrate, wherein the data driver circuit applies the counter electrode to the counter electrode every vertical period. The liquid crystal display device according to claim 7, wherein the video signal having the same polarity is output to the data line. 9. The liquid crystal display device according to claim 7, wherein the value of t is equal to the value of n. The liquid crystal display device according to claim 1, wherein the switch includes a thin film transistor. The liquid crystal display device according to any one of claims 1 to 10, wherein a color filter is not provided. Irradiated by a light source that sequentially emits light of a plurality of colors during the vertical period, the gate driver circuit scans the gate line a plurality of times during the vertical period in synchronization with the operation of the light source. 12. The data driver circuit according to claim 11, wherein the data driver circuit sequentially outputs video signals corresponding to a plurality of color images during the vertical period in synchronization with the operation of the light source. Liquid crystal display device. The liquid crystal display device according to claim 1, further comprising a plurality of color filters extending in the row direction and arranged for each pixel column. 2. A color filter having a plurality of colors extending in the column direction and arranged for each pixel column, wherein the number n of data lines belonging to each set is larger than the number of colors of the color filter. The liquid crystal display device according to any one of 10. A projector apparatus comprising the liquid crystal display device according to claim 1. A light source, separation means for separating the light emitted from the light source into light of a plurality of colors, and the separated light transmitted through the light paths of the separated light. 12. A projector device comprising: a plurality of liquid crystal display devices according to claim 11 for adding an image; and a prism for combining light transmitted through the plurality of liquid crystal display devices. A portable terminal device comprising the liquid crystal display device according to claim 12. (N × m) (n and m are integers greater than or equal to 2) data lines and a plurality of gates extending in the column direction divided into m groups for every n adjacent to each other extending in the row direction In a driving method of a liquid crystal display device comprising: a line; and a plurality of pixels provided at proximity points between the data line and the gate line, the gate line is sequentially selected and the data line is By outputting the video signal, a vertical period in which an image for one screen is displayed on the pixel is repeatedly performed, and for each vertical period, one data line is selected while one gate line is selected. A horizontal period for outputting a video signal for a pixel row is sequentially performed for all the gate lines, and the video signal is transmitted to the kth data line (k is an integer from 1 to n) in each group for each horizontal period. Are sequentially output, and the n number of data are output within the horizontal period. Method of driving a liquid crystal display device, characterized in that the order to output the video signal to the data line, made different at predetermined intervals. 19. The driving method of the liquid crystal display device according to claim 18, wherein the order in which the video signals are output to the n data lines within the horizontal period is different for each vertical period. The order of outputting the video signals is n, and the n ways are n ways in which the last selected switch is different among n consecutive horizontal periods, and the n times from the vertical period. 20. The method of driving a liquid crystal display device according to claim 19, wherein the n orders are repeatedly performed every one cycle. 21. The liquid crystal according to claim 19, wherein a sequence in which the video signals are output to the n data lines within the horizontal period is varied for each of the one or more horizontal periods. A driving method of a display device. The order of outputting the video signal is n, and the n ways are n different orders in which the last selected switch among n consecutive horizontal periods is different from the n horizontal periods. The method of driving a liquid crystal display device according to claim 21, wherein the n number of orders are repeatedly performed for each sub-period. 19. The method of driving a liquid crystal display device according to claim 18, wherein the order in which the video signals are output to the n data lines within the horizontal period is varied for each of the one or more horizontal periods. . The video signal input from the signal processing circuit is stored for at least one screen, and the stored video signal for one screen is input from the signal processing circuit during a period input from the next one screen video signal. 24. The method according to claim 18, wherein the read video signal is read out at a frequency t times (t is an integer equal to or greater than 2), and the read video signal is output to the data driver circuit t times. 2. A method for driving a liquid crystal display device according to item 1. The liquid crystal display device includes a first substrate on which the data lines and the gate lines are formed, a second substrate that sandwiches a liquid crystal layer between the first substrate, and the first substrate. A pixel electrode provided for each of the pixels to which the video signal is applied from the data line; and a counter electrode provided on the second substrate. 25. The driving method of a liquid crystal display device according to claim 24, wherein the video signal having the same polarity with respect to the counter electrode is output to the data line. 26. The method of driving a liquid crystal display device according to claim 24, wherein the value of t is equal to the value of n. The liquid crystal display device is sequentially irradiated with light of a plurality of colors during the vertical period, and in synchronization with the irradiation, the gate line is scanned a plurality of times during the vertical period, and a video corresponding to an image of a plurality of colors 27. The method of driving a liquid crystal display device according to claim 18, wherein the signals are sequentially output.

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