JP2002526860A - マルチプロセッサ環境において正しいプロセッサのための入出力命令をエミュレートし、ソフトウェアｓｍｉをサービスするための装置及び方法 - Google Patents

マルチプロセッサ環境において正しいプロセッサのための入出力命令をエミュレートし、ソフトウェアｓｍｉをサービスするための装置及び方法

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Publication number
JP2002526860A
JP2002526860A JP2000575034A JP2000575034A JP2002526860A JP 2002526860 A JP2002526860 A JP 2002526860A JP 2000575034 A JP2000575034 A JP 2000575034A JP 2000575034 A JP2000575034 A JP 2000575034A JP 2002526860 A JP2002526860 A JP 2002526860A
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JP
Japan
Prior art keywords
processor
instruction
input
smi
output
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000575034A
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English (en)
Japanese (ja)
Inventor
カサノ，アンソニー・ポール
エドリッチ，デイビッド・スティーブン
Original Assignee
フィーニックス テクノロジーズ リミテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by フィーニックス テクノロジーズ リミテッド filed Critical フィーニックス テクノロジーズ リミテッド
Publication of JP2002526860A publication Critical patent/JP2002526860A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45537—Provision of facilities of other operating environments, e.g. WINE

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Debugging And Monitoring (AREA)
JP2000575034A 1998-10-01 1999-10-01 マルチプロセッサ環境において正しいプロセッサのための入出力命令をエミュレートし、ソフトウェアｓｍｉをサービスするための装置及び方法 Pending JP2002526860A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/164,347 US6571206B1 (en) 1998-01-15 1998-10-01 Apparatus and method for emulating an I/O instruction for the correct processor and for servicing software SMI's in a multi-processor environment
US09/164,347 1998-10-01
PCT/US1999/020899 WO2000020977A1 (fr) 1998-10-01 1999-10-01 Appareil et procede pour l'emulation d'une instruction i/o pour le processeur correct et pour la maintenance d'un systeme logiciel smi dans un environnement multiprocesseur

Publications (1)

Publication Number Publication Date
JP2002526860A true JP2002526860A (ja) 2002-08-20

Family

ID=22594084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000575034A Pending JP2002526860A (ja) 1998-10-01 1999-10-01 マルチプロセッサ環境において正しいプロセッサのための入出力命令をエミュレートし、ソフトウェアｓｍｉをサービスするための装置及び方法

Country Status (5)

Country Link
US (1) US6571206B1 (fr)
JP (1) JP2002526860A (fr)
AU (1) AU6386999A (fr)
TW (1) TW470885B (fr)
WO (1) WO2000020977A1 (fr)

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JP2005013799A (ja) * 2003-06-24 2005-01-20 Ishigaki Co Ltd 懸濁物質の凝集処理方法

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US6697901B1 (en) * 2000-10-24 2004-02-24 Oracle International Corporation Using secondary resource masters in conjunction with a primary resource master for managing resources that are accessible to a plurality of entities
US20020099893A1 (en) * 2001-01-24 2002-07-25 Nguyen Tuyet-Huong Thi System and method for the handling of system management interrupts in a multiprocessor computer system
US6968410B2 (en) * 2001-02-28 2005-11-22 Intel Corporation Multi-threaded processing of system management interrupts
TW498213B (en) * 2001-04-18 2002-08-11 Via Tech Inc Method and chipset for supporting interrupts of system management mode in multiple-CPU system
JP4005026B2 (ja) 2001-12-13 2007-11-07 株式会社ソニー・コンピュータエンタテインメント プログラムのセキュアな配布方法及び装置
WO2003055132A1 (fr) 2001-12-21 2003-07-03 Sony Computer Entertainment Inc. Procedes et appareil de distribution securisee de contenu de programme
US7243353B2 (en) * 2002-06-28 2007-07-10 Intel Corporation Method and apparatus for making and using a flexible hardware interface
US7698689B2 (en) 2002-08-13 2010-04-13 Phoenix Technologies Ltd. Method for meeting SMI duration limits by time slicing SMI handlers
US20050066097A1 (en) * 2003-09-04 2005-03-24 Matsushita Electric Industrial Co., Ltd. Resource management apparatus
TW200401188A (en) * 2003-09-16 2004-01-16 Via Tech Inc Debug device and method thereof
US7340547B1 (en) * 2003-12-02 2008-03-04 Nvidia Corporation Servicing of multiple interrupts using a deferred procedure call in a multiprocessor system
US20050154573A1 (en) * 2004-01-08 2005-07-14 Maly John W. Systems and methods for initializing a lockstep mode test case simulation of a multi-core processor design
US7197433B2 (en) * 2004-04-09 2007-03-27 Hewlett-Packard Development Company, L.P. Workload placement among data centers based on thermal efficiency
CN1906576B (zh) 2004-09-20 2010-05-12 索尼计算机娱乐公司 分布软件应用的方法与设备
US20060282589A1 (en) * 2005-06-08 2006-12-14 Dell Products L.P. System and method of processing system management interrupts (SMI) in a multi-processor environment
US7464211B2 (en) * 2006-09-14 2008-12-09 International Business Machines Corporation Method of detecting and recovering a lost system management interrupt (SMI) in a multiprocessor (MP) environment
US7721034B2 (en) * 2006-09-29 2010-05-18 Dell Products L.P. System and method for managing system management interrupts in a multiprocessor computer system
TW201025015A (en) * 2008-12-30 2010-07-01 Wistron Corp Method for safely removing an external image processing device for a computer system and related computer system
US8578138B2 (en) 2009-08-31 2013-11-05 Intel Corporation Enabling storage of active state in internal storage of processor rather than in SMRAM upon entry to system management mode
DE102010011583B4 (de) * 2010-03-16 2011-12-22 Fujitsu Technology Solutions Intellectual Property Gmbh Verfahren zum Umsetzen von Befehlen mit Basisregister-relativer Adressierung bei einer Emulation
CN108717387B (zh) * 2012-11-09 2021-09-07 相干逻辑公司 对于多处理器系统的实时分析和控制
TW201533576A (zh) * 2013-11-20 2015-09-01 Insyde Software Corp 在多核心系統上運用系統管理中斷（ｓｍｉ）之系統效能增強
US11188640B1 (en) * 2018-08-23 2021-11-30 Advanced Micro Devices, Inc. Platform firmware isolation

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JPS62160561A (ja) * 1986-01-10 1987-07-16 Hitachi Ltd プロセツサ間通信方式
JPH03171250A (ja) * 1989-05-17 1991-07-24 Internatl Business Mach Corp <Ibm> コンピュータ・システム
JPH0628321A (ja) * 1992-04-22 1994-02-04 Toshiba Corp マルチプロセッサシステム
JPH07175665A (ja) * 1993-12-17 1995-07-14 Fujitsu Ltd 入出力割込制御回路
JPH07200496A (ja) * 1993-12-28 1995-08-04 Fujitsu Ltd プロセッサ割当て方式
WO1997013202A1 (fr) * 1995-10-06 1997-04-10 Advanced Micro Devices, Inc. Mise en application souple d'un mode de gestion de systeme (smm) dans un processeur
JPH10143387A (ja) * 1996-10-29 1998-05-29 Compaq Computer Corp 障害診断機能付きのコンピュータ・システム
JPH10187589A (ja) * 1996-10-18 1998-07-21 Compaq Computer Corp キーボード用ホットプラグ

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KR950008837B1 (ko) 1990-03-09 1995-08-08 후지쓰 가부시끼가이샤 멀티 프로세서 시스템용 제어시스템
JPH05216712A (ja) 1991-10-23 1993-08-27 Internatl Business Mach Corp <Ibm> コンピュータシステムおよびこのコンピュータシステム上で内観的タスクを遂行する方法並びにｉ／ｏプロセッサアセンブリ
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US5796984A (en) 1996-01-26 1998-08-18 Dell Usa, L.P. Operating system independent apparatus and method for eliminating peripheral device functions
US6003129A (en) * 1996-08-19 1999-12-14 Samsung Electronics Company, Ltd. System and method for handling interrupt and exception events in an asymmetric multiprocessor architecture
US5889978A (en) * 1997-04-18 1999-03-30 Intel Corporation Emulation of interrupt control mechanism in a multiprocessor system
US6321279B1 (en) * 1998-09-14 2001-11-20 Compaq Computer Corporation System for implementing intelligent I/O processing in a multi-processor system by redirecting I/O messages to a target central processor selected from the multi-processor system
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Patent Citations (9)

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Publication number Priority date Publication date Assignee Title
JPS62160561A (ja) * 1986-01-10 1987-07-16 Hitachi Ltd プロセツサ間通信方式
JPH03171250A (ja) * 1989-05-17 1991-07-24 Internatl Business Mach Corp <Ibm> コンピュータ・システム
JPH0628321A (ja) * 1992-04-22 1994-02-04 Toshiba Corp マルチプロセッサシステム
JPH07175665A (ja) * 1993-12-17 1995-07-14 Fujitsu Ltd 入出力割込制御回路
JPH07200496A (ja) * 1993-12-28 1995-08-04 Fujitsu Ltd プロセッサ割当て方式
WO1997013202A1 (fr) * 1995-10-06 1997-04-10 Advanced Micro Devices, Inc. Mise en application souple d'un mode de gestion de systeme (smm) dans un processeur
JP2000506636A (ja) * 1995-10-06 2000-05-30 アドバンスト・マイクロ・デバイシズ・インコーポレイテッド プロセッサにおけるシステム管理モード（ｓｍｍ）のフレキシブルな実現
JPH10187589A (ja) * 1996-10-18 1998-07-21 Compaq Computer Corp キーボード用ホットプラグ
JPH10143387A (ja) * 1996-10-29 1998-05-29 Compaq Computer Corp 障害診断機能付きのコンピュータ・システム

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005013799A (ja) * 2003-06-24 2005-01-20 Ishigaki Co Ltd 懸濁物質の凝集処理方法

Also Published As

Publication number Publication date
WO2000020977A9 (fr) 2000-08-24
AU6386999A (en) 2000-04-26
TW470885B (en) 2002-01-01
US6571206B1 (en) 2003-05-27
WO2000020977A1 (fr) 2000-04-13

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