JP2002521845A - 埋込みローカル配線 - Google Patents

埋込みローカル配線

Info

Publication number
JP2002521845A
JP2002521845A JP2000562953A JP2000562953A JP2002521845A JP 2002521845 A JP2002521845 A JP 2002521845A JP 2000562953 A JP2000562953 A JP 2000562953A JP 2000562953 A JP2000562953 A JP 2000562953A JP 2002521845 A JP2002521845 A JP 2002521845A
Authority
JP
Japan
Prior art keywords
layer
insulating layer
trench
substrate
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000562953A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002521845A5 (https=
Inventor
ホーズ，フレデリック・エヌ
ガードナー，マーク・アイ
メイ，チャールズ・イー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2002521845A publication Critical patent/JP2002521845A/ja
Publication of JP2002521845A5 publication Critical patent/JP2002521845A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2000562953A 1998-07-27 1999-02-05 埋込みローカル配線 Pending JP2002521845A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/123,177 1998-07-27
US09/123,177 US6261908B1 (en) 1998-07-27 1998-07-27 Buried local interconnect
PCT/US1999/002459 WO2000007241A1 (en) 1998-07-27 1999-02-05 Buried local interconnect

Publications (2)

Publication Number Publication Date
JP2002521845A true JP2002521845A (ja) 2002-07-16
JP2002521845A5 JP2002521845A5 (https=) 2006-03-09

Family

ID=22407146

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000562953A Pending JP2002521845A (ja) 1998-07-27 1999-02-05 埋込みローカル配線

Country Status (5)

Country Link
US (1) US6261908B1 (https=)
EP (1) EP1114458A1 (https=)
JP (1) JP2002521845A (https=)
KR (1) KR100615658B1 (https=)
WO (1) WO2000007241A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003045957A (ja) * 2001-05-18 2003-02-14 Samsung Electronics Co Ltd 半導体装置の素子分離方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100557943B1 (ko) * 2000-06-30 2006-03-10 주식회사 하이닉스반도체 플라즈마공정에 의한 에스티아이 공정의 특성개선방법
US7081398B2 (en) * 2001-10-12 2006-07-25 Micron Technology, Inc. Methods of forming a conductive line
US6828199B2 (en) 2001-12-20 2004-12-07 Advanced Micro Devices, Ltd. Monos device having buried metal silicide bit line
US6825097B2 (en) 2002-08-07 2004-11-30 International Business Machines Corporation Triple oxide fill for trench isolation
US6894915B2 (en) 2002-11-15 2005-05-17 Micron Technology, Inc. Method to prevent bit line capacitive coupling
US6734482B1 (en) * 2002-11-15 2004-05-11 Micron Technology, Inc. Trench buried bit line memory devices
JP2004221204A (ja) * 2003-01-10 2004-08-05 Oki Electric Ind Co Ltd 半導体装置の製造方法
DE102004024659B4 (de) 2004-05-18 2014-10-02 Infineon Technologies Ag Halbleiterbauteil
US7093989B2 (en) 2004-05-27 2006-08-22 Silverbrook Research Pty Ltd Printer comprising two uneven printhead modules and at least two printer controllers, one which spends print data to the other
KR100577312B1 (ko) * 2004-07-05 2006-05-10 동부일렉트로닉스 주식회사 씨모스 이미지 센서의 포토트랜지스터 및 그 제조 방법
US7118966B2 (en) * 2004-08-23 2006-10-10 Micron Technology, Inc. Methods of forming conductive lines
US7786003B1 (en) 2005-05-25 2010-08-31 Advanced Micro Devices, Inc. Buried silicide local interconnect with sidewall spacers and method for making the same
US7754522B2 (en) * 2008-08-06 2010-07-13 Micron Technology, Inc. Phase change memory structures and methods
US8492819B2 (en) 2011-07-14 2013-07-23 International Business Machines Corporation FET eDRAM trench self-aligned to buried strap
US20150145041A1 (en) * 2013-11-22 2015-05-28 International Business Machines Corporation Substrate local interconnect integration with finfets
US11183419B2 (en) 2020-03-17 2021-11-23 International Business Machines Corporation Unconfined buried interconnects
CN117334668A (zh) * 2022-06-16 2024-01-02 长鑫存储技术有限公司 半导体结构及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6265346A (ja) * 1985-09-17 1987-03-24 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH09307059A (ja) * 1996-05-16 1997-11-28 Toshiba Corp モノリシック集積回路

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4683486A (en) 1984-09-24 1987-07-28 Texas Instruments Incorporated dRAM cell and array
US5100823A (en) * 1988-02-29 1992-03-31 Motorola, Inc. Method of making buried stacked transistor-capacitor
US5070388A (en) 1990-01-19 1991-12-03 Harris Corporation Trench-resident interconnect structure
US5196373A (en) 1990-08-06 1993-03-23 Harris Corporation Method of making trench conductor and crossunder architecture
JPH04328860A (ja) * 1991-04-30 1992-11-17 Hitachi Ltd 半導体集積回路装置及びその製造方法
US5274965A (en) * 1992-02-06 1994-01-04 Gutter-Clean Hinge Company Inverting rain gutter
US5268326A (en) * 1992-09-28 1993-12-07 Motorola, Inc. Method of making dielectric and conductive isolated island
US5275965A (en) * 1992-11-25 1994-01-04 Micron Semiconductor, Inc. Trench isolation using gated sidewalls
US5429977A (en) 1994-03-11 1995-07-04 Industrial Technology Research Institute Method for forming a vertical transistor with a stacked capacitor DRAM cell
US5627092A (en) * 1994-09-26 1997-05-06 Siemens Aktiengesellschaft Deep trench dram process on SOI for low leakage DRAM cell
JPH08250677A (ja) 1994-12-28 1996-09-27 Nippon Steel Corp 半導体記憶装置及びその製造方法
US5545583A (en) 1995-04-13 1996-08-13 International Business Machines Corporation Method of making semiconductor trench capacitor cell having a buried strap
KR0144899B1 (ko) * 1995-04-25 1998-07-01 김광호 매몰 비트라인 디램 셀 및 그 제조방법
US5610441A (en) * 1995-05-19 1997-03-11 International Business Machines Corporation Angle defined trench conductor for a semiconductor device
US5859466A (en) 1995-06-07 1999-01-12 Nippon Steel Semiconductor Corporation Semiconductor device having a field-shield device isolation structure and method for making thereof
US6020230A (en) * 1998-04-22 2000-02-01 Texas Instruments-Acer Incorporated Process to fabricate planarized deep-shallow trench isolation having upper and lower portions with oxidized semiconductor trench fill in the upper portion and semiconductor trench fill in the lower portion

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6265346A (ja) * 1985-09-17 1987-03-24 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH09307059A (ja) * 1996-05-16 1997-11-28 Toshiba Corp モノリシック集積回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003045957A (ja) * 2001-05-18 2003-02-14 Samsung Electronics Co Ltd 半導体装置の素子分離方法

Also Published As

Publication number Publication date
US6261908B1 (en) 2001-07-17
WO2000007241A1 (en) 2000-02-10
EP1114458A1 (en) 2001-07-11
KR20010071967A (ko) 2001-07-31
KR100615658B1 (ko) 2006-08-25

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