KR100615658B1 - 매립된 국부 배선 - Google Patents

매립된 국부 배선 Download PDF

Info

Publication number
KR100615658B1
KR100615658B1 KR1020017000785A KR20017000785A KR100615658B1 KR 100615658 B1 KR100615658 B1 KR 100615658B1 KR 1020017000785 A KR1020017000785 A KR 1020017000785A KR 20017000785 A KR20017000785 A KR 20017000785A KR 100615658 B1 KR100615658 B1 KR 100615658B1
Authority
KR
South Korea
Prior art keywords
layer
local wiring
insulating layer
trench
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020017000785A
Other languages
English (en)
Korean (ko)
Other versions
KR20010071967A (ko
Inventor
하우스프레드릭엔.
가드너마크아이.
메이찰스이.
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20010071967A publication Critical patent/KR20010071967A/ko
Application granted granted Critical
Publication of KR100615658B1 publication Critical patent/KR100615658B1/ko
Assigned to 글로벌파운드리즈 인크. reassignment 글로벌파운드리즈 인크. 권리의 전부이전등록 Assignors: 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020017000785A 1998-07-27 1999-02-05 매립된 국부 배선 Expired - Fee Related KR100615658B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/123,177 1998-07-27
US09/123,177 US6261908B1 (en) 1998-07-27 1998-07-27 Buried local interconnect

Publications (2)

Publication Number Publication Date
KR20010071967A KR20010071967A (ko) 2001-07-31
KR100615658B1 true KR100615658B1 (ko) 2006-08-25

Family

ID=22407146

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020017000785A Expired - Fee Related KR100615658B1 (ko) 1998-07-27 1999-02-05 매립된 국부 배선

Country Status (5)

Country Link
US (1) US6261908B1 (https=)
EP (1) EP1114458A1 (https=)
JP (1) JP2002521845A (https=)
KR (1) KR100615658B1 (https=)
WO (1) WO2000007241A1 (https=)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100557943B1 (ko) * 2000-06-30 2006-03-10 주식회사 하이닉스반도체 플라즈마공정에 의한 에스티아이 공정의 특성개선방법
US20020197823A1 (en) * 2001-05-18 2002-12-26 Yoo Jae-Yoon Isolation method for semiconductor device
US7081398B2 (en) * 2001-10-12 2006-07-25 Micron Technology, Inc. Methods of forming a conductive line
US6828199B2 (en) 2001-12-20 2004-12-07 Advanced Micro Devices, Ltd. Monos device having buried metal silicide bit line
US6825097B2 (en) 2002-08-07 2004-11-30 International Business Machines Corporation Triple oxide fill for trench isolation
US6894915B2 (en) 2002-11-15 2005-05-17 Micron Technology, Inc. Method to prevent bit line capacitive coupling
US6734482B1 (en) * 2002-11-15 2004-05-11 Micron Technology, Inc. Trench buried bit line memory devices
JP2004221204A (ja) * 2003-01-10 2004-08-05 Oki Electric Ind Co Ltd 半導体装置の製造方法
DE102004024659B4 (de) 2004-05-18 2014-10-02 Infineon Technologies Ag Halbleiterbauteil
US7093989B2 (en) 2004-05-27 2006-08-22 Silverbrook Research Pty Ltd Printer comprising two uneven printhead modules and at least two printer controllers, one which spends print data to the other
KR100577312B1 (ko) * 2004-07-05 2006-05-10 동부일렉트로닉스 주식회사 씨모스 이미지 센서의 포토트랜지스터 및 그 제조 방법
US7118966B2 (en) * 2004-08-23 2006-10-10 Micron Technology, Inc. Methods of forming conductive lines
US7786003B1 (en) 2005-05-25 2010-08-31 Advanced Micro Devices, Inc. Buried silicide local interconnect with sidewall spacers and method for making the same
US7754522B2 (en) * 2008-08-06 2010-07-13 Micron Technology, Inc. Phase change memory structures and methods
US8492819B2 (en) 2011-07-14 2013-07-23 International Business Machines Corporation FET eDRAM trench self-aligned to buried strap
US20150145041A1 (en) * 2013-11-22 2015-05-28 International Business Machines Corporation Substrate local interconnect integration with finfets
US11183419B2 (en) 2020-03-17 2021-11-23 International Business Machines Corporation Unconfined buried interconnects
CN117334668A (zh) * 2022-06-16 2024-01-02 长鑫存储技术有限公司 半导体结构及其制备方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5070388A (en) * 1990-01-19 1991-12-03 Harris Corporation Trench-resident interconnect structure

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4683486A (en) 1984-09-24 1987-07-28 Texas Instruments Incorporated dRAM cell and array
JPS6265346A (ja) * 1985-09-17 1987-03-24 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US5100823A (en) * 1988-02-29 1992-03-31 Motorola, Inc. Method of making buried stacked transistor-capacitor
US5196373A (en) 1990-08-06 1993-03-23 Harris Corporation Method of making trench conductor and crossunder architecture
JPH04328860A (ja) * 1991-04-30 1992-11-17 Hitachi Ltd 半導体集積回路装置及びその製造方法
US5274965A (en) * 1992-02-06 1994-01-04 Gutter-Clean Hinge Company Inverting rain gutter
US5268326A (en) * 1992-09-28 1993-12-07 Motorola, Inc. Method of making dielectric and conductive isolated island
US5275965A (en) * 1992-11-25 1994-01-04 Micron Semiconductor, Inc. Trench isolation using gated sidewalls
US5429977A (en) 1994-03-11 1995-07-04 Industrial Technology Research Institute Method for forming a vertical transistor with a stacked capacitor DRAM cell
US5627092A (en) * 1994-09-26 1997-05-06 Siemens Aktiengesellschaft Deep trench dram process on SOI for low leakage DRAM cell
JPH08250677A (ja) 1994-12-28 1996-09-27 Nippon Steel Corp 半導体記憶装置及びその製造方法
US5545583A (en) 1995-04-13 1996-08-13 International Business Machines Corporation Method of making semiconductor trench capacitor cell having a buried strap
KR0144899B1 (ko) * 1995-04-25 1998-07-01 김광호 매몰 비트라인 디램 셀 및 그 제조방법
US5610441A (en) * 1995-05-19 1997-03-11 International Business Machines Corporation Angle defined trench conductor for a semiconductor device
US5859466A (en) 1995-06-07 1999-01-12 Nippon Steel Semiconductor Corporation Semiconductor device having a field-shield device isolation structure and method for making thereof
JP3719774B2 (ja) * 1996-05-16 2005-11-24 株式会社東芝 モノリシック集積回路
US6020230A (en) * 1998-04-22 2000-02-01 Texas Instruments-Acer Incorporated Process to fabricate planarized deep-shallow trench isolation having upper and lower portions with oxidized semiconductor trench fill in the upper portion and semiconductor trench fill in the lower portion

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5070388A (en) * 1990-01-19 1991-12-03 Harris Corporation Trench-resident interconnect structure

Also Published As

Publication number Publication date
US6261908B1 (en) 2001-07-17
WO2000007241A1 (en) 2000-02-10
EP1114458A1 (en) 2001-07-11
KR20010071967A (ko) 2001-07-31
JP2002521845A (ja) 2002-07-16

Similar Documents

Publication Publication Date Title
KR100615658B1 (ko) 매립된 국부 배선
US8951910B2 (en) Methods for fabricating and forming semiconductor device structures including damascene structures
US5674781A (en) Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC application
US5677563A (en) Gate stack structure of a field effect transistor
US7704811B2 (en) Sub-lithographics opening for back contact or back gate
US6184127B1 (en) Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure
US6180509B1 (en) Method for forming planarized multilevel metallization in an integrated circuit
EP0534631B1 (en) Method of forming vias structure obtained
US5970375A (en) Semiconductor fabrication employing a local interconnect
US6140674A (en) Buried trench capacitor
US6228767B1 (en) Non-linear circuit elements on integrated circuits
US8368219B2 (en) Buried silicide local interconnect with sidewall spacers and method for making the same
US5895961A (en) Semiconductor device with a planarized interconnect with poly-plug and self-aligned contacts
US6399480B1 (en) Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction
US6300666B1 (en) Method for forming a frontside contact to the silicon substrate of a SOI wafer in the presence of planarized contact dielectrics
US6114251A (en) Method of fabrication for ultra thin nitride liner in silicon trench isolation
US5904559A (en) Three dimensional contact or via structure with multiple sidewall contacts
US5471094A (en) Self-aligned via structure
US6380082B2 (en) Method of fabricating Cu interconnects with reduced Cu contamination
US5923584A (en) Dual poly integrated circuit interconnect
US6087252A (en) Dual damascene
US6025272A (en) Method of planarize and improve the effectiveness of the stop layer
US6297144B1 (en) Damascene local interconnect process
JPH11186274A (ja) デュアル・ダマスク技術
US6323540B1 (en) Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure

Legal Events

Date Code Title Description
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 20120727

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

FPAY Annual fee payment

Payment date: 20130723

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

FPAY Annual fee payment

Payment date: 20140722

Year of fee payment: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

FPAY Annual fee payment

Payment date: 20150717

Year of fee payment: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

FPAY Annual fee payment

Payment date: 20160720

Year of fee payment: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

FPAY Annual fee payment

Payment date: 20170719

Year of fee payment: 12

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 12

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20180818

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20180818

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000