JP2002359316A - 半導体チップ搭載基板及びそれを用いた半導体装置 - Google Patents

半導体チップ搭載基板及びそれを用いた半導体装置

Info

Publication number
JP2002359316A
JP2002359316A JP2002064208A JP2002064208A JP2002359316A JP 2002359316 A JP2002359316 A JP 2002359316A JP 2002064208 A JP2002064208 A JP 2002064208A JP 2002064208 A JP2002064208 A JP 2002064208A JP 2002359316 A JP2002359316 A JP 2002359316A
Authority
JP
Japan
Prior art keywords
chip mounting
semiconductor chip
semiconductor
conductive pads
groups
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP2002064208A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002359316A5 (https=
Inventor
Takuya Takahashi
拓也 高橋
Tadaharu Hashiguchi
忠治 橋口
Kazuhiro Yamamoto
和博 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2002064208A priority Critical patent/JP2002359316A/ja
Priority to US10/105,366 priority patent/US6803666B2/en
Publication of JP2002359316A publication Critical patent/JP2002359316A/ja
Publication of JP2002359316A5 publication Critical patent/JP2002359316A5/ja
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/699—Insulating or insulated package substrates; Interposers; Redistribution layers for flat cards, e.g. credit cards
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/656—Fan-in layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view

Landscapes

  • Wire Bonding (AREA)
JP2002064208A 2001-03-27 2002-03-08 半導体チップ搭載基板及びそれを用いた半導体装置 Abandoned JP2002359316A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002064208A JP2002359316A (ja) 2001-03-27 2002-03-08 半導体チップ搭載基板及びそれを用いた半導体装置
US10/105,366 US6803666B2 (en) 2001-03-27 2002-03-26 Semiconductor chip mounting substrate and semiconductor device using the same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001090951 2001-03-27
JP2001-90951 2001-03-27
JP2002064208A JP2002359316A (ja) 2001-03-27 2002-03-08 半導体チップ搭載基板及びそれを用いた半導体装置

Publications (2)

Publication Number Publication Date
JP2002359316A true JP2002359316A (ja) 2002-12-13
JP2002359316A5 JP2002359316A5 (https=) 2005-09-02

Family

ID=26612237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002064208A Abandoned JP2002359316A (ja) 2001-03-27 2002-03-08 半導体チップ搭載基板及びそれを用いた半導体装置

Country Status (2)

Country Link
US (1) US6803666B2 (https=)
JP (1) JP2002359316A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007214582A (ja) * 2007-03-29 2007-08-23 Sharp Corp 半導体装置およびインターポーザチップ

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4615189B2 (ja) 2003-01-29 2011-01-19 シャープ株式会社 半導体装置およびインターポーザチップ
JP4037332B2 (ja) * 2003-07-10 2008-01-23 シャープ株式会社 Ｉｃモジュールおよびｉｃカード
US8649820B2 (en) 2011-11-07 2014-02-11 Blackberry Limited Universal integrated circuit card apparatus and related methods
USD703208S1 (en) 2012-04-13 2014-04-22 Blackberry Limited UICC apparatus
US8936199B2 (en) 2012-04-13 2015-01-20 Blackberry Limited UICC apparatus and related methods
USD701864S1 (en) * 2012-04-23 2014-04-01 Blackberry Limited UICC apparatus
US9305876B2 (en) * 2013-02-01 2016-04-05 Infineon Technologies Austria Ag Device including a semiconductor chip and wires
CN107025481B (zh) * 2016-02-02 2021-08-20 上海伯乐电子有限公司 柔性印制电路板及应用其的智能卡模块和智能卡
US10541010B2 (en) * 2018-03-19 2020-01-21 Micron Technology, Inc. Memory device with configurable input/output interface

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5216278A (en) * 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007214582A (ja) * 2007-03-29 2007-08-23 Sharp Corp 半導体装置およびインターポーザチップ

Also Published As

Publication number Publication date
US20020140110A1 (en) 2002-10-03
US6803666B2 (en) 2004-10-12

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