JP2002299822A - Low-temperature baked ceramic circuit board - Google Patents

Low-temperature baked ceramic circuit board

Info

Publication number
JP2002299822A
JP2002299822A JP2001097957A JP2001097957A JP2002299822A JP 2002299822 A JP2002299822 A JP 2002299822A JP 2001097957 A JP2001097957 A JP 2001097957A JP 2001097957 A JP2001097957 A JP 2001097957A JP 2002299822 A JP2002299822 A JP 2002299822A
Authority
JP
Japan
Prior art keywords
dielectric layers
conductor
circuit board
hole
hole conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001097957A
Other languages
Japanese (ja)
Other versions
JP4593817B2 (en
Inventor
Tsutomu Oda
勉 小田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001097957A priority Critical patent/JP4593817B2/en
Publication of JP2002299822A publication Critical patent/JP2002299822A/en
Application granted granted Critical
Publication of JP4593817B2 publication Critical patent/JP4593817B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

PROBLEM TO BE SOLVED: To provide a low-temperature baked circuit board that can suppress the protrusion of via-hole conductors from its surface even when two kinds of dielectric layers having different sintering starting temperatures are integrally baked. SOLUTION: This low-temperature baked circuit board is composed of two different kinds of first and second dielectric layers 1a, 1b, and 2a-2c, and first and second via-hole conductors 31 and 32 formed through the dielectric layers 1a, 1b, and 2a-2b in the thickness direction and containing Ag as the chief ingredient. The second dielectric layers 2a-2c have higher sintering starting temperatures than the first dielectric layers 1a and 1b have. In addition, the first via-hole conductors 31 contain MoO3 in amounts of 2-5 pts.wt. in the Ag- based material and the second via-hole conductors 32 contain Ru2 O in amounts of 2-5 pts.wt. in the Ag-based material.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、積層された複数の
誘電体層間に内部配線導体及び各層間の接続用に形成し
たビアホール導体を配して成る低温焼成セラミック回路
基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-temperature fired ceramic circuit board in which internal wiring conductors and via-hole conductors formed for connection between layers are arranged between a plurality of stacked dielectric layers.

【0002】[0002]

【従来の技術】従来より、焼成温度を800〜1050
℃と比較的低い温度で焼成可能な材料を用いた回路基板
が広く提案されている。
2. Description of the Related Art Conventionally, a firing temperature of 800 to 1050 has been used.
A circuit board using a material that can be fired at a relatively low temperature of ° C. has been widely proposed.

【0003】回路基板は、複数の誘電体層を積層した基
板と、該積層体の各誘電体層間に配置した内部配線導体
と、該積層体の表面に配置した表面配線導体と、各誘電
体層の厚み方向に所定内部配線導体間、所定内部配線導
体と表面配線導体との間を接続するビアホール導体とか
ら構成されている。
[0003] The circuit board includes a substrate on which a plurality of dielectric layers are laminated, an internal wiring conductor disposed between the dielectric layers of the laminated body, a surface wiring conductor disposed on the surface of the laminated body, and each dielectric layer. It is composed of via-hole conductors that connect between predetermined internal wiring conductors in the layer thickness direction and between the predetermined internal wiring conductor and the surface wiring conductor.

【0004】なお、積層体の表面に配置した表面配線導
体には、ICチップを始め、各種電子部品が搭載されて
いる。
[0004] Various electronic components such as an IC chip are mounted on the surface wiring conductor arranged on the surface of the laminate.

【0005】上述の内部配線導体の導電率を高めて回路
の高速化を行うために、内部配線導体、ビアホール導
体、表面配線導体としては、金属成分がAg単体または
Ag−Pd、Ag−PtなどのAg合金から成るAg系
材料が使用されている。また、誘電体層としては、上述
のAg系導体のAgの融点から、低温(800〜105
0℃)で焼成可能な材料が用いられている。例えば、ガ
ラス成分とセラミック成分とから成る材料である。
In order to increase the conductivity of the above-mentioned internal wiring conductors to increase the circuit speed, the internal wiring conductors, via-hole conductors and surface wiring conductors may be composed of Ag alone or Ag-Pd, Ag-Pt, or the like. Ag-based material composed of the above Ag alloy is used. In addition, the dielectric layer may be formed at a low temperature (800 to 105) based on the melting point of Ag of the Ag-based conductor described above.
(0 ° C.). For example, a material composed of a glass component and a ceramic component.

【0006】[0006]

【発明が解決しようとする課題】ところで、電子機器の
小型、高機能化が進み、回路基板内にコンデンサ、フィ
ルターなどの素子を効率良く内蔵し、かつ、内蔵素子の
特性向上の要求が強まっている。
By the way, as electronic devices have become smaller and more sophisticated, there has been a growing demand for efficiently incorporating elements such as capacitors and filters in a circuit board and improving the characteristics of the built-in elements. I have.

【0007】しかしながら、焼結開始温度の異なる2種
類のガラス−セラミック材料などの誘電体層を積層して
一体的に焼成すると、収縮挙動に差が生じることによ
り、基板表面におけるビアホール導体の表面が突出して
しまい、その結果、基板表面の配線導体が形成できず、
また、電子部品素子の実装ができなくなる問題点があっ
た。
However, when two types of dielectric layers such as glass-ceramic materials having different sintering start temperatures are laminated and fired integrally, a difference occurs in the shrinkage behavior, so that the surface of the via-hole conductor on the substrate surface is reduced. As a result, the wiring conductor on the board surface cannot be formed,
In addition, there has been a problem that the electronic component element cannot be mounted.

【0008】これは、焼結開始温度が相違する誘電体層
を積層して焼結すると、誘電体層の収縮差による応力
が、積層方向に集中し、基板表面におけるビアホール導
体及びその周囲の誘電体層が突起することになる。
[0008] This is because when dielectric layers having different sintering start temperatures are laminated and sintered, the stress due to the difference in contraction of the dielectric layers is concentrated in the laminating direction, and the via-hole conductor on the substrate surface and the dielectric around the via-hole conductor. The body layer will protrude.

【0009】仮に、基板の表面にビアホール導体が露出
していない状態であっても、その応力はビアホール導体
の直上の基板表面を押し上げるように突出してしまう。
Even if the via-hole conductor is not exposed on the surface of the substrate, the stress protrudes to push up the substrate surface immediately above the via-hole conductor.

【0010】本発明は、上述の問題に鑑みて案出された
ものであり、その目的は、焼結開始温度の異なる2種類
の誘電体層を一体的に焼成しても、基板表面からビアホ
ール導体の突起を抑えることができる回路基板を提供す
るものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object the purpose of forming via holes from the substrate surface even when two types of dielectric layers having different sintering start temperatures are integrally fired. An object of the present invention is to provide a circuit board capable of suppressing protrusions of a conductor.

【0011】[0011]

【課題を解決するための手段】本発明は、焼結開始温度
が異なる2種類の第1、第2の誘電体層を積層するとと
もに、前記第1、第2の誘電体層の層間に内部配線導体
を配置し、且つ第1の誘電体層に第1のビアホール導体
を、第2の誘電体層に第2のビアホール導体を夫々配置
して成る低温焼成セラミック回路基板であって、前記第
2の誘電体層は、第1の誘電体層に比べて焼結開始温度
が高く、且つ前記第1のビアホール導体は、Ag系導体
材料にMoO3を含有するとともに、前記第2のビアホ
ール導体はRu2Oを含有することを特徴とする低温焼
成セラミック回路基板である。
SUMMARY OF THE INVENTION According to the present invention, two kinds of first and second dielectric layers having different sintering start temperatures are laminated, and an inner layer is provided between the first and second dielectric layers. A low-temperature fired ceramic circuit board comprising a wiring conductor, a first via-hole conductor in a first dielectric layer, and a second via-hole conductor in a second dielectric layer. The second dielectric layer has a higher sintering start temperature than the first dielectric layer, and the first via-hole conductor contains MoO 3 in an Ag-based conductor material, and the second via-hole conductor is a low-temperature fired ceramic circuit board, characterized by containing Ru 2 O.

【0012】[0012]

【発明の実施の形態】以下、本発明の回路基板を図面に
基づいて説明する。図1は、本発明に係る回路基板の断
面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a circuit board according to the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a circuit board according to the present invention.

【0013】図1において、10は回路基板であり、1
は基体(以下、積層体という)、3は積層体1内に形成
された内部配線導体、4は積層体1の表面に形成した表
面配線導体、31、32は積層体1内に形成されたビア
ホール導体、5は積層体1の表面に搭載したICチップ
部品であり、6は他の電子部品である。
In FIG. 1, reference numeral 10 denotes a circuit board,
Is a substrate (hereinafter, referred to as a laminate), 3 is an internal wiring conductor formed in the laminate 1, 4 is a surface wiring conductor formed on the surface of the laminate 1, and 31 and 32 are formed in the laminate 1. Via-hole conductors 5 and 5 are IC chip components mounted on the surface of the multilayer body 1, and 6 is another electronic component.

【0014】積層体1は、ガラス−セラミック材料から
なる第1の誘電体層1a、1bと、第1の誘電体層1
a、1bのガラス−セラミック材料と成分が相違し、焼
結開始温度が相違するガラス−セラミック材料からなる
第2の誘電体層2a〜2cとが積層されて構成される。
そして、第1の誘電体層1a、1bの焼結開始温度は例
えば、800〜900℃の範囲にあり、第2の誘電体層
2a〜2cの焼結開始温度は、第1の誘電体層1a、1
bよりも高い例えば900〜1000℃の範囲である。
そして、第1の誘電体層1a、1bは、第2の誘電体層
2a〜2cの外側に配置されて積層されている。
The laminate 1 includes first dielectric layers 1a and 1b made of a glass-ceramic material and first dielectric layers 1a and 1b.
The second dielectric layers 2a to 2c made of glass-ceramic materials having different components from the glass-ceramic materials a and 1b and having different sintering start temperatures are laminated.
The sintering start temperature of the first dielectric layers 1a and 1b is, for example, in the range of 800 to 900 ° C., and the sintering start temperature of the second dielectric layers 2a to 2c is equal to the first dielectric layer. 1a, 1
It is higher than b, for example, in the range of 900 to 1000 ° C.
Then, the first dielectric layers 1a and 1b are arranged and stacked outside the second dielectric layers 2a to 2c.

【0015】各誘電体層1a、2a〜2c、1bの各層
間には、所定回路網を達成するや容量成分を発生するた
めに、Ag等を主成分とする内部配線導体膜3が形成さ
れている。また、第1の誘電体層1a、1bには、その
層の厚み方向を貫く第1のビアホール導体31が形成さ
れ、第2の誘電体層2a〜2cには、その層の厚み方向
を貫く第2のビアホール導体32が形成されている。
An internal wiring conductor film 3 mainly composed of Ag or the like is formed between each of the dielectric layers 1a, 2a to 2c, and 1b in order to achieve a predetermined circuit network and generate a capacitance component. ing. In the first dielectric layers 1a and 1b, a first via-hole conductor 31 penetrating the thickness direction of each layer is formed, and in the second dielectric layers 2a to 2c, the first via hole conductor 31 penetrates the thickness direction of the layer. A second via-hole conductor 32 is formed.

【0016】そして、第1のビアホール導体31はAg
100重量部に対して、酸化モリブデン(MoO3)が
銀を2〜5重量部含有した材料からなり、第2のビアホ
ール導体32はAg100重量部に対して酸化ルテニウ
ム(Ru2O)を2〜5重量部含有した材料からなる。
The first via-hole conductor 31 is made of Ag.
Molybdenum oxide (MoO 3 ) is made of a material containing 2 to 5 parts by weight of silver with respect to 100 parts by weight, and the second via-hole conductor 32 is made of ruthenium oxide (Ru 2 O) with 2 to 5 parts by weight of Ag with respect to 100 parts by weight of Ag. It consists of a material containing 5 parts by weight.

【0017】第1及び第2の誘電体層1a、1b、2a
〜2cは、ガラス−セラミック材料かなる。ガラス−セ
ラミック材料のセラミック粉末は、クリストバライト、
石英、コランダム(αアルミナ)、ムライト、コージェ
ライトなどの絶縁セラミック材料、BaTiO3、Pb4
Fe2Nb212、TiO2などの誘電体セラミック材
料、Ni−Znフェライト、Mn−Znフェライト広義
の意味でセラミックという)などの磁性体セラミック材
料などが挙げらる。また、ガラス材料は、焼成処理する
ことによってコージェライト、ムライト、アノーサイ
ト、セルジアン、スピネル、ガーナイト、ウイレマイ
ト、ドロマイト、ペタライトやその置換誘導体の結晶や
スピネル構造の結晶相を析出するものであればよく、例
えば、B23、SiO2、Al23、ZnO、アルカリ
土類酸化物を含むガラスフリットが挙げられる。この誘
電体層1a、1b、2a〜2cの厚みは、例えば100
〜300μm程度である。
First and second dielectric layers 1a, 1b, 2a
2c are made of a glass-ceramic material. The ceramic powder of the glass-ceramic material is cristobalite,
Insulating ceramic materials such as quartz, corundum (α-alumina), mullite, cordierite, BaTiO 3 , Pb 4
Magnetic ceramic materials such as dielectric ceramic materials such as Fe 2 Nb 2 O 12 and TiO 2 , Ni—Zn ferrite, and Mn—Zn ferrite are referred to as ceramics in a broad sense. Further, the glass material may be any one that precipitates a crystal phase of a cordierite, mullite, anorthite, serdian, spinel, garnite, willemite, dolomite, petalite or a substituted derivative thereof or a crystal phase of a spinel structure by firing. For example, glass frit containing B 2 O 3 , SiO 2 , Al 2 O 3 , ZnO, and alkaline earth oxide can be used. The thickness of the dielectric layers 1a, 1b, 2a to 2c is, for example, 100
About 300 μm.

【0018】内部配線導体膜3、ビアホール導体31、
32は、Ag系導体膜(導体)からなり、内部配線導体
膜3の厚みは8〜15μm程度であり、ビアホール導体
31、32の直径は任意な値とすることができるが、例
えば直径は80〜350μmである。
The internal wiring conductor film 3, the via hole conductor 31,
Reference numeral 32 denotes an Ag-based conductor film (conductor), the thickness of the internal wiring conductor film 3 is about 8 to 15 μm, and the diameter of the via-hole conductors 31 and 32 can be set to an arbitrary value. 350350 μm.

【0019】表面配線導体膜4は、主に表面の回路配線
導体を構成するとともに、半田を介して接合される電子
部品6の接続パッドとなったり、また、厚膜抵抗膜、厚
膜コンデンサ素子の端子電極となる。特に、内部配線導
体膜3との接続は、第1の誘電体層1a、1bに形成さ
れた第1のビアホール導体31を通じて接続される。
The surface wiring conductor film 4 mainly constitutes a circuit wiring conductor on the surface, serves as a connection pad for an electronic component 6 to be joined via solder, and has a thick film resistance film, a thick film capacitor element. Terminal electrode. In particular, the connection with the internal wiring conductor film 3 is made through the first via-hole conductor 31 formed in the first dielectric layers 1a and 1b.

【0020】また、表面配線導体膜4は、ボンディング
細線、フリップチップによって接続されるICチップ5
の接続パッド(ワイヤボンディングパッド)としても用
いられる。
The surface wiring conductor film 4 is made of an IC chip 5 connected by a bonding thin wire or a flip chip.
As a connection pad (wire bonding pad).

【0021】上述の回路基板10の製造方法について説
明する。
A method for manufacturing the above-described circuit board 10 will be described.

【0022】まず、誘電体層1a、2a〜2c、1bと
なるガラス−セラミック材料から成るグリーンシートを
形成する。具体的には、セラミック材料、ガラス材料、
有機バインダ、有機溶剤を均質混練したスラリーを、ド
クターブレード法によって所定厚みにテープ成形して、
所定大きさに切断してシートを作成する。
First, a green sheet made of a glass-ceramic material for forming the dielectric layers 1a, 2a to 2c and 1b is formed. Specifically, ceramic materials, glass materials,
An organic binder, a slurry obtained by homogeneously kneading an organic solvent, is tape-formed to a predetermined thickness by a doctor blade method,
The sheet is cut into a predetermined size to create a sheet.

【0023】上述のセラミック材料とガラス材料との構
成比率は、850〜1050℃の比較的低温で焼成する
ために、セラミック材料が10〜60wt%、好ましく
は30〜50wt%であり、ガラス材料が90〜40w
t%、好ましくは70〜50wt%である。
The composition ratio of the above-mentioned ceramic material and glass material is such that the ceramic material is 10 to 60 wt%, preferably 30 to 50 wt%, since firing at a relatively low temperature of 850 to 1050 ° C. 90-40w
t%, preferably 70 to 50 wt%.

【0024】有機バインダは、固形分(セラミック粉
末、低融点ガラス成分のフリット)との濡れ性も重視す
る必要があり、比較的低温で且つ短時間の焼成工程で焼
失できるように熱分解性に優れたものが好ましく、アク
リル酸もしくはメタクリル酸系重合体のようなカルボキ
シル基、アルコール性水酸基を備えたエチレン性不飽和
化合物が好ましい。
The organic binder also needs to pay attention to the wettability with solids (ceramic powder, frit of low melting point glass component), and is thermally decomposable so that it can be burned off in a relatively low temperature and short firing step. Excellent ones are preferable, and ethylenically unsaturated compounds having a carboxyl group and an alcoholic hydroxyl group such as acrylic acid or methacrylic acid-based polymers are preferable.

【0025】溶剤として、有機系溶剤、水系溶剤を用い
ることができる。例えば、有機溶剤の場合には、2,
2,4−トリメチル−1,3−ペンタンジオールモノイ
ソベンチートなどが用いられ、水系溶剤の場合には、水
溶性である必要があり、モノマー及びバインダには、親
水性の官能基、例えばカルボキシル基が付加されてい
る。その付加量は酸価で表せば2〜300あり、好まし
くは5〜100である。付加量が少ない場合は水への溶
解性、固定成分の粉末の分散性が悪くなり、多い場合は
熱分解性が悪くなるため、付加量は、水への溶解性、分
散性、熱分解性を考慮して、上述の範囲で適宜付加され
る。
As the solvent, an organic solvent or an aqueous solvent can be used. For example, in the case of an organic solvent,
For example, 2,4-trimethyl-1,3-pentanediol monoisoventate or the like is used. In the case of an aqueous solvent, the solvent must be water-soluble, and the monomer and the binder include a hydrophilic functional group such as carboxyl. A group has been added. The amount of addition is 2 to 300, preferably 5 to 100, when expressed in acid value. If the added amount is small, the solubility in water and the dispersibility of the powder of the fixed component deteriorate, and if the added amount is large, the thermal decomposability deteriorates. In consideration of the above, it is appropriately added within the above range.

【0026】次に、第1の誘電体層1a、1bとなるグ
リーンシートの所定位置に、第1のビアホール導体31
となる所定径の貫通穴をパンチングによって形成する。
Next, the first via-hole conductor 31 is placed at a predetermined position on the green sheet to be the first dielectric layers 1a and 1b.
Is formed by punching.

【0027】また、第2の誘電体層2a〜2cとなるグ
リーンシートの所定位置に、第2のビアホール導体32
となる所定径の貫通穴をパンチングによって形成する。
The second via-hole conductor 32 is provided at a predetermined position on the green sheet to be the second dielectric layers 2a to 2c.
Is formed by punching.

【0028】次に、第1の誘電体層1a、1bとなるグ
リーンシートの貫通穴に、第1のビアホール導体31の
導体を充填し、その表面に内部配線導体膜3となる導体
膜を印刷し、乾燥処理を行う。尚、第1のビアホール導
体膜31となる導体は、Ag系(Ag単体、Ag−Pd
合金)粉末、MoO3粉末、エチルセルロースなどの有
機バインダー、溶剤からなる導電性ペーストを用いた。
また、内部配線導体膜3となる導体膜は、Ag系(Ag
単体、Ag−Pd合金)粉末、ホウ珪酸系低融点ガラス
フリット、エチルセルロースなどの有機バインダー、溶
剤を均質混合した導電性ペーストを用いた。
Next, the conductor of the first via-hole conductor 31 is filled in the through hole of the green sheet to be the first dielectric layers 1a and 1b, and a conductor film to be the internal wiring conductor film 3 is printed on the surface thereof. Then, a drying process is performed. The conductor to be the first via-hole conductor film 31 is made of Ag (Ag alone, Ag-Pd).
Alloy) A conductive paste composed of a powder, MoO 3 powder, an organic binder such as ethyl cellulose, and a solvent was used.
Further, the conductor film to be the internal wiring conductor film 3 is made of an Ag-based (Ag-based).
A conductive paste obtained by homogeneously mixing a simple substance, an Ag-Pd alloy) powder, a borosilicate-based low-melting glass frit, an organic binder such as ethyl cellulose, and a solvent was used.

【0029】また、第2の誘電体層2a〜2cとなるグ
リーンシートの貫通穴に、第2のビアホール導体32の
導体を充填し、その基板1の内部側となるグリーンシー
ト上に内部配線導体膜3となる導体膜を印刷し、乾燥処
理を行う。また、その基板1の表面側となるグリーンシ
ート上に表面配線導体膜4となる導体膜を印刷し、乾燥
処理を行う。尚、第2のビアホール導体膜32となる導
体は、Ag系(Ag単体、Ag−Pd合金)粉末、Ru
O粉末、エチルセルロースなどの有機バインダー、溶剤
からなる導電性ペーストを用いた。また、内部配線導体
膜3となる導体膜は、上述の導電性ペーストを用いた。
また、表面配線導体膜4となるAg系導電性ペースト
は、Ag系(Ag単体、Ag−PdなどのAg合金)粉
末、Pt粉末、無機バインダー、有機バインダー、溶剤
を均質混合したものが用いられる。また、基板1と表面
配線導体膜4との密着性を向上するために、V25粉末
を各金属成分に対して0.2〜1.0重量部添加してよ
い。
Also, the conductor of the second via-hole conductor 32 is filled in the through hole of the green sheet to be the second dielectric layers 2a to 2c, and the internal wiring conductor is placed on the green sheet to be the inner side of the substrate 1. A conductor film to be the film 3 is printed and dried. Further, a conductor film to be the surface wiring conductor film 4 is printed on the green sheet on the front surface side of the substrate 1 and dried. The conductor to be the second via-hole conductor film 32 is made of Ag-based (Ag alone, Ag-Pd alloy) powder, Ru
A conductive paste composed of O powder, an organic binder such as ethyl cellulose, and a solvent was used. The above-mentioned conductive paste was used for the conductor film to be the internal wiring conductor film 3.
Further, as the Ag-based conductive paste to be the surface wiring conductor film 4, one obtained by homogeneously mixing Ag-based (Ag alone, Ag alloy such as Ag-Pd) powder, Pt powder, an inorganic binder, an organic binder, and a solvent is used. . Further, in order to improve the adhesion between the substrate 1 and the surface wiring conductive film 4, a V 2 O 5 powder may be added 0.2 to 1.0 parts by weight for each metal component.

【0030】このように第1及び第2のビアホール導体
31、32となる導体、表層配線導体膜4となる導体
膜、内部配線導体膜3となる導体膜が形成された第1及
び第2の誘電体層1a、1b、2a〜2cとなるグリー
ンシートを、積層順に応じて積層一体化する。
As described above, the first and second via-hole conductors 31 and 32, the conductor film as the surface wiring conductor film 4, and the first and second conductor films as the internal wiring conductor film 3 are formed. The green sheets to be the dielectric layers 1a, 1b, 2a to 2c are laminated and integrated according to the lamination order.

【0031】次に、この未焼成の積層体を、酸化性雰囲
気または大気雰囲気で焼成処理する。焼成処理は、脱バ
インダ過程と焼結過程からなる。脱バインダ過程は、誘
電体層1a、1b、2a〜2cとなるグリーンシート、
内部配線導体膜3となる導体膜、ビアホール導体31、
32となる導体、表面配線導体膜4となる導体膜に含ま
れる有機成分を焼失するためのものであり、例えば60
0℃以下の温度領域で行われる。
Next, the unfired laminate is fired in an oxidizing atmosphere or an air atmosphere. The firing process includes a binder removal process and a sintering process. The binder removal process includes a green sheet that becomes the dielectric layers 1a, 1b, 2a to 2c,
A conductor film serving as the internal wiring conductor film 3, a via-hole conductor 31,
32 for burning off organic components contained in the conductor film 32 and the conductor film serving as the surface wiring conductor film 4, for example, 60
It is performed in a temperature range of 0 ° C. or less.

【0032】また、焼結過程は、ガラス−セラミック材
料のグリーンシートのガラス成分を結晶化させると同時
にセラミック粉末の粒界に均一に分散させ、積層体1に
一定強度を与え、内部配線導体膜3となる導体膜、第1
及び第のビアホール導体31、32となる導体、表面配
線導体膜4となる導体膜の導電材料の金属粉末、Ag系
粉末を粒成長させて、低抵抗化させ、誘電体層1a、2
a〜2c、1bと一体化させるものである。これは、ピ
ーク温度850〜1050℃に達するまでに行われる。
In the sintering process, the glass component of the green sheet of the glass-ceramic material is crystallized and simultaneously dispersed uniformly at the grain boundaries of the ceramic powder to give the laminate 1 a certain strength and to provide the internal wiring conductor film. 3 conductor film, 1st
And a metal powder and an Ag-based powder of a conductive material of the conductor film to be the first via-hole conductors 31 and 32, the conductor film to be the surface wiring conductor film 4, are made to have low resistance, and the dielectric layers 1a, 2
a to 2c and 1b. This is done until a peak temperature of 850-1050 <0> C is reached.

【0033】この工程で、内部配線導体膜3、第1およ
び第2のビアホール導体31、32が形成され、且つ表
面に表面配線導体膜4が形成された積層体1が達成され
ることになる。
In this step, the laminated body 1 in which the internal wiring conductor film 3, the first and second via-hole conductors 31 and 32 are formed, and the surface wiring conductor film 4 is formed on the surface is achieved. .

【0034】その後、必要に応じて、表面配線導体膜4
に接続する厚膜抵抗素子や所定形状の絶縁保護膜を形成
して、ICチップ5、各種電子部品6を実装する。
Thereafter, if necessary, the surface wiring conductor film 4
The IC chip 5 and various electronic components 6 are mounted by forming a thick-film resistance element and an insulating protection film having a predetermined shape connected to the IC chip 5.

【0035】これにより、図1に示す回路基板が達成す
ることになる。
As a result, the circuit board shown in FIG. 1 is achieved.

【0036】かくして、本発明の低温焼成セラミック回
路基板10によれば、異なる2種類の第1、第2の誘電
体層1a、1b、2a〜2cを積層するとともに、該第
1、第2の誘電体層1a、1b、2a〜2cの層間に内
部配線導体3を配置し、且つそれぞれ第1、第2の誘電
体層の厚みを貫く、Ag系材料を主成分とする第1、第
2のビアホール導体31、32を配置している。
Thus, according to the low-temperature fired ceramic circuit board 10 of the present invention, two different types of first and second dielectric layers 1a, 1b, 2a to 2c are laminated, and the first and second dielectric layers are laminated. An internal wiring conductor 3 is arranged between the dielectric layers 1a, 1b, 2a to 2c, and the first and second layers mainly composed of an Ag-based material penetrate through the thicknesses of the first and second dielectric layers, respectively. Via-hole conductors 31 and 32 are arranged.

【0037】そして、第2の誘電体層2a〜2cは、第
1の誘電体層1a、1bに比べて焼結開始温度が高く、
かつ第1のビアホール導体31がAg系材料100重量
部に対してMoO3を2〜5重量部含有するとともに、
第2のビアホール導体32はAg系材料100重量部に
対してRu2Oを2〜5重量部有する。このため、第1
のビアホール31においては、MoO3がAg粒子間に
存在し、第1の誘電体層1a、1bが焼結を開始される
まで、Agの焼結を遅らせ、焼成による収縮応力を低減
させる。
The second dielectric layers 2a to 2c have a higher sintering start temperature than the first dielectric layers 1a and 1b.
And the first via-hole conductor 31 contains 2 to 5 parts by weight of MoO 3 based on 100 parts by weight of the Ag-based material,
The second via-hole conductor 32 has 2 to 5 parts by weight of Ru 2 O based on 100 parts by weight of the Ag-based material. Therefore, the first
In the via hole 31, MoO 3 exists between the Ag particles, and sintering of Ag is delayed until the first dielectric layers 1a and 1b start sintering, thereby reducing shrinkage stress due to sintering.

【0038】また、第2のビアホール32においては、
Ru2OがAg粒子間に存在し、第2誘電体層2a〜2
cが焼結を開始されるまで、Agの焼結を遅らせ、焼成
による収縮応力を低減させる。
In the second via hole 32,
Ru 2 O is present between the Ag particles, and the second dielectric layers 2 a to 2
The sintering of Ag is delayed until sintering of c is started, and the shrinkage stress due to sintering is reduced.

【0039】そして、800℃以上の温度領域におい
て、第1の誘電体層1a、1bが収縮を開始する際に、
MoO3がAg粉末と固溶し、Agの収縮を促進するた
め、第1の誘電体層1a、1bの収縮応力を緩和するこ
とができる。さらに、900℃以上の温度領域におい
て、第2の誘電体層2a〜2cが収縮を開始する際に、
Ru2OがAgと固溶し、Agの収縮を促進するため、
第2の誘電体層2a〜2cの収縮応力を緩和することが
できる。その結果、ビアホール31、32のAgの焼結
に、約100℃の温度差が発生する。
When the first dielectric layers 1a and 1b start contracting in a temperature range of 800 ° C. or more,
Since MoO 3 forms a solid solution with the Ag powder and promotes the shrinkage of Ag, the shrinkage stress of the first dielectric layers 1a and 1b can be reduced. Further, in the temperature region of 900 ° C. or more, when the second dielectric layers 2a to 2c start shrinking,
Ru 2 O forms a solid solution with Ag and promotes Ag shrinkage.
The contraction stress of the second dielectric layers 2a to 2c can be reduced. As a result, a temperature difference of about 100 ° C. occurs in the sintering of the Ag of the via holes 31 and 32.

【0040】ここで、第1のビアホール導体31はAg
系材料100重量部に対してMoO 3を2〜5重量部含
有させ、また、第2のビアホール導体32はAg系材料
100重量部に対してRu2Oを2〜5重量部含有させ
ている。まず、MoO3とRu 2Oとでは、Agと固溶す
る温度に、100℃程度の差を設けるためには好都合の
材料である。また、MoO3あるいはRu2Oの添加量が
2重量部未満の場合、Agと固溶し、Agの収縮を促進
する効果が不十分である。一方、MoO3あるいはRu2
Oの添加量が5重量部より大きい場合、第1および第2
のビアホール導体31、32の導体抵抗が大きくなって
しまう。
Here, the first via-hole conductor 31 is made of Ag
MoO for 100 parts by weight of base material Three2 to 5 parts by weight
The second via-hole conductor 32 is made of an Ag-based material.
Ru for 100 parts by weightTwoO 2 to 5 parts by weight
ing. First, MoOThreeAnd Ru TwoWith O, solid solution with Ag
To provide a difference of about 100 ° C.
Material. Also, MoOThreeOr RuTwoThe amount of O added
If less than 2 parts by weight, it dissolves with Ag and promotes Ag shrinkage.
Effect is insufficient. On the other hand, MoOThreeOr RuTwo
When the amount of O added is more than 5 parts by weight, the first and second
Conductor resistance of via-hole conductors 31 and 32 of
I will.

【0041】なお、本発明は上記の実施の形態例に限定
されるものではなく、本発明の要旨を逸脱しない範囲内
での種々の変更や改良等は何ら差し支えない。
It should be noted that the present invention is not limited to the above embodiment, and various changes and improvements may be made without departing from the scope of the present invention.

【0042】[0042]

【実験例】本発明者は、収縮開始温度が800℃に設定
した第1の誘電体層1a、1bと、収縮開始温度が90
0℃に設定した第2の誘電体層2a〜2cとを積層し、
一体焼結した多層基板において、第1の誘電体層1a、
1bに形成する第1のビアホール導体31の酸化物の種
類、添加量と第2の誘電体層2a〜2cに形成する第2
のビアホール導体32の酸化物の種類、添加量を変更に
よる検討を行った。
[Experimental Example] The present inventor assumed that the first dielectric layers 1a and 1b whose shrinkage start temperature was set at 800 ° C. and the shrinkage start temperature was 90 ° C.
Laminating the second dielectric layers 2a to 2c set at 0 ° C.,
In the integrally sintered multilayer substrate, the first dielectric layer 1a,
1b, the type and amount of oxide of the first via-hole conductor 31 formed in the first via-hole conductor 31 and the second oxide formed in the second dielectric layers 2a to 2c.
Investigations were conducted by changing the type and amount of oxide of the via-hole conductor 32 described above.

【0043】なお、図1に示すように、5層構造の積層
体1で、上下の各1層を第1の誘電体層1a、1bが、
積層体1中央寄りの3層に第2の誘電体層2a〜2cを
用いた。
As shown in FIG. 1, in the laminated body 1 having a five-layer structure, the first dielectric layers 1a and 1b
The second dielectric layers 2a to 2c were used for three layers near the center of the laminate 1.

【0044】[0044]

【表1】 [Table 1]

【0045】ビアホール導体の突起量の測定方法は、積
層体1の第1のビアホール導体31領域にて、最低高さ
を示す部分と、最高高さを示す部分との高さの差を接触
膜厚計のプローブを当てて測定し、20μm未満のもの
を良品、20μm以上のものを不良品とした。
The method of measuring the amount of protrusion of the via-hole conductor is as follows. In the region of the first via-hole conductor 31 of the laminated body 1, the difference in height between the portion having the lowest height and the portion having the highest height is determined by the contact film. The thickness was measured with a probe of a thickness gauge, and those having a thickness of less than 20 μm were determined to be good, and those having a thickness of 20 μm or more were determined to be defective.

【0046】導体抵抗の測定方法は、図1における表面
配線導体膜4にそれぞれプローブを当てることによって
測定し、1mΩ未満のものを良品、1mΩ以上のものを
不良品とした。
The conductor resistance was measured by applying a probe to each of the surface wiring conductor films 4 shown in FIG. 1, and those having a resistance of less than 1 mΩ were determined to be good and those having a resistance of 1 mΩ or more were determined to be defective.

【0047】表1に示すように、第1のビアホール導体
31がMoO3を2〜5重量部、第2のビアホール導体
32がRu2Oを2〜5重量部含有する場合(試料番号
4〜7)、ビアホール導体の突起量は20μm未満、導
体抵抗は1mΩ未満となった。
As shown in Table 1, the case where the first via-hole conductor 31 contains 2 to 5 parts by weight of MoO 3 and the second via-hole conductor 32 contains 2 to 5 parts by weight of Ru 2 O (sample numbers 4 to 5) 7), the protrusion amount of the via hole conductor was less than 20 μm, and the conductor resistance was less than 1 mΩ.

【0048】一方、第1、第2のビアホール導体31、
32の両方ともMoO3を2重量部含有する場合(試料
番号1)、ビアホール導体の突起量が25μmとなっ
た。また、第1、第2のビアホール導体31、32の両
方ともRu2Oを2重量部含有する場合(試料番号
2)、ビアホール導体の突起量が25μmとなった。
On the other hand, the first and second via-hole conductors 31,
When both of Nos. 32 contained 2 parts by weight of MoO 3 (Sample No. 1), the protrusion amount of the via-hole conductor was 25 μm. When both the first and second via-hole conductors 31 and 32 contained 2 parts by weight of Ru 2 O (Sample No. 2), the protrusion amount of the via-hole conductor was 25 μm.

【0049】また、第1のビアホール導体31がMoO
3を1重量部、第2のビアホール導体32がRu2Oを1
重量部含有する場合(試料番号3)、ビアホール導体の
突起量が22μmとなった。さらに、第1のビアホール
導体31がMoO3を重量部、第2のビアホール導体3
2がRu2Oを6重量部含有する場合(試料番号8)、
導体抵抗は1.5mΩとなった。
The first via-hole conductor 31 is made of MoO
3 1 part by weight, the second via-hole conductor 32 is a Ru 2 O 1
When it was contained in parts by weight (Sample No. 3), the protrusion amount of the via-hole conductor was 22 μm. Further, the first via-hole conductor 31 includes MoO 3 by weight, and the second via-hole conductor 3
2 contains 6 parts by weight of Ru 2 O (Sample No. 8)
The conductor resistance was 1.5 mΩ.

【0050】[0050]

【発明の効果】以上のように、本発明によれば、異なる
2種類の第1、第2の誘電体層を積層するとともに、第
1、第2の誘電体層の内部に、それぞれ誘電体層の厚み
を貫く、Agを主成分とする第1、第2のビアホール導
体を配置した低温焼成セラミック回路基板であって、第
2の誘電体層は、第1の誘電体層に比べて焼結開始温度
が高く、かつ第1のビアホール導体はMoO3を2〜5
重量部含有するとともに、第2のビアホール導体はRu
2Oを2〜5重量部含有する。このため、MoO3、Ru
2Oは、それぞれ第1、第2の誘電体層が収縮を開始す
る前に、第1、第2のビアホール導体の焼結を遅らせ、
収縮応力を低減させるとともに、それぞれ第1、第2の
誘電体層が収縮を開始する際に、Agと固溶し、Agの
収縮を促進することにより、第1、第2の誘電体層の収
縮応力を緩和し、基板表面からビアホール導体の突起を
抑えることができる。
As described above, according to the present invention, two different types of first and second dielectric layers are laminated, and the first and second dielectric layers are respectively provided inside the first and second dielectric layers. A low-temperature fired ceramic circuit board having first and second via-hole conductors containing Ag as a main component and penetrating the thickness of the layer, wherein the second dielectric layer is fired as compared with the first dielectric layer. The starting temperature is high, and the first via-hole conductor is MoO 3 of 2-5.
And the second via-hole conductor is Ru.
Contains 2 to 5 parts by weight of 2O. Therefore, MoO 3 , Ru
2 O delays sintering of the first and second via-hole conductors before the first and second dielectric layers respectively begin to shrink,
In addition to reducing the shrinkage stress, when the first and second dielectric layers respectively start to shrink, they form a solid solution with Ag and promote the shrinkage of Ag, thereby reducing the shrinkage of the first and second dielectric layers. The shrinkage stress can be reduced, and the protrusion of the via-hole conductor from the substrate surface can be suppressed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る回路基板の断面図である。FIG. 1 is a cross-sectional view of a circuit board according to the present invention.

【符号の説明】[Explanation of symbols]

10 回路基板 1 積層体 1a、1b 第1のガラス−セラミック層 2a〜2c 第2のガラス−セラミック層 3 内部配線導体膜 4 表面配線導体膜 31 第1のビアホール導体 32 第2のビアホール導体 DESCRIPTION OF SYMBOLS 10 Circuit board 1 Laminated body 1a, 1b 1st glass-ceramic layer 2a-2c 2nd glass-ceramic layer 3 Internal wiring conductor film 4 Surface wiring conductor film 31 First via-hole conductor 32 Second via-hole conductor

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 23/14 C04B 35/00 J H05K 1/09 H01L 23/14 M Fターム(参考) 4E351 AA07 BB01 BB31 BB49 CC12 CC22 CC31 DD05 DD17 DD20 DD21 DD31 DD32 DD34 DD41 DD47 EE02 GG01 GG03 4G030 AA10 AA16 AA20 AA27 AA29 AA32 AA36 AA37 AA40 AA61 BA09 BA12 CA03 CA08 GA19 GA27 HA01 HA04 HA12 HA18 HA25 5E346 AA02 AA05 AA12 AA13 AA15 AA32 AA33 AA43 AA51 CC21 CC31 CC35 CC39 DD02 DD13 DD34 EE24 EE25 EE27 EE29 FF05 FF18 FF45 GG04 GG06 GG08 GG09 HH11 HH31 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI theme coat ゛ (reference) H01L 23/14 C04B 35/00 J H05K 1/09 H01L 23/14 MF term (reference) 4E351 AA07 BB01 BB31 BB49 CC12 CC22 CC31 DD05 DD17 DD20 DD21 DD31 DD32 DD34 DD41 DD47 EE02 GG01 GG03 4G030 AA10 AA16 AA20 AA27 AA29 AA32. CC35 CC39 DD02 DD13 DD34 EE24 EE25 EE27 EE29 FF05 FF18 FF45 GG04 GG06 GG08 GG09 HH11 HH31

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 焼結開始温度が異なる2種類の第1、第
2の誘電体層を積層するとともに、前記第1、第2の誘
電体層の層間に内部配線導体を配置し、且つ第1の誘電
体層に第1のビアホール導体を、第2の誘電体層に第2
のビアホール導体を夫々配置して成る低温焼成セラミッ
ク回路基板であって、 前記第2の誘電体層は、第1の誘電体層に比べて焼結開
始温度が高く、且つ前記第1のビアホール導体は、Ag
系導体材料にMoO3を含有するとともに、前記第2の
ビアホール導体はRu2Oを含有することを特徴とする
低温焼成セラミック回路基板。
1. A method according to claim 1, wherein two types of first and second dielectric layers having different sintering start temperatures are laminated, and an internal wiring conductor is arranged between the first and second dielectric layers. The first via-hole conductor is provided in one dielectric layer, and the second via-hole conductor is provided in the second dielectric layer.
A low-temperature fired ceramic circuit board, wherein the second dielectric layer has a higher sintering start temperature than the first dielectric layer, and the first via-hole conductor Is Ag
A low-temperature fired ceramic circuit board, wherein the system conductor material contains MoO 3 and the second via-hole conductor contains Ru 2 O.
【請求項2】 前記第1の誘電体層の焼結開始温度は8
00〜900℃の範囲にあり、且つ前記第2の誘電体層
の焼結開始温度は900〜1000℃の範囲にあること
を特徴とする請求項1記載の低温焼成セラミック回路基
板。
2. The sintering start temperature of the first dielectric layer is 8
2. The low-temperature fired ceramic circuit board according to claim 1, wherein the sintering temperature of the second dielectric layer is in the range of 900 to 1000 [deg.] C.
【請求項3】 前記第1のビアホール導体は、Ag系導
体材料100重量%に対してMoO3を2〜5重量部含
有するとともに、前記第2のビアホール導体は同Ru2
Oを2〜5重量部含有する請求項2記載の低温焼成セラ
ミック回路基板。
3. The first via-hole conductor contains 2 to 5 parts by weight of MoO 3 based on 100% by weight of the Ag-based conductor material, and the second via-hole conductor is made of Ru 2.
3. The low-temperature fired ceramic circuit board according to claim 2, containing 2 to 5 parts by weight of O.
JP2001097957A 2001-03-30 2001-03-30 Low temperature fired ceramic circuit board Expired - Fee Related JP4593817B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001097957A JP4593817B2 (en) 2001-03-30 2001-03-30 Low temperature fired ceramic circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001097957A JP4593817B2 (en) 2001-03-30 2001-03-30 Low temperature fired ceramic circuit board

Publications (2)

Publication Number Publication Date
JP2002299822A true JP2002299822A (en) 2002-10-11
JP4593817B2 JP4593817B2 (en) 2010-12-08

Family

ID=18951660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001097957A Expired - Fee Related JP4593817B2 (en) 2001-03-30 2001-03-30 Low temperature fired ceramic circuit board

Country Status (1)

Country Link
JP (1) JP4593817B2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0697656A (en) * 1992-09-11 1994-04-08 Matsushita Electric Ind Co Ltd Production of ceramic multilayered board
JPH0794840A (en) * 1993-06-14 1995-04-07 Nikko Co Through-hole filled ceramic substrate and conductor paste for through hole
JP2000049431A (en) * 1998-07-30 2000-02-18 Kyocera Corp Ceramic circuit board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0697656A (en) * 1992-09-11 1994-04-08 Matsushita Electric Ind Co Ltd Production of ceramic multilayered board
JPH0794840A (en) * 1993-06-14 1995-04-07 Nikko Co Through-hole filled ceramic substrate and conductor paste for through hole
JP2000049431A (en) * 1998-07-30 2000-02-18 Kyocera Corp Ceramic circuit board

Also Published As

Publication number Publication date
JP4593817B2 (en) 2010-12-08

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