JP2002252246A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent characteristics deterioration of a semiconductor device which is caused by the fact that a pressed-stress is directly applied to a chip, thereby, damage is concentrated to circumferential corners of the chip when inspecting the CPS type semiconductor device with the back surface of the chip exposed. SOLUTION: The CPS type semiconductor device is provided with a carrier 2 and the semiconductor chip 9 on which an integrated circuit element and an electrode pad are formed on its surface, and a part of a wiring pattern on the carrier 2 and the extruded formed on the electrode pad surface of the semiconductor chip 9 are flip-chip-connected each other. The integrated circuit element is formed in a region except for the region of the electrode pad positioned at least at each corner of plane of the semiconductor chip 9, the integrated circuit element is not formed in the region even if a concentrated stress is applied to the circumferential corner part of the semiconductor chip when checking a semiconductor device, therefore, the semiconductor device can be inspected without deteriorating the characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit element in a semiconductor chip constituting a semiconductor device, and to damage an integrated circuit element on the periphery of the semiconductor chip when performing an electrical test on the semiconductor device. The present invention relates to a semiconductor device having a structure that does not give a problem.

[0002]

2. Description of the Related Art As a conventional semiconductor device, there is a flip-chip mounting type semiconductor device called a CSP (Chip Size Package) as shown in FIG.

A semiconductor device shown in FIG. 3 has a semiconductor chip 1 having an electrode pad on a peripheral portion of a surface, and a semiconductor chip 1 having an electrode pad.
And a carrier 2 which is a circuit board on which a land electrode (external terminal) electrically connected to the wiring pattern is arranged on the back surface and a wiring pattern connected to the electrode pad of the semiconductor chip 1. And the electrodes of the wiring pattern on the surface of the carrier 2 are flip-chip connected by gold bumps formed on the electrode pads, and the semiconductor chip 1
The gap between the carrier and the carrier 2 is filled and sealed with a sealing resin 3.

A semiconductor chip mounted on the semiconductor device shown in FIG. 3 has an integrated circuit element 4 formed over the entire surface thereof as shown in a plan view of FIG. In FIG. 4A, a structure in which an electrode pad 5 is formed in a peripheral portion of the semiconductor chip 1 (peripheral pad)
FIG. 4B shows a structure (area pad) in which the electrode pads 5 are arranged in the area of the semiconductor chip 1, and for convenience of the surface of the semiconductor chip 1, a hatched area indicates an integrated circuit. 3 shows a region where the element 4 is formed.

Next, inspection of a conventional flip-chip connected semiconductor device will be described.

In order to inspect the electrical characteristics of a conventional CSP type semiconductor device, first, as shown in FIG. 5A, the semiconductor device is housed in an inspection socket 7 having an inspection measuring pin 6. Then, the land electrodes formed on the back surface of the carrier 2 of the semiconductor device are brought into contact with each other to make them electrically conductive. Then, as shown in FIG. 5 (b), a predetermined load is applied from above the semiconductor device housed in the test socket 7 by the test press jig 8 to press the back surface of the semiconductor chip 1 to obtain the electrical characteristics. An inspection is performed.

The measuring pins 6 for inspection are connected to an external tester tester, and inspect the electrical characteristics of the semiconductor device by controlling the input / output of the tester. The inspection holding jig 8 is larger in area than the semiconductor chip 1 of the semiconductor device. Also,
An electric functional element is present near a peripheral pad of a semiconductor chip constituting a semiconductor product to be inspected, and an electric functional element is present below the outermost peripheral pad.

[0008]

However, in the configuration of the conventional semiconductor device, the flip chip-connected semiconductor chip has a back surface (back surface) of the chip itself exposed, so that the holding jig for inspection is held down. The surface and the backside of the semiconductor chip are in direct contact, and external stress is directly applied to the backside of the chip.

For example, in the inspection stage of a semiconductor device, as shown in FIG. 6, when a predetermined weight is applied to the inspection holding jig 8 from above to hold down the semiconductor chip 1 of the semiconductor device, the back surface of the semiconductor chip 1 is designed. And inspection holding jig 8
Are uniformly contacted with each other on a flat surface, but depending on the installation state of the inspection holding jig 8 and the inclination of the semiconductor device housed in the inspection socket 7, etc., the inspection holding jig 8 and the back surface of the semiconductor chip 1 May not contact uniformly. For this reason, a higher concentrated stress is applied to the peripheral portion of the back surface of the semiconductor chip 1 than to the central portion. As a result, damage concentrates on the peripheral portion of the semiconductor chip 1, and the integrated circuit elements formed on the peripheral portion are affected, resulting in deterioration of the characteristics of the semiconductor device. In particular, the present inventors have confirmed that this problem frequently occurs in a region of 200 [μm] from the peripheral corner of the semiconductor chip 1, that is, in a region of approximately two electrode pads on the semiconductor chip 1.

The present invention solves the above-mentioned conventional problems. In particular, the present invention pays attention to a semiconductor chip of a CSP type semiconductor device. It is an object of the present invention to provide a semiconductor device that can be inspected without deteriorating characteristics.

[0011]

In order to solve the above-mentioned conventional problems, a semiconductor device according to the present invention comprises a circuit board having a wiring pattern on a front surface, external terminals connected to the wiring pattern on a back surface, and a front surface. A CSP type semiconductor device comprising: a semiconductor chip having an integrated circuit element and an electrode pad formed thereon, wherein a part of the wiring pattern of the circuit board and a surface of the semiconductor chip are flip-chip connected. ,
The integrated circuit element formed on the semiconductor chip is a semiconductor device formed in a region excluding a region of an electrode pad located at least at each corner of a plane of the semiconductor chip.

More specifically, the integrated circuit element formed on the semiconductor chip is formed in a region excluding the region of the electrode pad located at least at each corner of the plane of the semiconductor chip and the region of the electrode pad adjacent to the electrode pad. Semiconductor device.

Further, the integrated circuit element formed on the semiconductor chip is a semiconductor device formed in a region excluding a region within 200 [μm] from at least each corner of the plane of the semiconductor chip.

Further, in the semiconductor device flip-chip connected on the circuit board, a gap between the surface of the circuit board and the surface of the semiconductor chip is filled with a sealing resin.

As described above, the semiconductor device of the present invention comprises:
Even if a concentrated stress is applied to the peripheral portion of the semiconductor chip during the inspection of the semiconductor device, the integrated circuit element is not formed in the peripheral portion of the semiconductor chip, particularly in the region of the electrode pad located at each corner, so that the semiconductor chip It is possible to realize a semiconductor device capable of eliminating the influence on itself and performing an inspection without causing deterioration of characteristics of a semiconductor chip even when the semiconductor chip is pressed with an uneven force by a holding jig at the time of inspection.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the semiconductor device of the present invention will be described below with reference to the drawings.

FIG. 1 is a perspective view showing a CSP type semiconductor device of the present embodiment. FIG. 2 is a plan view showing a semiconductor chip of the semiconductor device of the present embodiment. I have.

As shown in the perspective view of FIG. 1, the semiconductor device of this embodiment has a wiring pattern on its surface,
A carrier 2 which is a circuit board having a land electrode (external terminal) electrically connected to the wiring pattern inside the substrate on the back surface, and a semiconductor chip 9 having an integrated circuit element and electrode pads formed on the surface. A semiconductor device in which a part of a wiring pattern on a carrier and a bump electrode such as a gold bump formed on an electrode pad surface of the semiconductor chip 9 are flip-chip connected to each other. The integrated circuit element is a semiconductor device formed in a region excluding a region of an electrode pad located at least at each corner of the plane of the semiconductor chip 9. The gap between the semiconductor chip 9 and the carrier 2 is filled and sealed with the sealing resin 3.

The semiconductor chip 9 of the semiconductor device of the present embodiment
As shown in FIG. 2, the integrated circuit element 4 is formed on the surface thereof, and is formed in a region excluding the region of the electrode pad 5 located at least at each corner of the plane of the semiconductor chip 9. . FIG. 2A shows a structure (peripheral pad) in which the electrode pad 5 is formed on the periphery (peripheral edge) of the semiconductor chip 9, and FIG. 2B shows that the electrode pad 5 is located in the area of the semiconductor chip 9. The structure (area pad) formed in an array is shown. For convenience of the surface of the semiconductor chip 9, a hatched region indicates a region where the integrated circuit element 4 is formed.

More specifically, the integrated circuit element 4 formed on the semiconductor chip 9 includes the electrode pad 5 located at least at each corner of the plane of the semiconductor chip 9 and the electrode pad 5 adjacent to the electrode pad 5. It is formed in a region excluding the region. The integrated circuit element 4 formed on the semiconductor chip 9 is formed in a region excluding a region within 200 [μm] from at least each corner of the plane of the semiconductor chip 4.

From each corner of the semiconductor chip 9, 200
The numerical basis of the area within [μm] is because it has been confirmed that concentrated stress occurs in an area of 200 [μm] from the peripheral corner of the semiconductor chip. That is, in the inspection of the semiconductor device, the inspection holding jig and the back surface of the semiconductor chip may not be in uniform contact with each other. In this case, a larger concentrated stress is applied to the peripheral portion of the back surface of the semiconductor chip than the central portion. become. As a result, damage concentrates on the peripheral portion of the semiconductor chip, and the integrated circuit element formed on the peripheral portion is affected, thereby deteriorating the characteristics of the semiconductor device.
[Μm] region, approximately 2 of the electrode pads on the semiconductor chip
It has been confirmed that concentrated stress frequently occurs in the individual area.

In the inspection of the electrical characteristics of the CSP type semiconductor device of the present embodiment, the semiconductor device is housed in an inspection socket having a measurement pin for inspection and the semiconductor device is inspected in the same manner as described above. The land electrodes formed on the rear surface of the carrier are brought into contact with each other to make them electrically conductive. Then, a predetermined load is applied from above the semiconductor device by an inspection holding jig to press the back surface of the semiconductor chip to inspect the electrical characteristics.

In the semiconductor device of this embodiment, since no integrated circuit element is formed in the peripheral portion of the semiconductor chip, particularly in the region of the electrode pad located at each corner, the integrated circuit element is formed in the peripheral portion of the semiconductor chip when the semiconductor device is inspected. Even if concentrated stress is applied, the influence on the semiconductor chip itself can be eliminated, and inspection can be performed without deteriorating the characteristics of the semiconductor chip even if it is pressed with an uneven force with a holding jig at the time of inspection. A semiconductor device that can be realized.

As described above, the semiconductor device according to the present embodiment is a CSP in which the semiconductor chip is exposed in a test socket in which the semiconductor chip is exposed by pressing the semiconductor chip surface to obtain an electrical connection when the semiconductor device is inspected for characteristics. In the semiconductor device of the embodiment, the semiconductor product is manufactured by using an integrated circuit element formed in a region excluding a region of an electrode pad located at least at each corner of a plane of the semiconductor chip as a semiconductor chip to be mounted. It is possible to reduce element damage that occurs at the time of inspection.

[0025]

As described above, according to the semiconductor device of the present invention, even if a concentrated stress is applied to the peripheral portion of the semiconductor chip during the inspection of the semiconductor device, the electrode pad located at each corner of the peripheral portion of the semiconductor chip, particularly, at each corner portion. Since no integrated circuit element is formed in the area of, the influence on the semiconductor chip itself can be eliminated, and even if it is pressed with a non-uniform force by the holding jig at the time of inspection, the characteristics of the semiconductor chip will deteriorate. Can be inspected. That is, in the case of a CSP type semiconductor device in which a semiconductor chip is exposed in a test socket when a semiconductor device is housed in a test socket and a semiconductor chip surface is pressed to obtain an electrical connection for testing, the semiconductor chip to be mounted is mounted. By using an integrated circuit element formed in an area excluding an area of an electrode pad located at least at each corner of a plane of a semiconductor chip, to reduce element damage caused when inspecting a semiconductor product Can be.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a semiconductor chip of the semiconductor device according to one embodiment of the present invention;

FIG. 3 is a perspective view showing a conventional semiconductor device.

FIG. 4 is a plan view showing a semiconductor chip of a conventional semiconductor device.

FIG. 5 is a sectional view showing an inspection operation of the semiconductor device;

FIG. 6 is a cross-sectional view showing a problem in an inspection operation of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Carrier 3 Sealing resin 4 Integrated circuit element 5 Electrode pad 6 Inspection measuring pin 7 Inspection socket 8 Inspection holding jig 9 Semiconductor chip

Claims (4)

[Claims] A circuit board having a wiring pattern on a front surface and external terminals connected to the wiring pattern on a back surface; and a semiconductor chip having an integrated circuit element and an electrode pad formed on a front surface, A CSP type semiconductor device in which a part of the wiring pattern of a circuit board and a surface of the semiconductor chip are flip-chip connected to each other, wherein the integrated circuit element formed on the semiconductor chip is formed on a plane of the semiconductor chip. A semiconductor device formed at least in a region excluding a region of an electrode pad located at each corner. 2. An integrated circuit element formed on a semiconductor chip is formed in a region excluding an electrode pad located at least at each corner of a plane of the semiconductor chip and a region of an electrode pad adjacent to the electrode pad. The semiconductor device according to claim 1, wherein: 3. An integrated circuit device formed on a semiconductor chip is provided at least from each corner of a plane of the semiconductor chip.
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed in a region excluding a region within 00 [μm]. 4. A semiconductor chip flip-chip connected to a circuit board, wherein a gap between the surface of the circuit board and the surface of the semiconductor chip is filled with a sealing resin. 3. The semiconductor device according to claim 1.