JP2002239167A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely dispense a winning ball in the case of a power failure. SOLUTION: When a power source voltage of DC12 V is lowered to a reference voltage LV1 (point P7), an interrupt terminal XINT becomes effective by a function of a voltage monitoring circuit 70, and a CPU63 stops driving of a ball stopping motor 29b. When the power source voltage reaches a reference voltage LV3 (point P8), an output voltage of a backup voltage monitoring circuit 64 is changed to a lower level, and NMI is applied to the CPU63. In forced interruption processing by the NMI, the CPU63 is switched to a mode recognizing detection of a game ball when a detection signal from a winning ball dispensing switch 29a is raised from a low level to a high level. In this way, it is recognized that the winning ball is dispensed when the detection signal of the winning ball dispensing switch 29a is raised from the low level to the high level (point P9). There is no need to wait for a drop (point P11) of the detection signal, so that failure in detection of the number of the number balls can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention belongs to the technical field of gaming machines.

[0002]

2. Description of the Related Art In a gaming machine, for example, a pachinko machine, a payout device that pays out game balls as prize balls or ball rentals (hereinafter collectively referred to as "prize balls or the like"), and detects game balls paid out from the payout device. A detecting means (for example, a passage sensor) and a payout control board for controlling the payout device, and a storage means (for example, RA) for storing the number of game balls to be paid out (the required payout number)
M) detecting and recognizing means (CPU) for recognizing that the detecting means has detected a game ball based on a change in the signal level from the detecting means, and reducing the required payout number of the storing means based on the recognition result by the detecting and recognizing means. A payout control board including control means for controlling the payout device by referring to the required payout number stored in the storage means and the payout control board, and the storage means when power supply to the payout control board is stopped. Some include storage holding means for holding a memory.

[0003] With this configuration, when the supply of power to the payout control board is stopped (at the time of a power failure), the memory of the storage means can be retained. (For example, Japanese Patent Laid-Open No. 11-3)
0018 publication). In other words, even if a power failure occurs, correct payment can be performed.

[0004]

The signal level from the passage sensor serving as the detecting means rises, for example, from a low level to a high level at the beginning of the passage of the game ball, stays at the high level during the passage, and changes from the high level at the end of the passage. Fall to low level. Conventionally, in order to prevent erroneous detection due to a level change due to noise, for example, it has been recognized that “detection” is a fall after a high level continues to some extent. Note that the signal level may be opposite to that in this example.

However, for example, when a power failure occurs at the beginning of the passage of a game ball (voltage starts dropping) and the function of the CPU serving as the detection and recognition means stops before the signal of the passage sensor falls, the CPU stops processing. The game ball could not be recognized. For this reason, there was a problem that the payout control board could not count this even though there was actually one payout, so that the payout was doubled for that.

[0006]

According to the first aspect of the present invention, there is provided a game machine for paying out a game ball as a prize ball or a ball for rent, and a payout device for paying out the game ball. Detecting means for detecting a game ball to be paid out, and a payout control board for controlling the payout device, and a storage means for storing the number of game balls to be paid out (the required payout number);
Detecting and recognizing means for recognizing that the detecting means has detected a game ball based on a change in the signal level from the detecting means; and reducing the required payout number of the storage means based on the recognition result by the detection and recognizing means. A payout control board including a subtraction means and a control means for controlling the payout device with reference to the payout number stored in the storage means, and when power supply to the payout control board is stopped A game machine comprising: a memory holding means for holding the memory by the memory means, further comprising a voltage monitoring means for outputting a power failure signal when a power supply voltage to the payout control board falls below a reference voltage, wherein the detection recognition means comprises: When the power failure signal is input, the detection means detects the game ball by the fact that the signal level from the detection means has changed from the non-detection level to the detection level. Characterized in that it recognized.

[0007] For example, when the supply of power to the payout control board is stopped due to the occurrence of a power outage, the power supply voltage to the payout control board falls below the reference voltage, and the voltage monitoring means outputs a power outage signal. When the supply of power to the dispensing control board is stopped due to a power failure or the like, the power supply voltage does not immediately drop to 0 volt when the power is cut off (when a power failure occurs), but gradually decreases immediately after the power is cut off. By appropriately setting the voltage, the CPU serving as each unit of the payout control board can be operated even after the input of the power failure signal. In other words, the reference voltage should be set to a value at which a voltage at which the CPU can operate can be secured for a time sufficient for the CPU to execute necessary processing after the input of the power failure signal.

After the power supply voltage drops and the voltage monitoring means outputs a power failure signal, and after the power failure signal is input, the detection / recognition means,
When the signal level from the detection means has changed from the level at the time of non-detection to the level at the time of detection (for example, rising), it is recognized that the detection means has detected a game ball, and the level at the time of detection is changed from the level at the time of non-detection Change (eg falling)
, The passing of the paid game balls can be reliably recognized before the function of the CPU serving as the detection and recognition means stops. Therefore, accurate payout becomes possible.

By the way, even if the signal level from the detection means changes from the non-detection level to the detection level (for example, rising) at normal times, the detection means recognizes that the game ball has been detected. There is a possibility that a level change is erroneously detected. Therefore, in the gaming machine according to the second aspect, in the gaming machine according to the first aspect, the detection and recognition unit normally changes a signal level from the detection unit from a detection level to a non-detection level. By doing so, the detecting means recognizes that the game ball has been detected. With this configuration, detection and recognition of an instantaneous level change due to noise can be prevented in normal times. Therefore, accurate payout can be ensured even in normal times.

According to a third aspect of the present invention, in the gaming machine according to the first or second aspect, when the supply of power to the payout control board is stopped, the payout control board is provided before the input of the power failure signal. The dispensing device is stopped by the control means, and operates for a set time or more after the stop.

There is no problem if the dispensing device is stopped when the supply of power to the dispensing control board is stopped (for example, when a power failure occurs), but if the dispensing device is operating, the CPU serving as the detection and recognition means operates. You must stop as much as possible.
In addition, the last one cannot be detected unless the game balls paid out at the time of the stop of the payout device are stopped with enough time for detection processing. This time allowance is not the processing time of the payout control board, but the time corresponding to the time (fall time) until the game ball paid out from the payout device reaches the detecting means. Therefore, although it depends on the structure of the dispensing device, the installation position of the detecting means, and the like, usually about 50 milliseconds is sufficient.

When the supply of power to the dispensing control board is stopped due to a power failure or the like, the power supply voltage drops substantially linearly immediately after the cutoff, but then drops almost linearly until it finally reaches 0 V. By setting the voltage at which the dispensing device is stopped based on the measurement experiment of the voltage drop, the above-mentioned time allowance (about 50 milliseconds) can be secured.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. Note that the embodiment of the present invention
It is needless to say that the present invention is not limited to the following specific examples at all, and can take various forms within the technical scope of the present invention.

As shown in FIG. 1, the pachinko machine 10 of this embodiment comprises a large rectangular outer frame 11 and a front frame 12, and a known card reader 13 is provided on the left of the outer frame 11. I have. The front frame 12 is rotatably attached to the outer frame 11 by upper and lower hinges 14 on the left end.

Below the front frame 12, an upper plate 15 is provided, on which a lending button 16, a settlement button 17 and a balance display section 18 are provided. When the prepaid card is inserted into the card slot 19 of the card reader 13, the stored balance is displayed on the balance display section 18, and when the lending button 16 is pressed, the game balls are lent, and the game balls are discharged from the payout slot of the upper plate 15. Is discharged.

A window-shaped metal frame 20 is removably attached to the front frame 12. A sheet glass 21 is doubly fitted into the metal frame 20. A game board 22 is housed behind the glass sheet 21. Upper plate 1
5, a lower plate 23 is provided below the front frame 12, and the lower plate 2
A firing handle 24 is attached to the right side of 3.
A rotating ring (not shown) is provided on the outer periphery of the firing handle 24, and when rotated clockwise, a game ball can be played on the game board 22.
Can be fired on.

The upper plate 15 and the lower plate 23 are connected,
When the upper plate 15 is full of game balls, the game balls are guided to the lower plate 23. FIG. 2 shows the pachinko machine 10
FIG. 3 is a rear view as viewed from the back side. As shown in the figure, a mechanism board 26 to which the game board 22 described above is detachably attached is housed in the outer frame 11 described above. In this mechanism panel 26,
From above, the ball tank 27, the guiding gutter 28 and the dispensing device 29
Is provided. With this configuration, if there is a prize of a game ball at a winning opening on the game board 22, the guiding gutter 2
A predetermined number of game balls can be discharged to the above-mentioned upper plate 15 by the dispensing device 29 via 8.

A main control board 30 and a prize ball control board 31 are detachably mounted on the mechanism board 26, a special symbol display device 32 is mounted on the game board 22, and a firing control board 33 is provided on a lower left portion of the front frame.
The external connection terminal board 5 is provided on the left side of the special symbol display device 32.
0 are each attached. The structure related to the payout of game balls and the like centering on the mechanism board 26 is the same as that of the conventional structure, and a detailed description thereof will be omitted.

Next, the game board 22 will be described with reference to FIG. As shown in FIG. 3, the gaming board 22 has an LCD panel unit (hereinafter, referred to as "LCD") 32a constituting a special symbol display device 32 in the center, and an ordinary electric accessory as a first type starting port below the LCD panel unit 32a. 36, an ordinary symbol display device 37 at the upper part of the LCD 35, an ordinary winning opening 78 provided behind the ordinary symbol display device 37, and an ordinary symbol on the left and right of the LCD 35 used to start changing the symbol displayed on the ordinary symbol display device 37. Operating gates 38, 39, these gates 38,
A special winning opening 74, 75 disposed below 39, a special winning opening 80 disposed below the ordinary electric accessory 36 and having a special winning opening 40 and right and left normal winning openings 76, 77, An out port 41, other winning ports, a windmill, a game nail (not shown), and the like are provided.

With this configuration, the above-described firing handle 2
4, the firing motor 33 a controlled by the firing control board 33 is driven to drive the firing device 33 b from the upper plate 15.
The game balls supplied to the game board 22 are guided by guide rails and fired on the game board 22. If the launched game ball wins in each winning opening, the game ball is taken in as a safe ball on the back surface of the board, and if not won, it is similarly taken in as an out ball via the out port 41 on the back surface of the board.

Next, the electrical configuration of the pachinko machine 10 will be described with reference to the block diagram of FIG. Pachinko machine 1
As shown in the figure, the electric circuit of 0 includes the main control board 30, the prize ball control board 31, the special symbol display device 32, the launch control board 33, the lamp control board 34, and the sound control board 35.
And so on. Note that this circuit diagram does not show a so-called relay board or the like for transferring signals.

The main control board 30 includes a ROM storing a game control program and a RAM serving as a work area for operations and the like.
And an external input / output circuit for inputting / outputting data from / to each board or various switches and various actuators.

On the input side of the main control board 30, a first-type starting port switch 36a, ordinary symbol operation switches 38a and 3
9a, an accessory continuous operation switch (hereinafter, simply referred to as a "V switch") 40a, a count switch 40b, a winning opening switch 52, a full tank switch 43, a supply switch 44, and the like are connected. On the output side, a special winning opening solenoid 40c, a V solenoid 40b, a normal accessory solenoid 36b, an external connection terminal board 50, and the like are connected.

[0024] Type 1 start switch 36a is in the ordinary electric won game 36 on the game board 22 described above, the normal symbol operating switches 38a and 39a are each normal symbol operating gate 38 and the 39, V switch 40a is big winning In the special device operation area (hereinafter, referred to as “special area”) in the mouth 40, the count switch 40b is also in the special winning opening 40, the full tank switch 43 is in the lower plate 16, and the supply switch 44 is in the ball tank. The other winning port switches 52 are attached to the normal winning ports 74, 75, 76, 77, 78, respectively.

Here, the first-type start switch 36a is used to indicate that the game ball has won the ordinary electric accessory 36, and that the V switch 4
0a indicates that the game ball winning in the special winning opening 40 has passed through the special area, and the count switch 40b indicates that the special winning opening 40
All game balls that win within the game, other winning opening switch 5
2 indicates that a game ball has won each of the normal winning ports 74 to 78, the full tank switch 43 indicates that the game ball is full in the lower plate 16, and the replenishment switch 44 indicates that the ball tank 27 is full. This is for detecting the existence of the game ball.

The special winning opening solenoid 40c connected to the output side is for opening and closing the special winning opening 40, the V solenoid is for opening and closing the special winning area in the special winning opening 40, and the ordinary accessory solenoid 36b is for opening and closing the ordinary electric accessory 36. Each is used. The special symbol display device 32 includes the above-described LCD 32a,
It comprises a symbol control board 32b (see FIG. 5) for driving and controlling the D32a, and auxiliary units (not shown) such as a backlight and an inverter board. Symbol control board 32
b is configured as a logic operation circuit centered on an 8-bit one-chip microcomputer similarly to the main control board 30 described above.

The prize ball control board 31 drives and controls the ball cutting motor 29b of the payout device 29 in accordance with a command command from the main control board 30, and pays out a game ball as a prize ball for winning. The unit 13 and the CR settlement display board 42 are also controlled, and are configured as a logical operation circuit using a microcomputer. The CR settlement display board 42 includes the above-described lending button 16 of the upper plate 15, the settlement button 17, the balance display section 18, and the like. The RAM of the award ball control board 31
Functions as storage means.

A prize ball payout switch 29a corresponding to the detecting means is connected to the input side of the prize ball control board 31. The prize ball payout switch 29a is provided below the ball cutting motor 29b in the payout device 29, and detects a game ball paid out by the ball cutting motor 29b. The prize ball payout switch 29a is turned on when a game ball is detected, and the signal level input to the prize ball control board 31 becomes high.

The prize ball control board 31 (CPU 63) normally recognizes the detection of a game ball when the prize ball payout switch 29a is turned off (falling) from on to off. When 29a is turned on (falling), it is recognized that a game ball has been detected.

The firing control board 33 drives and controls the firing motor 33a in accordance with the amount of rotation of the firing handle 24 operated by the player, and stops the firing when the player presses the firing stop switch 24b. Or to turn on the touch lamp 45 when the touch switch 24a built in the firing handle 24 is in an on state.

The touch switch 24a is connected to the firing handle 24.
And detects that the player is touching the firing handle 24. The lamp control board 34 mainly includes a driving element such as a transistor, and receives a command from the main control board 30 to control the ordinary symbol display device 37, lamps such as jackpot lamps and error lamps, and various lamps such as LEDs. It is for lighting display.

The sound control board 35 is composed of a sound source IC, an amplifier and the like, and drives and controls the speaker 46 in response to a command from the main control board 30. Transmission to the special symbol display device 32, the prize ball control board 31, the launch control board 33, the lamp control board 34, and the sound control board 35 is a one-way communication circuit so that transmission can be performed only from the main control board 30. Is configured as This one-way communication configuration can be implemented using an inverter circuit or a latch circuit.

The main control board 30, the prize ball control board 31,
As shown in FIG. 5, the symbol control board 32b, the firing control board 33, the lamp control board 34, the sound control board 35, etc.
Various power supplies are supplied from the power supply board 55. The power supply board 55 is provided with a DC power supply of 32 V DC, 12 V DC,
Further, a configuration is employed in which a backup power supply of 5 V DC is generated by a capacitor. Then, the main control board 30,
Each board such as the prize ball control board 31 and the symbol control board 32b uses the supplied DC 12V power supply to drive the IC drive DC 5V.
Generate V.

Here, as shown in the figure, the DC 12V power supplied from the power supply board 55 is reset (RES) of the CPU 61 via the voltage monitoring circuit 60 of the main control board 30.
Connected to terminal. Similarly, the DC 12 V power supplied from the power supply board 55 is connected to the reset (XRES) terminal of the CPU 63 via the voltage monitoring circuit 62 of the prize ball control board 31, and the interruption terminal XINT of the CPU 63 via the voltage monitoring circuit 70. , And to the XNMI terminal of the CPU 63 via the backup voltage monitoring circuit 64. The 5V backup power supply of the power supply circuit is CPU
63 are connected to the backup terminal (VBB).

Similarly, the DC supplied from the power supply board 55
The 12V power supply is a voltage monitoring circuit 65 of the symbol control board 32b.
Is connected to the reset (RES) terminal of the CPU 66 via the. The voltage monitoring circuit 60 of the main control board 30
As shown in the figure, the voltage monitoring IC 11, the resistors R17, R1
8 and R19, a bypass capacitor C10 and the like. A VSB terminal, which is an input terminal of the voltage monitoring IC 11, has a voltage of DC12V divided by resistors R17 and R18.
Is supplied, and the RESET terminal, which is the output terminal,
Pull up to DC5V by resistor R19 and C
It is connected to the RES terminal, which is the input terminal of the PU 61.

Although not shown, the voltage monitoring circuit 65 has the same configuration as the voltage monitoring circuit 60. Award ball control board 3
As shown in FIG. 7, one voltage monitoring circuit 62 includes a voltage monitoring IC 8, resistors R38, R39 and R40, bypass capacitors C22 and C23, and the like. A resistor R39 is connected to a VS terminal which is an input terminal of the voltage monitoring IC 8.
And R40 are supplied with a DC12V power supply, and a RESET terminal, which is an output terminal, is connected to a DC5V by a resistor R38.
It is pulled up to V and connected to an XRES terminal which is an input terminal of the CPU 63.

The backup voltage monitoring circuit 64 comprises a comparator IC1A, resistors R41 to R45, and the like. The minus input terminal of the comparator IC1A
The power of 5V DC divided by the resistors R43 and R44 is supplied, the plus input terminal is supplied with 12V DC of voltage divided by the resistors R41 and R42, and the output terminal is pulled to 5V DC by the resistor R45. Up and CP
It is connected to the XNMI terminal which is the input terminal of U63.

The voltage monitoring circuit 70 has the same configuration as the voltage monitoring circuit 60 of the main control board 30. With the above configuration,
Main control board 3 when pachinko machine 10 is powered on
The start-up states of the CPUs 0 and the sub-control boards other than the main control board such as the prize ball control board 31 and the symbol control board 32b will be described with reference to the timing chart shown in FIG.

When the pachinko machine 10 is turned on, the power supply board 55 generates DC 32 V, DC 12 V, and DC 5 V which is a battery backup power supply (VBB). The generated DC 12V power is supplied to each control board as shown in FIG. Here, as shown in FIG. 8, when the power is turned on (point P1), DC12V
The voltage of the power supply gradually rises from 0 V to 12 V in a parabola. The voltage of this gradually rising DC12V power supply is
When the reference voltage LV2 is reached, the outputs of the voltage monitoring circuit 62 of the prize ball control board 31 and the voltage monitoring circuit 65 of the symbol control board 32b are changed from low level to high level, the reset of the CPU 63 is released, and the CPU 63 starts the security check operation (point). P2).

When the power supply voltage of DC12V is the reference voltage LV2, the output of the voltage monitoring circuit 60 of the main control board 30 maintains a low level state. When the power supply voltage of DC12V rises from the reference voltage LV2 to the reference voltage LV1,
The output of the voltage monitoring circuit 60 changes from the low level to the high level, the reset of the CPU 61 is released, and the CPU 61 starts the security check operation (point P3).

The security check time T1 of the CPU 61 of the main control board 30 is determined by the CPU 63 of the prize ball control board 31.
The security check time T2 of each CPU of the sub control board such as the CPU 66 of the symbol control board 32b is designed to be equal to or longer than the security check time T2.

It is to be noted that the security check is, as is well known, a one-chip microcomputer CPU 61, 63 or 6
Reference numeral 6 denotes a function for checking whether or not the contents of the ROM in which the progress of the game is written are regular contents. The security check time T1 of the main control board 30 is longer than the security check time T2 of the sub control board, and the security check operation of the CPU 61 of the main control board 30 is performed later than the security check operation of the sub control board. Thereby, the CPU of the main control board 30
When the CPU 61 starts executing the control of the game according to the program written in the ROM, each CPU of the sub-control board
Has already executed the game control. As a result, even if the CPU 61 of the main control board 30 transmits data to each sub-control board immediately after the power is turned on, each sub-control board can reliably receive data because each sub-control board is executing the original control. .

In this specific example, the security check time T1 is about 439 ms, and the CPU of the main control board 30
The time from when the power is turned on to when the control of the game is executed is about 529 ms to 549 ms. The security check time T2 is about 200 ms, and the time from when the power is turned on to when the CPU 63 of the prize ball control board 31, which is one of the sub-control boards, controls the game is about 202 ms or more.
203 ms.

Next, the operation when the power to the pachinko machine 10 is cut off will be described with reference to the timing chart shown in FIG. Although the power supply voltage of DC12V drops remarkably immediately after the interruption, it drops almost linearly thereafter, and becomes 0V after a predetermined time. When the voltage gradually reaches the above-described reference voltage LV1 (point P7) during the linearly decreasing process, the output voltage of the voltage monitoring circuit 60 of the main control board 30 changes from the high level to the low level, and the CPU 61 is reset.

At point P7, the voltage monitoring circuit 70
Makes the interrupt terminal XINT of the CPU 63 valid. When the interrupt terminal XINT of the CPU 63 becomes valid, a “power failure processing routine 1” shown in FIG. 17 is executed, and the CPU 63 stops driving the ball cutting motor 29b (steps S700 to S710).

At this time, if the ball cutting motor 29b is operating (if the game balls are being paid out), the ball cutting motor 29b is stopped when one payout that is to be paid out is completed. In this embodiment, the ball cutting motor 29
Since a stepping motor is used as b, it can be stopped at this timing based on the number of steps. The drive stopping process of the ball cutting motor 29b is executed even when the ball cutting motor 29b is not driven.

Thereafter, as the time elapses, the power supply voltage of DC12V gradually decreases to the reference voltage LV3 (point P8), and the output voltage of the backup voltage monitoring circuit 64 of the award ball control board 31 changes from high level to low level. Change. As a result, the XN of the CPU 63 of the prize ball control board 31
The MI terminal goes low, and a non-maskable interrupt (NMI) is applied to the CPU 63. The "power failure processing routine 2" shown in FIG. 19 is executed during the forced interruption processing by the NMI.

In the power failure processing routine 2, the CPU 63
When the detection signal from the prize ball payout switch 29a rises from low to high, the mode is switched to a mode for recognizing detection of a game ball (S750). Thus, the payout of the game ball is recognized when the detection signal of the prize ball payout switch 29a changes from the low level to the high level. Then, after maintaining the mode detected at the rising edge for a set time (for example, 50 milliseconds), access to the RAM is inhibited to prevent writing (S760).

As described above, the prize ball control board 3
When the supply of power to the power supply 1 is stopped, the CPU 63 first stops the driving of the ball cutting motor 29b, enters a mode of detecting at the rising edge by the NMI, and finally executes a process of prohibiting access to the RAM. .

Thus, even if the prize ball is paid out when a power failure occurs, the payout of the game ball is recognized by the rise of the detection signal of the prize ball payout switch 29a (point P9), and the fall (point P11) is detected. Since there is no need to wait, it is possible to prevent omission of the number of winning balls. That is, a game ball dropped from the ball cutting motor 29b when a power failure occurs can be reliably detected.

When the power supply voltage of DC12V further decreases from the reference voltage LV3 to reach the reference voltage LV2 (point P1).
0), the output voltages of the voltage monitoring circuits of the sub-control boards such as the voltage monitoring circuit 62 of the award ball control board 31 and the voltage monitoring circuit 65 of the symbol control board 32b change from high level to low level. Thus, the CPU of each sub-control board is reset.

Here, the RAM of the prize ball control board 31 is backed up by a battery, and the data stored in the RAM is kept for a predetermined time (about one hour and two hours in this specific example) even when the power is turned off.
0 minutes to about 3 hours 30 minutes). By the way, as described above, before the CPU 63 of the award ball control board 31 is reset, the CPU 63 prohibits access to the RAM and blocks writing. As a result, the contents of the RAM in a stable state before resetting can be backed up by a battery, instead of backing up the contents of the RAM in an unstable state in which the state is reset.

As described above, when the power is turned off, first, the CPU 61 of the main control board 30 is reset, and then each CPU of the sub-control board is reset. This has the effect that each sub-control board can reliably receive data transmitted by the CPU 61 of the main control board 30 before the power is turned off.

Incidentally, in this specific example, the reference voltage LV1 is 9.
39V to 10.21V, and the reference voltage LV3 is 8.0.
0V to 9.23V, and the reference voltage LV2 is 7.20V.
It is designed to be up to 7.75V. The reference voltage LV3 to which the NMI is applied becomes the reference voltage of claim 1, the output voltage of the backup voltage monitoring circuit 64 which has changed from the high level to the low level at that time becomes the power failure signal, and the backup voltage monitoring circuit 64 becomes the voltage monitoring means. Applicable.

The operation of this embodiment having the above-described configuration is shown in FIG.
15 will be described with reference to FIG. Main control board 30
When the processing executed by the CPU 61 shifts to the "winning storage routine" shown in FIG. 10, first, it is determined whether or not there is a winning (step S100). In this specific example, five ordinary electric accessory 36 as a starting port has a prize ball, 15 special winning ports 40 have a prize ball, and 10 other prize ports 74 to 78 have a prize ball.
It is configured as a winning port for individual prize balls. Normal electric accessory 3
The winning of No. 6 is detected by the first type starting port switch 36a, the winning of the special winning opening 40 is detected by the count switch 40b, and the winning of other winning ports 74 to 78 is detected by the other winning port switch 52.

When a positive determination is made that there is a prize (step S100), the value of the unpaid prize number MMN is incremented (+1) (step S110), and thereafter a prize order storing process is executed (step S120). ). As shown in the memory map of FIG. 11, the winning order storing process (step S120) uses a 2-bit memory for one winning on a 20-byte memory space to determine the winning ball number. Written in order. In this specific example, 5
Data of 01 (H) is written for the winning opening of the winning prize ball, 10 (H) is won for the winning opening of 10 prize balls, and 11 (H) is written for the winning of 15 winning balls. It is. In this specific example, data indicating the number of winning balls for four winnings is written in one byte by using two bits from the least significant bit in the order in which the winning is detected, and if a one-byte memory is used. Is written to the memory at the next higher address. Which position in the memory space is written can be determined by the value of the incremented unpaid winning number MMN.

When the winning data is stored by the "winning storage routine", the "winning transmission routine" shown in FIG.
Is executed. The "winning storage routine" shown in FIG.
The "winning transmission routine" shown in FIG. 12 is periodically executed by a hardware interrupt.

In the "prize transmission routine" shown in FIG.
First, it is determined whether or not the value of the unpaid winning number MMN is not zero (step S150). If the value of the unpaid winning number MMN is not zero, a winning transmission process is executed (step S).
160). In this specific example, 1 of address A000 (H)
The byte data is transmitted as it is, that is, the data of the number of winning balls for four winnings is transmitted to the symbol control board 32b at a time. For example, even if the value of the unpaid winning number MMN is 3 or less and 1 or more, 1-byte data is transmitted as it is.

When the winning transmission processing is executed, the value 4 is subtracted from the value of the unpaid winning number MMN (step S17).
0) Then, it is determined whether the value of the unpaid winning number MMN subjected to the subtraction processing is equal to or smaller than zero (step S180). If a negative determination is made that the value is not equal to or less than zero, a storage update process is executed (step S190).

The storage update process (step S190) is a process of repeatedly executing the process of copying 1-byte data of the address whose address is higher than 1 to the address whose address is lower than 1 until an address where no data is written.
More specifically, the data at address A001 (H) is stored at address A000 (H), and the data at address A002 (H) is stored at address A001 (H) and address A003.
(H) data is sequentially stored in address A002 (H),
This is a process of copying one byte at a time, and is a process of repeatedly executing up to an address where data is not written.

On the other hand, if it is determined in step S180 that the value of the unpaid winning number MMN is equal to or less than zero, the value of the unpaid winning number MMN is cleared to zero (step S2).
00), a process of clearing the memories at addresses A000 (H) to A013 (H) to zero (step S210).

In this specific example, the winning transmission processing (step S160) is configured to transmit one byte of data by one processing, but the first bit which is the least significant bit of the address A000 (H) is transmitted. And two-bit data of two bits may be transmitted by one process. In the case of this configuration, the value of the unpaid winning number MMN is decremented (-1) after the transmission process, and the storage update process shifts the data right by two bits, and the seventh bit and the most significant bit, that is, 8 bits The data of the first bit and the second bit whose address is higher by one are copied to the eyes.

When the CPU 63 of the prize ball control board 31 determines that the prize data has been transmitted from the main control board 30 (step S250 (FIG. 13 “Reception data storage routine”)), the number of unpaid prizes ZMN is added. A process is performed (step S260). In the addition processing in step S260, if the transmitted 1-byte data is data representing the number of winnings for four winnings, the number of unpaid winnings ZMN is +4, and the number of winnings for three winnings is calculated. In the case of the data, the number of unpaid winnings ZMN is +3, and in the case of data representing the number of winnings for two winnings, the number of unpaid winnings ZMN is +2, and the number of winnings for one winning is represented. If it is data, this is a process of adding +1 to the unpaid winning number ZMN.

When the process of adding the unpaid winning number ZMN is performed (step S260), it is determined whether the unpaid winning number ZMN is not over the memory (step S270). In this specific example, the memory for storing the winning number is the same as the memory for storing the winning number of the main control board shown in FIG.
Byte memory is facilitated, and the number of award balls of 5 award balls is 01 (H), the number of award balls of 10 award balls is 10 (H), 1
Two bits of 11 (H) are used as the number of prize balls of five prize balls. Therefore, a 20-byte memory can store the number of prize balls for 80 game balls winning.

If it is determined that the memory is not over, a winning order storing process is executed (step S28).
0). This processing is performed in Step S performed by the main control board 30.
Similar to the process 120, the process of writing the number of prize balls corresponding to a prize in the memory, which is transmitted from the memory space corresponding to the unpaid prize number ZMN obtained by adding +1 to the unpaid prize number ZMN before being added. 01 (H), 10 (10) in the memory space corresponding to the unpaid winning number ZMN obtained by adding the winning numbers 1 to 4
(H) or 11 (H) data is written. It should be noted that whether the winning number is 1 to 4 based on the transmitted 1-byte data is determined from the most significant bit to which bit.
It can be determined whether (H) is continuous.

If one to four winning numbers represented in the one-byte data transmitted in step S250 correspond to memory over, the corresponding winning number is added and a new over winning number is obtained. OMN processing is executed (step S290).

When the processing in step S280 or S290 is executed, the number of award balls M5D, MAD, MED
Is performed (step S300). In this process, if 01 (H) data is included in the transmitted 1-byte data, the award ball number M5D is incremented (+
1) Then, if there is 10 (H) data, the award ball number MAD is incremented, and if there is 11 (H) data, the award ball number MED is incremented.

"Reception data storage routine" shown in FIG.
Is executed, the winning number of the 15 prize balls to be paid out is determined as the number of prize balls MED, the winning number of the 10 prize balls is determined as the prize ball number MAD, and the winning number of 5 prize balls is determined as the winning number of prize balls M5D. The order of prizes for the 80 prize balls to be stored and paid out is stored on the memories A000 to A013 (H).

Here, in a case where 2-bit data, that is, data for one winning, is transmitted by one transmission processing, each processing (step) of the "reception data storage routine" shown in FIG. By executing S310 to S390), the winning number of the fifteen prize balls to be paid out is determined as the prize ball number MED, the winning number of the ten prize balls is determined as the prize ball number MAD,
The winning number of the five prize balls is stored as the number of prize balls M5D.
The winning order for the 80 winning balls to be paid out may be stored in the memory at the addresses A000 (H) to A013 (H).

Next, the process in which the CPU 63 of the winning ball control board 31 drives and controls the ball cutting motor 29b to pay out a winning ball will be described with reference to a "winning ball payout routine" shown in FIG. If the value of the unpaid winning number ZMN added by the processing of the step S260 is not zero and the over winning number OMN is zero (steps S400 to S41)
0), the number of prize balls for a prize that has not been paid out is stored in the memories A000 (H) to A013 (H) in the order of the prize. In this case, the CPU 63 of the award ball control board 31 determines that the address of the address is A000.
The data written in the first and second bits of the memory, which are the least significant bits of (H), are 11 (H), 10 (H),
(H) or 01 (H) is determined (step S420).

If it is determined to be 11 (H) by the determination processing, the ball cutting motor 29b is operated until the prize ball payout switch 29a detects that 15 game balls have been paid out.
Is controlled (step S430), and thereafter, a process of decrementing (−1) the value of the winning ball number MED is executed (step S440). If it is determined to be 10 (H) by the determination process, the ball cutting motor 29b is drive-controlled until it is detected by the prize ball payout switch 29a that 10 game balls have been paid out (step S450), and thereafter,
A process of decrementing (-1) the value of the winning ball number MAD is executed (step S460). 01 by the judgment process
If (H) is determined, the ball cutting motor 29b is drive-controlled until it is detected by the prize ball payout switch 29a that five game balls have been paid out (step S470),
Thereafter, a process of decrementing (-1) the value of the winning ball number M5D is executed (step S480).

When the execution of the prize ball payout process is completed (steps S420 to S480), after updating the winning order storage (step S490), the number of unpaid winnings ZMN is decremented (step S500). The winning order storage update process (step S490) is performed for the A000 (H) address 1
A process of shifting the byte data to the right twice, that is, moving the written data to the right by 2 bits, is executed, and the seventh bit and the eighth bit, which is the most significant bit, have A001.
(H) The data of the first bit and the second bit of the address are moved, and this process is repeated by repeating the process up to the address where no data is written.

On the other hand, when it is determined in step S410 that the number of over-winning winnings OMN is not zero, the order of winning is stored after exceeding 80 winning prize ball data which have not been paid out yet. A process of paying out no prize balls is executed (step S510). The over-prize-ball payout process will be described with reference to the “over-prize-ball payout process” shown in FIG.

In this processing, the CPU of the prize ball control board 31
33, first, whether the value of the award ball number MED is zero (step S550), whether the value of the award ball number MAD is zero (step S560), and whether the value of the award ball number M5D is zero (step S560). S570) is determined one after another.

If the value of the prize ball number MED is not zero (step S550), the value of the prize ball number MED is decremented after paying out 15 game balls as prize balls (steps S580 to S590). The value of the award ball number MED is zero,
If the value of the award ball number MAD is not zero (step S5)
(50-S560) After the ten game balls are paid out as prize balls, the value of the prize ball number MAD is decremented (steps S600-S610). If the value of the prize ball number MED and the value of the prize ball number MAD are both zero and the value of the prize ball number M5D is not zero (steps S550 to S570), the prize is paid out after paying out five game balls as prize balls. The value of the number of balls M5D is decremented (steps S620 to S630).

Steps S580 and S590, steps S600 and S610, or step S6
After the execution of any one of steps S20 and S630, the value of the over-winning number OMN is decremented (step S6).
40), the process exits to "RETURN". In steps S550 to S570, the number of award balls MED and MAD are determined.
When it is determined that the values of M5D and M5D are all zero, nothing is executed, and the processing directly exits to "RETURN".

According to the specific example described in detail above,
The main control board 30 stores the number of winning balls in the order of winning, and transmits the stored winning data to the winning ball control board 31.
On the other hand, the prize ball control board 31 stores the number of prize balls in the order of winning until the memory of 20 bytes exceeds the memory,
If the prize ball cannot catch up or a large number of winnings occur at one time, 20
When the byte memory is over, only the number of winning balls is stored. Then, for the memory overrun, the prize balls are executed in order from the one with the largest number of prize balls. Thus, in normal times, the prize balls can be paid out in the order of the winning prize, and in a transient when the prize balls cannot catch up, the payout is executed with priority given to the prize balls with a large number of prize balls for the memory over. As a result, there is an excellent effect that the memory space for storing the winning order can be configured without unnecessarily increasing. In addition, in this specific example, since the battery backup function is mounted, even when returning from a power failure, prize balls can be paid out according to the stored data, and prize balls can be paid out in the order of winning. It has the effect of being able to.

Further, in this specific example, when the memory is over, the payout of the memory over is given priority, and then the payout is made in accordance with the winning order. Even if the winning data is transmitted on the way, the writing process may be performed as it is on the data after the prize ball processing, and there is an excellent effect that the storing process of the winning data is not complicated.

In this example, the winning data transmitted from the main control board 30 to the prize ball control board 31 is configured to transmit one byte of data at a time. There is also an excellent effect that the time for the reception processing of the control board 31 can be shortened.

Furthermore, in this specific example, when the memory is not over, addresses A000 (H) to A013 (H)
In the 20-byte memory space, data indicating the number of winning balls is written in the order of winning, and the number M5D, MAD, and MED of the winning balls, which are data indicating the number of winning balls, are incremented. Even if part or all of the data written to the memory at the addresses A000 (H) to A013 (H) disappears, the number of award balls M5
Prize balls can be paid out in accordance with D, MAD, and MED, and there is an effect that unexpected disadvantage is not given to the player.

When the memory is not over, the total number of winning balls indicated by the data written to the addresses A000 (H) to A013 (H) and the number of winning balls M5D, MAD,
By comparing the total number of award balls indicated by the MED with the total number of award balls, it is also possible to compare and determine whether the total number of award balls is correct.

Further, in this specific example, a configuration is employed in which data is transmitted in one direction from the main control board 30 to the prize ball control board 31.
Since the CPU 63 of the prize ball control board 31 is configured to start up earlier than the U61, even if a game ball is won immediately after returning from a power failure or the like, the main control board 30 transmits the prize ball to the prize ball control board 31. Has the effect of being able to always receive the data according to.

On the other hand, when the power is cut off due to a power failure or the like, the operation of the main control board 30 is stopped earlier than the prize ball control board 31. This has the effect that the adverse effect that the substrate 31 does not receive can be prevented beforehand.

In addition, before the XRES terminal becomes valid and the CPU 63 of the winning ball control board 31 stops operating,
Since the I terminal is enabled and data writing to the RAM can be prohibited at this time, accurate winning data can be stored and retained at the time of a power failure without writing data in an unstable power supply. It also has the effect.

Further, when the XNMI terminal becomes valid, the detection signal of the prize ball payout switch 29a, which has been recognized at the falling edge until then, becomes a mode for recognizing at the rising edge. Since there is no need to wait for the fall of the detection signal, it is possible to prevent omission of the number of winning balls (detection of all game balls paid out when a power failure occurs).

Further, the operation of the CPU 63 of the winning ball control board 31 can be stopped immediately without waiting for the fall of this signal. That is, before the driving voltage of the CPU 63 drops to a voltage level at which the driving of the CPU 63 stops, it can be stopped normally. In this specific example, the detection signal of the prize ball payout switch 29a is recognized at the falling time during normal operation and at the rising time during a power failure. On the contrary, it is sufficient to recognize the rising at the time of normal and the falling at the time of the power failure.

In this specific example, when the prize balls are paid out when the memory is over, the one with the large number of prize balls is paid out preferentially, but the one with a small number of prize balls is paid out preferentially. No problem at all. Further, in this specific example, when returning from the power failure, the prize balls are paid out in the order of winning according to the stored data, but when returning from the power failure, priority is given to winning with a large number of prize balls, Alternatively, a configuration in which a prize with a small number of prize balls is paid out with priority may be adopted.

Further, in this specific example, until the memory is over, data indicating the number of winning balls is written in the memory in the order of winning, and the corresponding number of winning balls M5D, MAD, ME
Although the value of D is incremented, the number of prize balls M5D, MAD, and MED are incremented only when the memory is over, and when the memory is not over, data indicating the number of prize balls is simply written in the memory in the order of winning. There is no problem even with the configuration of.

[Brief description of the drawings]

FIG. 1 is an external perspective view showing a gaming machine 10 employing the present invention.

FIG. 2 is a back view of the gaming machine 10 as viewed from the back.

FIG. 3 is a front view showing a configuration of a game board 22 of the gaming machine 10.

FIG. 4 is a block diagram showing an electrical configuration of the gaming machine 10.

FIG. 5 is a block diagram showing a configuration for supplying power from a power supply board 55.

FIG. 6 is a circuit diagram showing a configuration of a voltage monitoring circuit 60 of the main control board 30.

FIG. 7 is a circuit diagram showing a configuration of a voltage monitoring circuit 62, a backup voltage monitoring circuit 64, and a voltage monitoring circuit 70 of the award ball control board 31.

FIG. 8 is a timing chart showing the operation states of the CPU 61 of the main control board 30 and the CPUs of the sub-control boards when the power is turned on.

FIG. 9 shows the CPU 61 of the main control board 30 when the power is turned on and off.
6 is a timing chart illustrating an operation state of a CPU of each sub-control board.

FIG. 10 is a flowchart showing processing of a “winning storage routine”.

FIG. 11 is a memory map showing a memory area for storing a winning order.

FIG. 12 is a flowchart showing the processing of a “winning transmission routine”.

FIG. 13 is a flowchart showing processing of a “received data storage routine”.

FIG. 14 is a flowchart illustrating a process of a “received data storage routine” of the second specific example.

FIG. 15 is a flowchart showing processing of a “prize ball payout routine”.

FIG. 16 is a flowchart showing a process in an “over prize ball payout process”.

FIG. 17 is a flowchart illustrating a process of a “power failure processing routine 1”.

FIG. 18 is a flowchart illustrating a process of a “power failure processing routine 2”.

[Explanation of symbols]

Reference Signs List 10 Pachinko machine 29 Payout device 29a Prize ball payout switch (detection means) 29b Ball cutting motor 30 Main control board 31 Prize ball control board (payout control board) 32 Special symbol display device 55 Power supply board (memory holding means) 60 Voltage monitoring circuit 62 voltage monitoring circuit 63 CPU (detection recognition means, reduction means, control means,
Data updating means) 64 backup voltage monitoring circuit 65 voltage monitoring circuit 70 voltage monitoring circuit (voltage monitoring means)

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Takahiro Matsuura 1-3-3 Taiheidori, Nakagawa-ku, Nagoya-shi, Aichi Takaonai F-term (reference) 2C088 BA13 BA17 BA32 BC58 EA10

Claims (3)

[Claims] 1. A payout device for paying out game balls as prize balls or lending balls, detecting means for detecting game balls to be paid out from the payout device, and a payout control board for controlling the payout device. Storage means for storing the number of game balls to be dispensed (hereinafter referred to as "payout number required"); and detection for recognizing that the detection means has detected game balls based on a change in signal level from the detection means. Recognition means; reduction means for reducing the required payout number in the storage means based on the recognition result by the detection / recognition means; and control for controlling the payout device with reference to the required payout number stored in the storage means. A payout control board including: a payout control board; and a memory holding means for holding a memory by the storage means when the supply of power to the payout control board is stopped. A voltage monitoring unit that outputs a power failure signal when the power supply voltage to the board falls below the reference voltage; andthe detection recognition unit receives the power failure signal, and when the signal level from the detection unit is not detected. A gaming machine characterized in that the detection means recognizes that a game ball has been detected when the level has changed from a level to a detection level. 2. The gaming machine according to claim 1, wherein said detection recognizing means normally detects that the signal level from said detecting means has changed from a detected level to a non-detected level. A game machine that recognizes that a game ball has been detected. 3. The gaming machine according to claim 1, wherein when the supply of power to the payout control board is stopped, the payout control board is controlled by the control means before input of the power outage signal. A gaming machine in which a payout device is stopped and operates for a set time or more after the stop.