JP2002237593A - Method for manufacturing insulated gate semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing an MOSFET having proper ON-resistance performance and high mutual inductance. SOLUTION: Dummy oxidation layer is made thick, after forming trenches to make impurities concentrate in trench sides by piling up. Impurity concentration is low in a channel region along the trenches, and the impurity concentration distribution is flattened. As a result, since the ON-resistance becomes uniform at any apart by applying gate voltage, the ON-resistance exhibits satisfactory performance, and since mutual inductance is improved, a high frequency characteristic is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing an insulated gate semiconductor device, and more particularly to a method of manufacturing an insulated gate semiconductor device which flattens the concentration distribution of a channel region along a trench and improves transconductance.

[0002]

2. Description of the Related Art With the spread of portable terminals, a small-sized and large-capacity lithium-ion battery has been required. The protection circuit for performing the battery management of the charging and discharging of the lithium ion battery must be smaller and capable of sufficiently withstanding a load short due to the need for reducing the weight of the portable terminal. Such a protection circuit is required to be miniaturized because it is built in a container of a lithium ion battery, and a COB (Chip on Boar) using a lot of chip components is required.
d) Technology has been used to meet the demand for miniaturization. However, on the other hand, a power MOS in series with a lithium ion battery
Since the FET is connected, there is a need to make the on-resistance of the power MOSFET extremely small, which is an indispensable factor for a mobile phone to increase the talk time and the standby time.

[0003] For this reason, in the production of chips, developments have been made to increase the cell density by fine processing. Specifically, in the planar structure in which the channel is formed on the surface of the semiconductor substrate, the cell density is 7.4 million cells / square inch. In the first generation of the trench structure in which the channel is formed on the side surface of the trench, the cell density is 2500. Significantly improved to 10,000 pieces per square inch. Furthermore, in the second generation of the trench structure,
The cell density could be increased to 72 million cells / square inch by miniaturization.

In addition to reducing the on-resistance, the MOS
It is also important to improve the cutoff of the on-resistance by improving the transconductance indicating the performance of the FET in order to improve the maximum frequency during operation.

Referring to FIGS. 9 to 13, a manufacturing process of a conventional P-channel power MOSFET having a trench structure will be described.

In FIG. 9, a P ⁺ type silicon semiconductor substrate 21 is shown.
A P ^- type epitaxial layer on the drain region 2
Form 2 After selectively implanting phosphorus into the intended channel layer 24, it is diffused to form an N-type channel layer 24.

On the entire surface, NSG (Non-d
Then, a CVD oxide film 25 of an opto-silicate glass is formed, and after forming a mask, the film is partially removed by dry etching to form a trench opening 26 where the channel layer 24 is exposed.

Using the CVD oxide film 25 as a mask, the silicon semiconductor substrate in the trench opening 26 is
Anisotropic dry etching with a system gas, channel layer 2
4 through the trench 27 reaching the drain region 22
To form

In FIG. 10, dummy oxidation is performed to form trench 27.
An oxide film 29 of about 1000 to 2000 ° is formed on the inner wall and the surface of the CVD oxide film 25, and thereafter, the oxide film 29 and the CVD oxide film 2 are formed.
5 is removed by etching. The reason for removing the etching damage at the time of this dummy and performing gate oxidation oxidation later is to form a dry etching film stably. Further, the trench opening 26 is rounded by thermal oxidation at a high temperature, and there is also an effect of avoiding electric field concentration in the trench opening 26. Thus, a trench 27 is formed.

In FIG. 11, a gate oxide film 31 is formed by thermally oxidizing the entire surface. Thereafter, a gate electrode 33 buried in the trench 27 is formed. That is, a non-doped polysilicon layer is attached to the entire surface, and a high conductivity is achieved by injecting and diffusing a P-type impurity at a high concentration. Thereafter, the polysilicon layer adhered to the entire surface is dry-etched without a mask to form a gate electrode 33 buried in the trench 27.

In FIG. 12, phosphorus is selectively ion-implanted with a mask using a resist film PR to form an N ⁺ -type body contact region 34, and then the resist film PR is removed.

Further, the new source film PR is masked so as to expose the intended source region 35 and gate electrode 33, and boron or the like is ion-implanted, and the P ⁺ type source region 35 is formed in a channel adjacent to the trench 27. After the formation on the surface of the layer 24, the resist film PR is removed.

In FIG. 13, after forming an NSG layer on the entire surface,
PSG (Boron Phosphorus Sili)
(Cate Glass) layer is deposited by a CVD method,
An interlayer insulating film 36 is formed. Thereafter, the interlayer insulating film 36 is formed on at least the gate electrode 33 using the resist film as a mask.
Leave. After that, aluminum is adhered to the entire surface by a sputtering apparatus, so that the source region 35 and the body contact region 3 are formed.
4 is formed.

Referring to FIG. 13, the structure of a conventional power MOSFET having a trench structure is shown taking a P-channel type as an example.

[0015] P on top of the P ⁺ type silicon semiconductor substrate 21 ^-
A drain region 22 made of a type epitaxial layer is provided, and an N-type channel layer 24 is provided on the surface thereof. A trench 27 penetrating through the channel layer 24 and reaching the drain region 22 is provided.
1 and a gate electrode 33 made of polysilicon filled in the trench 27 is provided. A P ⁺ -type source region 35 is formed on the surface of the channel layer 24 adjacent to the trench 27, and an N ⁺ -type body contact region 34 is formed on the surface of the channel layer 24 between the source regions 35 of two adjacent cells.
Is provided. Further, a channel region 28 is formed in the channel layer 24 from the source region 35 along the trench 27 as shown by a broken line. On the gate electrode 33, an interlayer insulating film 36
And the source region 35 and the body contact region 3
4 is provided with a source electrode 37 which is in contact.

FIG. 14 shows a conventional profile of the channel layer impurity concentration with respect to the channel layer depth. The X axis is the channel layer depth, and the Y axis is the impurity concentration in the channel layer.

Since the channel layer is formed by diffusion after ion implantation, the concentration becomes locally high at a depth of about 0.2 μm from the surface of the channel layer (indicated by a). In other words, the impurity concentration is low on the surface of the channel layer, becomes highest at the middle of the trench, and becomes low again at the bottom of the trench.
When a voltage is applied to the gate electrode, the channel region 28 is inverted as shown by a broken line in FIG. 13 in contrast to the impurity concentration.

[0018]

The conventional power M
In the method for manufacturing the OSFET, the impurity concentration of the channel layer is not uniform in the depth direction of the trench. The impurity concentration of the channel layer and the on-resistance are in a proportional relationship, and the higher the impurity concentration of the channel layer, the higher the on-resistance. Therefore, a portion having a high on-resistance and a portion having a low on-resistance are generated along the depth direction of the trench. That is, even if the surface of the channel layer having a low on-resistance and the bottom of the trench are turned on, they are not turned on in the middle of the trench, so that the on-resistance is poor and the mutual inductance is low. Mutual inductance is proportional to the highest frequency during operation, and this improvement is an important issue.

[0019]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in view of the above-mentioned circumstances. Forming a trench reaching the semiconductor substrate, forming a thick oxide film by dummy-oxidizing at least the channel layer of the trench, and pile-up of a reverse conductivity type impurity in the channel layer along the trench; Forming a gate insulating film on at least the channel layer of the trench; forming a gate electrode made of a semiconductor material buried in the trench; and forming a gate electrode adjacent to the trench on the surface of the channel layer. Forming a source region of a conductivity type; and forming impurities in a channel layer of the P-channel MOSFET. The dense portion of, attracted to the dummy oxide film of the trench inner wall by pile-up, but to eliminate the difference in impurity concentration. That is, it is possible to provide a method for manufacturing a MOSFET having a good on-resistance and a high mutual inductance.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 1 to 8 taking a P-channel trench MOSFET as an example.

In the trench type power MOSFET, a step of forming a channel layer of the opposite conductivity type on a surface of a semiconductor substrate of one conductivity type serving as a drain region, a step of forming a trench penetrating the channel layer and reaching the semiconductor substrate, Forming a thick oxide film by dummy oxidation on at least the channel layer of the trench, pile-up the impurity of the opposite conductivity type in the channel layer along the trench, and forming a gate insulating film on at least the channel layer of the trench A step of forming a gate electrode made of a semiconductor material embedded in the trench, a step of forming a source region of one conductivity type adjacent to the trench on the surface of the channel layer, and a step of forming a source electrode Is done.

In the first step of the present invention, as shown in FIG.
An object is to form a channel layer of a reverse conductivity type on a surface of a semiconductor substrate of one conductivity type which is to be a drain region.

A drain region 2 is formed by laminating a P ⁻ type epitaxial layer on a P ⁺ type silicon semiconductor substrate 1. After selectively implanting phosphorus or the like into the intended channel layer 4, it is diffused to form an N-type channel layer 4. The impurity concentration at this time varies depending on the model and withstand voltage.
The depth of the channel layer 4 is, for example, about 10 ¹⁵ to 1 × 10 ^17.
It is about 0.8 to 2 μm.

In the second step of the present invention, as shown in FIG.
It is to form a trench that penetrates a channel layer and reaches a semiconductor substrate.

An NSG (Non-d)
An oxide silicide glass (CVD) film 5 is formed and partially removed by dry etching to form a trench opening 6 exposing the channel layer 4.

Using the CVD oxide film 5 as a mask, the silicon semiconductor substrate in the trench opening 6 is anisotropically dry-etched with a CF-based gas and an HBr-based gas. A trench 7 is formed.

In the third step of the present invention, as shown in FIG.
The object of the present invention is to form a thick oxide film by performing dummy oxidation on at least the channel layer of the trench, and to pile up impurities of the opposite conductivity type in the channel layer along the trench.

This step is a characteristic step of the present invention. The dummy oxidation is performed at 1100.degree.
A thick oxide film 9 of about 1500 to 4000 ° is formed on the inner wall and the surface of the CVD oxide film 5. After that, the oxide film 9 and the CVD oxide film 5 are removed by wet hydrofluoric acid.

Normally, the dummy oxidation is performed to remove etching damage at the time of dry etching and stably form a gate oxide film later. In addition, there is also an effect of rounding the trench opening 6 by performing thermal oxidation at a high temperature and avoiding electric field concentration in the trench opening 6.

It is another object of the present invention to generate an oxide film 9 thicker than before so that impurities in the channel layer 4 are attracted toward the oxide film 9 on the inner wall of the trench 7 by pile-up. P-channel type MOSFE
P-type impurities forming the T channel layer 4 accumulate in a very thin layer at the interface between the silicon substrate (channel layer 4) and the oxide film 9 by pile-up. As a result, P ⁺ -type impurities in the vicinity of a depth of about 0.2 μm from the surface of the channel layer 4 having a high concentration are pulled toward the oxide film 9 side, and the impurity concentration in that portion is reduced.

Thereafter, by removing the oxide film 9 and the CVD oxide film 5, the thin layer in which the impurities are accumulated is also removed at the same time, and the impurity concentration is redistributed at a depth of 0.2 to 2 μm in the channel layer 4. That is, the impurity concentration becomes uniform along the depth direction of the trench 7.

In the fourth step of the present invention, as shown in FIG.
It is to form a gate insulating film at least on the channel layer of the trench.

The entire surface is thermally oxidized to form a gate oxide film 11 having a thickness of several hundred Å on at least the channel layer on the inner wall of trench 7.

In the fifth step of the present invention, as shown in FIG.
It is to form a gate electrode made of a semiconductor material to be buried in a trench.

A non-doped polysilicon layer is deposited on the entire surface, and P ⁺ -type impurities such as boron are implanted and diffused at a high concentration to achieve high conductivity. Thereafter, the polysilicon layer adhered to the entire surface is dry-etched without a mask to form a gate electrode 13 buried in the trench 7.

In the sixth step of the present invention, as shown in FIG.
Forming a source region of one conductivity type adjacent to the trench on the surface of the channel layer;

Phosphorus ions are selectively implanted using a mask made of the resist film PR to form the N ⁺ -type body contact region 14. Thereafter, the resist film PR is removed.

Further, masking is performed with a new resist film PR so as to expose the intended source region 15 and gate electrode 13, boron or the like is ion-implanted, and the P ⁺ type source region 15 is formed in a channel adjacent to the trench 7. After the formation on the surface of the layer 4, the resist film PR is removed.

In the seventh step of the present invention, as shown in FIG.
It is to form a source electrode.

After forming an NSG layer on the entire surface, the BPSG (Bo
ron Phosphorus Silicate G
) layer is deposited by a CVD method to form an interlayer insulating film 1.
6 is formed. Thereafter, the interlayer insulating film 16 is left at least on the gate electrode 13 using the resist film as a mask. Thereafter, aluminum is adhered to the entire surface by a sputtering device to form a source electrode 17 that contacts the source region 15 and the body contact region 14.

The structure of the power MOSFET of the present invention will be described with reference to the sectional view shown in FIG.

The trench type power MOSFET has a semiconductor substrate, a channel layer, a trench, a gate oxide film,
It comprises a gate electrode, a source region, an interlayer insulating film, and a source electrode.

The semiconductor substrate is formed as a drain region 2 by stacking a P ⁻ type epitaxial layer on a P ⁺ type silicon semiconductor substrate 1.

The channel layer 4 is formed to be shallower than the depth of the trench 7 by selectively diffusing N-type phosphorus or the like into the surface of the drain region 2. A channel region 8 is formed in a region of the channel layer 4 adjacent to the trench 7. Since the impurity concentration of the channel layer 4 is uniform along the depth direction of the trench, when a voltage is applied to the gate electrode, the channel layer in contact with the trench is evenly inverted, and the channel region 8 also changes as shown by the broken line in FIG. Formed uniformly.

The trench 7 is formed by anisotropic dry etching of the semiconductor substrate, and reaches the drain region 2 through the channel layer 4. Generally, trenches 7 are formed in a lattice or stripe shape on a semiconductor substrate. A gate oxide film 11 is provided on the inner wall of the trench 7, and the gate electrode 1
3 is buried with polysilicon.

Gate oxide film 11 is formed at least on the inner wall of trench 7 in contact with channel layer 4 to a thickness of several hundreds of mm. Since the gate oxide film 11 is an insulating film, the trench 7
It has a MOS structure sandwiched between a gate electrode 13 provided therein and a semiconductor substrate.

The gate electrode 13 is made of polysilicon buried in the trench 7, and a P-type impurity is introduced into the polysilicon to reduce the resistance. The gate electrode 13 extends to a gate connection electrode (not shown) surrounding the periphery of the semiconductor substrate, and is connected to a gate pad electrode (not shown) provided on the semiconductor substrate.

Source region 15 is formed by diffusing P ⁺ -type impurities on the surface of channel layer 4 adjacent to trench 7,
Contact with source electrode 17.

The body contact region 14 is formed by diffusing N ⁺ -type impurities on the surface of the channel layer 4 between the adjacent second source regions 15 in order to stabilize the potential of the substrate.

The interlayer insulating film 16 is formed so as to cover at least the gate electrode 13, and a part thereof is left in the trench opening 6.

The source electrode 17 is formed by sputtering aluminum on the entire surface and etching it into a desired shape.

FIG. 8 shows the profile of the channel layer impurity concentration with respect to the channel layer depth of the present invention. The X axis is the channel layer depth, and the Y axis is the impurity concentration in the channel layer.

In the figure, a solid line is a profile according to the embodiment of the present invention, and a broken line is a conventional profile. The impurities in the channel layer are attracted to the dummy oxide film on the inner wall of the trench by pile-up, and then a part thereof is removed simultaneously with the dummy oxide film. Thereby, as shown by the solid line,
The impurity concentration is redistributed from the vicinity of the channel layer surface to almost the entire channel layer, specifically, in the range of 0.2 to 2 μm in depth, and the locally high concentration portion is flattened. Along with the density. That is, when a voltage is applied to the gate electrode, the inversion is uniformly performed in any part, and the on-resistance is improved.

The thickness of the dummy oxide film is a value optimized for flattening the concentration distribution, and is not limited to the value shown here.

[0055]

According to the present invention, a thick oxide film is formed by dummy oxidation and piled up, whereby the impurity concentration distribution of the channel layer along the trench can be flattened.

Since the impurities in the channel layer accumulate at the interface between the trench and the silicon due to the pile-up, the impurity concentration is reduced from the vicinity of the channel layer surface to almost the entire channel layer, specifically, in the range of 0.2 to 2 μm in depth. The portion which is distributed and has a high concentration near the middle of the trench is flattened.

If the concentration distribution is flat, when a voltage is applied to the gate electrode, the channel layer is uniformly inverted in any part of the trench.

That is, the on-resistance is uniform along the depth direction of the trench, so that the on-resistance is well cut and the mutual inductance is improved. Since the mutual inductance is proportional to the maximum frequency of the MOSFET during operation,
A method for manufacturing a MOSFET having high high-frequency characteristics can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method for manufacturing an insulated gate semiconductor device of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing an insulated gate semiconductor device of the present invention.

FIG. 3 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 4 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 5 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 6 is a sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 7 is a cross-sectional view illustrating the insulated gate semiconductor device of the present invention and a method for manufacturing the same.

FIG. 8 is a conceptual diagram illustrating a method for manufacturing an insulated gate semiconductor device of the present invention.

FIG. 9 is a cross-sectional view illustrating a method for manufacturing a conventional insulated gate semiconductor device.

FIG. 10 is a cross-sectional view illustrating a method for manufacturing a conventional insulated gate semiconductor device.

FIG. 11 is a cross-sectional view illustrating a method of manufacturing a conventional insulated gate semiconductor device.

FIG. 12 is a cross-sectional view illustrating a method for manufacturing a conventional insulated gate semiconductor device.

FIG. 13 is a cross-sectional view illustrating a conventional insulated gate semiconductor device and a method for manufacturing the same.

FIG. 14 is a conceptual diagram illustrating a method for manufacturing a conventional insulated gate semiconductor device.

Claims (6)

[Claims] A step of forming a channel layer of the opposite conductivity type on a surface of the semiconductor substrate of one conductivity type serving as a drain region; a step of forming a trench penetrating the channel layer and reaching the semiconductor substrate; Forming a thick oxide film by dummy oxidation on at least the channel layer, and pile-up of impurities of the opposite conductivity type in the channel layer along the trench; and gate insulation on at least the channel layer of the trench. Forming a film, forming a gate electrode made of a semiconductor material embedded in the trench, and forming a source region of one conductivity type adjacent to the trench on the surface of the channel layer. A method for manufacturing an insulated gate semiconductor device, comprising: 2. The method for manufacturing an insulated gate semiconductor device according to claim 1, wherein the pile-up flattens the concentration distribution of the opposite conductivity type impurity in a depth direction of the trench in the channel layer. . 3. The method according to claim 2, wherein the impurity concentration of the channel layer is redistributed from near the center of the trench to the bottom of the trench by the pile-up. 4. The method according to claim 1, wherein a channel region formed in the channel layer is formed uniformly along a depth direction of the trench. 5. The method according to claim 1, wherein the trench has a rounded opening. 6. The semiconductor device is a P-channel type MOSF.
2. The method for manufacturing an insulated gate semiconductor device according to claim 1, wherein the method is ET.