JP2001338806A - Ceramic plate board for chip resistor - Google Patents

Ceramic plate board for chip resistor

Info

Publication number
JP2001338806A
JP2001338806A JP2000158829A JP2000158829A JP2001338806A JP 2001338806 A JP2001338806 A JP 2001338806A JP 2000158829 A JP2000158829 A JP 2000158829A JP 2000158829 A JP2000158829 A JP 2000158829A JP 2001338806 A JP2001338806 A JP 2001338806A
Authority
JP
Japan
Prior art keywords
groove
dividing
primary
depth
division
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000158829A
Other languages
Japanese (ja)
Inventor
Tetsuo Nakamoto
徹郎 中元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000158829A priority Critical patent/JP2001338806A/en
Priority to CN 01118979 priority patent/CN1201342C/en
Publication of JP2001338806A publication Critical patent/JP2001338806A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a ceramic plate board for a chip resistor, in which the generation of defective cracking and defective division in the manufacturing process of the ceramic plate board and the chip resistor is inhibited and which can satisfy dimensional accuracy after division. SOLUTION: The depth in total of both main surfaces of primary split grooves 1 is made shallower than that of both main surfaces of secondary split grooves 2, and primary split grooves 1a on the resistance forming surface side are formed in size deeper than primary split grooves 1b on the rear side and secondary split grooves 2b on the rear side in size deeper than secondary split grooves 2a on the resistance forming surface side.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、チップ抵抗器等の
母材として用いられるセラミック基板に関する。
The present invention relates to a ceramic substrate used as a base material for a chip resistor or the like.

【0002】[0002]

【従来の技術】図8に示すように、チップ抵抗器11
は、セラミック基板12の両主面と端面に電極14を形
成し、片方の主面に抵抗13とその上に保護膜15が形
成されている。上記セラミック基板12は、従来から図
9に示すように分割溝6で多数の格子内領域3に区画さ
れ、該格子内領域3の短辺側3aに形成された一次分割
溝1と長辺側3bに形成された二次分割溝2を有し、効
率的にチップ抵抗器11の製造を行うためにその製造工
程の途中までこの形状で取り扱われる。
2. Description of the Related Art As shown in FIG.
In this device, electrodes 14 are formed on both main surfaces and end surfaces of a ceramic substrate 12, and a resistor 13 is formed on one of the main surfaces, and a protective film 15 is formed thereon. Conventionally, the ceramic substrate 12 is divided into a large number of in-grating regions 3 by the dividing grooves 6 as shown in FIG. 9, and the primary dividing groove 1 formed on the short side 3a of the in-grid region 3 and the long side. It has a secondary dividing groove 2 formed in 3b and is handled in this shape until the middle of the manufacturing process in order to manufacture the chip resistor 11 efficiently.

【0003】またこのチップ抵抗器11の小型化、寸法
精度タイト化が進むにつれ両主面のそれぞれ対応する位
置に分割溝6を形成するのが一般的となってきており、
その分割溝6の形成方法は図10に示すように、金型へ
備えられた刃8a、8bをグリーンシート5へ押し当て
て形成する。このようにして所定の形状に成型されたグ
リーンシート5を所定の温度で焼成することによりセラ
ミック基板12が得られる。
[0003] As chip resistors 11 have become smaller and have tighter dimensional accuracy, it has become common to form dividing grooves 6 at corresponding positions on both main surfaces.
As shown in FIG. 10, the dividing groove 6 is formed by pressing the blades 8a and 8b provided on the mold against the green sheet 5. By firing the green sheet 5 thus formed into a predetermined shape at a predetermined temperature, the ceramic substrate 12 is obtained.

【0004】次に、チップ抵抗器11の製造工程につい
て説明する。図11に示すように、まずセラミック基板
12の両主面に電極14を印刷、焼成した後、セラミッ
ク基板12の片方の主面に抵抗13を印刷、焼成する。
次にレーザートリミングにより抵抗値を設定し抵抗13
上に保護膜15を印刷、焼成する。次に一次分割溝1の
分割を行い、分割された一次分割溝1の端面に電極14
を印刷、焼成した後、二次分割溝2を分割することによ
りチップ抵抗器11を製造する。
Next, the manufacturing process of the chip resistor 11 will be described. As shown in FIG. 11, first, electrodes 14 are printed and fired on both main surfaces of the ceramic substrate 12, and then a resistor 13 is printed and fired on one main surface of the ceramic substrate 12.
Next, the resistance value is set by laser trimming and the resistance 13 is set.
A protective film 15 is printed and fired on the upper surface. Next, the primary division groove 1 is divided, and the electrode 14 is placed on the end face of the divided primary division groove 1.
After printing and baking, the chip resistor 11 is manufactured by dividing the secondary division groove 2.

【0005】上記一次分割溝1及び上記二次分割溝2の
従来から実施されている分割方法として、ローラー方式
や抗折方式が良く知られており、ローラー方式は図12
(a)に示すように、セラミック基板12を大径ローラ
ー16と小径ローラー17間へ挿入圧接することにより
図13(a)に示すようなバー状基板4または図13
(b)に示すようなチップ抵抗器11に分割する方法で
ある。また、抗折方式は図12(b)に示すように、セ
ラミック基板12を押さえ部18で挟持し割部19で抗
折荷重をかけることにより、前述のローラー方式と同様
にセラミック基板12をバー状基板4またはチップ抵抗
器11に分割する方法である。
As a conventional dividing method of the primary dividing groove 1 and the secondary dividing groove 2, a roller method and a folding method are well known, and the roller method is shown in FIG.
As shown in FIG. 13A, the ceramic substrate 12 is inserted and pressed between the large-diameter roller 16 and the small-diameter roller 17 so that the bar-shaped substrate 4 as shown in FIG.
This is a method of dividing into chip resistors 11 as shown in FIG. In the bending method, as shown in FIG. 12 (b), the ceramic substrate 12 is sandwiched by a pressing portion 18 and a bending force is applied by a split portion 19, so that the ceramic substrate 12 can be bared in the same manner as the roller method described above. This is a method of dividing into a substrate 4 or a chip resistor 11.

【0006】ところが一次分割溝1を分割する際、上記
のローラー方式においては大径ローラー16からの押圧
力がセラミック基板12の二次分割溝2にもかかり二次
分割溝2まで割れてしまうバー折れ不良が発生し、同様
に抗折方式でもセラミック基板12を挟持する押圧力に
より二次分割溝2が割れるという問題があった。この一
次分割溝1の分割の際に発生する二次分割溝2が割れる
バー折れ不良は、前述の端面への電極14の印刷工程に
おいて自動機の搬送、位置決め、印刷等の動作に支障を
来たし、自動機が停止したり、また割れた不良の除去が
必要である。
However, when the primary dividing groove 1 is divided, in the above-described roller system, the pressing force from the large-diameter roller 16 is applied to the secondary dividing groove 2 of the ceramic substrate 12 and the bar is broken up to the secondary dividing groove 2. There is also a problem that a bending failure occurs and the secondary division groove 2 is also broken by the pressing force holding the ceramic substrate 12 even in the anti-folding method. The bar breaking failure that occurs when the primary division groove 1 is divided and the secondary division groove 2 is broken interferes with the operation of the automatic machine in the process of printing the electrode 14 on the end face, such as conveyance, positioning, and printing. It is necessary to stop the automatic machine or remove broken defects.

【0007】このバー折れ不良等の課題を解決するため
に溝深さに関する様々な提案がされているが、例えば、
特許第2889293号公報では、縦溝(一次分割溝
1)に沿って分割した後に横溝(二次分割溝2)に沿っ
て分割する場合に、縦溝の深さを基板厚みTの0.5程
度とし、横溝の深さは基板厚みTの0.2〜0.3と浅
く形成することが示されている。
Various proposals regarding the groove depth have been made in order to solve the problems such as the bar breaking failure.
In Japanese Patent No. 2889293, when dividing along a vertical groove (primary division groove 1) and then dividing along a horizontal groove (secondary division groove 2), the depth of the vertical groove is set to 0.5 of the substrate thickness T. It is shown that the lateral groove is formed as shallow as 0.2 to 0.3 of the substrate thickness T.

【0008】また、特開平3−64089号公報では基
板の厚みTの記載はないが、最初に分割する方向の分割
溝6(一次分割溝1)の印刷面の深さを170〜260
μm、裏面の深さを10〜120μmとし、最後に分割
する方向の分割溝6(二次分割溝2)の印刷面の深さを
10〜100μm、裏面の深さを70〜180μmとす
ることが示されている。これは二次分割溝2の両主面の
合計深さを一次分割溝1の両主面の合計深さより浅く、
かつ二次分割溝2の印刷面の深さはその裏面側より浅く
形成することで、印刷面に電極14、抵抗13、保護膜
15を形成することによってその引っ張り応力で印刷面
が谷型を呈しても、一次分割溝1の分割時にセラミック
基板12の両端に荷重が加わることによる二次分割溝2
の割れを防止するものである。
Although the thickness T of the substrate is not described in Japanese Patent Application Laid-Open No. 3-64089, the depth of the printing surface of the dividing groove 6 (primary dividing groove 1) in the first dividing direction is set to 170 to 260.
μm, the depth of the back surface is 10 to 120 μm, the depth of the printing surface of the division groove 6 (secondary division groove 2) in the last dividing direction is 10 to 100 μm, and the depth of the back surface is 70 to 180 μm. It is shown. This means that the total depth of both main surfaces of the secondary division groove 2 is shallower than the total depth of both main surfaces of the primary division groove 1,
In addition, the depth of the printing surface of the secondary dividing groove 2 is formed shallower than the back surface side, and the electrode 14, the resistor 13, and the protective film 15 are formed on the printing surface, so that the printing surface has a valley shape due to the tensile stress. Even if it is presented, the secondary division groove 2 is formed by applying a load to both ends of the ceramic substrate 12 when the primary division groove 1 is divided.
This is to prevent cracking.

【0009】以上のように、一次分割溝1の両主面の合
計深さより二次分割溝2の両主面の合計深さを浅くする
ことや、さらに二次分割溝2の表裏面の深さを逆にする
ことで、前述のローラー方式や抗折方式による一次分割
溝1の分割時に二次分割溝2が割れるバー折れ不良の発
生を防止するようになっている。
As described above, the total depth of the two main surfaces of the secondary division groove 2 can be made shallower than the total depth of the two main surfaces of the primary division groove 1, and the depth of the front and back surfaces of the secondary division groove 2 can be further reduced. By reversing the above, it is possible to prevent the occurrence of a bar break defect in which the secondary division groove 2 is broken when the primary division groove 1 is divided by the roller method or the bending method described above.

【0010】[0010]

【発明が解決しようとする課題】しかし、昨今チップ状
電子部品の薄型化、小型化は更に進みこの傾向はチップ
抵抗器11においても同様であり、従来の分割装置を用
いて精度良く確実にセラミック基板12を分割すること
が難しくなってきていた。
However, in recent years, chip electronic components have been further reduced in thickness and size, and this tendency is the same in chip resistors 11, and ceramic electronic components can be accurately and reliably formed using a conventional dividing device. It has become difficult to divide the substrate 12.

【0011】前述の特許第2889293号公報や特公
平5−5421号公報では、一次分割溝1の深さを基板
の厚みTの50%前後に形成しており、二次分割溝2の
両主面の合計深さは一次分割溝1の分割の際に発生する
バー折れ不良を防ぐために、一次分割溝1の両主面の合
計深さより浅く形成していた。
In the aforementioned Japanese Patent No. 2889293 and Japanese Patent Publication No. 5-5421, the depth of the primary dividing groove 1 is formed to be about 50% of the thickness T of the substrate, The total depth of the surfaces was formed to be shallower than the total depth of both main surfaces of the primary division groove 1 in order to prevent bar breakage defects occurring at the time of division of the primary division groove 1.

【0012】しかし、セラミック基板12の厚みTが2
30μm以下の薄板基板では、分割溝6の両主面の合計
深さがセラミック基板12の厚みTの約40%を超える
と、セラミック基板12の分割溝6の形成工程や焼成工
程、その後のチップ抵抗器11の印刷工程、焼成工程で
分割溝6が割れる課題と、前述の一次分割溝1の分割の
際に二次分割溝2が割れるバー折れ不良が多発するとい
う課題があった。
However, when the thickness T of the ceramic substrate 12 is 2
In the case of a thin substrate having a thickness of 30 μm or less, if the total depth of both main surfaces of the division groove 6 exceeds about 40% of the thickness T of the ceramic substrate 12, the step of forming the division groove 6 of the ceramic substrate 12, the firing step, and the subsequent chip There is a problem that the dividing groove 6 is cracked in the printing process and the firing process of the resistor 11 and a problem that the secondary dividing groove 2 is broken at the time of dividing the primary dividing groove 1 is frequently broken.

【0013】一方、特開平3−64089号公報では、
さらに二次分割溝2の印刷面の深さはその裏面側より浅
く形成しており、一次分割溝1の分割時に二次分割溝2
が割れるバー折れ不良に対し配慮はしているものの、記
載してある分割溝6の深さ範囲は著しく広く、その最小
値をセラミック基板12の厚みTが230μm以下の薄
板基板で採用してもセラミック基板12の分割溝6の形
成工程や焼成工程、その後のチップ抵抗器11の印刷工
程、焼成工程で分割溝6が割れるという課題と、前述の
一次分割溝1の分割時に二次分割溝2が割れるバー折れ
不良が多発するという課題があった。
On the other hand, JP-A-3-64089 discloses that
Further, the depth of the printing surface of the secondary division groove 2 is formed shallower than the back side thereof, and the secondary division groove 2 is divided when the primary division groove 1 is divided.
Although the consideration is given to the broken bar which is broken, the depth range of the dividing groove 6 described is remarkably wide, and the minimum value is adopted even when the thickness T of the ceramic substrate 12 is adopted for a thin plate having a thickness T of 230 μm or less. The problem that the dividing groove 6 is broken in the step of forming and firing the dividing groove 6 of the ceramic substrate 12 and the subsequent step of printing and firing the chip resistor 11, and the problem that the secondary dividing groove 2 There has been a problem that cracking failure of the bar is frequently caused.

【0014】[0014]

【課題を解決するための手段】本発明はこれらに鑑みて
行われたもので、格子状の分割溝を両主面に対応して配
列し、長方形状とした格子内領域の短辺側に形成された
一次分割溝の両主面の合計深さが、該格子内領域の長辺
側に形成された二次分割溝の両主面の合計深さよりも浅
く、かつ上記一次分割溝は抵抗形成面が裏面より深く、
上記二次分割溝は裏面が抵抗形成面より深く、上記セラ
ミック基板の厚みが200±30μm、上記格子内領域
が600μm×300μm以下において、上記一次分割
溝の抵抗形成面の深さを20±10μm、裏面の深さを
10±5μm、上記二次分割溝の抵抗形成面の深さを1
0±5μm、裏面の深さを40±10μmとし、かつ上
記一次分割溝の抵抗形成面および上記二次分割溝の裏面
の分割溝の開き角を30±10゜、上記一次分割溝の裏
面および上記二次分割溝の抵抗形成面の分割溝の開き角
を40±5゜にする。
SUMMARY OF THE INVENTION The present invention has been made in view of these circumstances, and has a lattice-shaped dividing groove arranged corresponding to both main surfaces, and is arranged on the short side of a rectangular lattice-shaped area. The total depth of both main surfaces of the formed primary division groove is shallower than the total depth of both main surfaces of the secondary division groove formed on the long side of the region in the lattice, and the primary division groove has a resistance. The formation surface is deeper than the back surface,
When the back surface of the secondary dividing groove is deeper than the resistance forming surface, the thickness of the ceramic substrate is 200 ± 30 μm, and the area in the lattice is 600 μm × 300 μm or less, the depth of the resistance forming surface of the primary dividing groove is 20 ± 10 μm. The depth of the back surface is 10 ± 5 μm, and the depth of the resistance forming surface of the secondary division groove is 1
0 ± 5 μm, the depth of the back surface is 40 ± 10 μm, and the opening angle of the resistance forming surface of the primary dividing groove and the dividing groove on the back surface of the secondary dividing groove is 30 ± 10 °, the back surface of the primary dividing groove and The opening angle of the dividing groove on the resistance forming surface of the secondary dividing groove is set to 40 ± 5 °.

【0015】[0015]

【発明の実施の形態】以下、本発明の実施形態を説明す
る。
Embodiments of the present invention will be described below.

【0016】本発明のチップ抵抗器用セラミック基板1
2は、例えばAl23含有率93.0〜99.6重量%
のアルミナ粉末と焼結助剤、溶剤、樹脂バインダーを混
合して得られた泥漿をドクターブレード法でセラミック
スのグリーンシート5に成形し、該グリーンシート5に
金型に備えられた刃8を所定の深さまで押し当てて分割
溝6を形成し、その後所定の温度で焼成することにより
作製する。尚、セラミックスの材質はアルミナの他、窒
化アルミニゥム、ムライト、フォルステライト、ガラス
セラミック等を用いても良い。
A ceramic substrate 1 for a chip resistor according to the present invention.
2 is, for example, an Al 2 O 3 content of 93.0 to 99.6% by weight.
The slurry obtained by mixing the alumina powder of Example 1 with a sintering aid, a solvent and a resin binder is formed into a ceramic green sheet 5 by a doctor blade method, and a blade 8 provided in a mold is fixed to the green sheet 5 by a predetermined amount. To form a dividing groove 6 by pressing to a depth of 2 mm, and then firing at a predetermined temperature. The ceramic material may be aluminum nitride, mullite, forsterite, glass ceramic, or the like, in addition to alumina.

【0017】上記分割溝6は、図1に示すように、多数
の格子状で両主面に対応して配列し、格子内領域3の短
辺側3aに一次分割溝1を、また該格子内領域3の長辺
側3bに二次分割溝2が形成されている。
As shown in FIG. 1, the dividing grooves 6 are arranged in a large number of lattices corresponding to both main surfaces, and the primary dividing grooves 1 are arranged on the short side 3a of the in-grating area 3. The secondary division groove 2 is formed on the long side 3 b of the inner region 3.

【0018】チップ抵抗器11の製造工程において、セ
ラミック基板12は、図2に示すように、片方の主面に
のみ抵抗13が形成される。本発明では、この抵抗形成
面側一次分割溝1aとその裏面側一次分割溝1bの合計
深さを、抵抗形成面側二次分割溝2aとその裏面側二次
分割溝2bの合計深さよりも浅く形成し、かつ、一次分
割溝1は裏面より抵抗形成面を深く、二次分割溝2は裏
面を抵抗形成面より深く形成している。
In the manufacturing process of the chip resistor 11, the resistor 13 is formed only on one main surface of the ceramic substrate 12, as shown in FIG. In the present invention, the total depth of the resistance forming surface side primary division groove 1a and the back surface side primary division groove 1b is made larger than the total depth of the resistance formation surface side secondary division groove 2a and the back surface side secondary division groove 2b. The primary division groove 1 is formed to be deeper in the resistance forming surface than the rear surface, and the secondary division groove 2 is formed to be deeper in the rear surface than the resistance forming surface.

【0019】さらに、厚みTが200±30μm、格子
内領域3の寸法が600μm×300μm以下のセラミ
ック基板12において、抵抗形成面側一次分割溝1aの
深さを20±10μm、裏面側一次分割溝1bの深さを
10±5μm、抵抗形成面側二次分割溝2aの深さを1
0±5μm、裏面側二次分割溝2bの深さを40±10
μm、分割溝6の開き角θは、抵抗形成面側一次分割溝
1aおよび裏面側二次分割溝2bを30±10゜、裏面
側一次分割溝1bおよび抵抗形成面側二次分割溝2aを
40±5゜に形成している。
Further, in the ceramic substrate 12 having a thickness T of 200 ± 30 μm and a dimension of the in-grating region 3 of 600 μm × 300 μm or less, the depth of the resistance forming surface side primary dividing groove 1a is 20 ± 10 μm and the back side primary dividing groove. The depth of 1b is 10 ± 5 μm, and the depth of the secondary groove 2a on the resistance forming surface side is 1
0 ± 5 μm, the depth of the back side secondary division groove 2 b is 40 ± 10
μm, the opening angle θ of the dividing groove 6 is 30 ± 10 ° for the resistance forming surface side primary dividing groove 1a and the back side secondary dividing groove 2b, and the back side primary dividing groove 1b and the resistance forming surface side secondary dividing groove 2a. It is formed at 40 ± 5 °.

【0020】この、一次分割溝1を二次分割溝2より浅
くする理由は、図3(a)に示すように、セラミック基
板12の一次分割溝1のピッチP1は二次分割溝2のピ
ッチP2より広く、図3(b)に示すように、グリーン
シート5の焼成の際における脱バインダー時に、グリー
ンシート5が膨張し中央から外側の矢印の方向に引っ張
り応力がかかり、ピッチが狭い二次分割溝2への応力は
分散されるものの、ピッチが広い一次分割溝1には応力
が集中しクラックや割れが発生しやすい。このクラック
や割れの発生を抑えるためである。尚、一次分割溝1を
浅く形成すると、最初に一次分割溝1を分割する際の分
割性が低下するが、本発明においては詳細を後述する分
割装置を用いることによって、浅い一次分割溝1であっ
ても良好に分割することが出来る。
The reason why the primary division groove 1 is made shallower than the secondary division groove 2 is that the pitch P1 of the primary division groove 1 of the ceramic substrate 12 is equal to the pitch of the secondary division groove 2 as shown in FIG. As shown in FIG. 3 (b), the green sheet 5 expands and a tensile stress is exerted in the direction of the arrow from the center to the outside at the time of binder removal during firing of the green sheet 5 to reduce the secondary pitch. Although the stress on the dividing grooves 2 is dispersed, the stress concentrates on the primary dividing grooves 1 having a wide pitch, and cracks and cracks are likely to occur. This is for suppressing the occurrence of cracks and cracks. When the primary division groove 1 is formed shallowly, the dividing property when the primary division groove 1 is first divided is reduced. However, in the present invention, by using a division device described in detail later, the shallow primary division groove 1 is formed. Even if there is, it can be divided well.

【0021】上記セラミック基板12の厚みTが230
μm以下においては、一次分割溝1並びに二次分割溝2
の両主面の合計深さは基板厚みTの40%以下が好まし
く、この分割溝6の深さが厚みTの40%を超えると、
グリーンシート5へ金型に備えられた刃8を押し当てて
分割溝6を形成する段階でグリーンシート5が破れた
り、その後の焼成工程や後のチップ抵抗器11の印刷、
焼成工程で分割溝6が割れたり、また、一次分割溝1の
分割工程で二次分割溝2が割れるバー折れ不良が発生し
易くなるためである。従って、一次分割溝1並びに二次
分割溝2の厚みTに対する好ましい比の範囲は、一次分
割溝1が7.5〜22.5%、二次分割溝2が17.5
〜32.5%とした。
The thickness T of the ceramic substrate 12 is 230
In the case of μm or less, the primary dividing groove 1 and the secondary dividing groove 2
Is preferably 40% or less of the substrate thickness T. When the depth of the dividing groove 6 exceeds 40% of the thickness T,
The green sheet 5 is torn at the stage of forming the dividing groove 6 by pressing the blade 8 provided in the mold against the green sheet 5, and the subsequent firing step and the printing of the chip resistor 11 afterwards.
This is because the dividing groove 6 is broken in the firing step, and a bar breakage failure in which the secondary dividing groove 2 is broken in the dividing step of the primary dividing groove 1 is likely to occur. Therefore, the preferable range of the ratio of the thickness T of the primary divisional groove 1 and the secondary divisional groove 2 is 7.5 to 22.5% for the primary divisional groove 1 and 17.5% for the secondary divisional groove 2.
To 32.5%.

【0022】また、抵抗形成面とその裏面の分割溝6の
深さについては、一次分割溝1、二次分割溝2ともに分
割時の押圧力を加える面を深くし、その反対側は分割時
の破断方向が基板の厚み方向に対し鉛直方向に向かうよ
うにするために、破断方向の誘導が出来る程度の深さで
あれば良い。本発明のチップ抵抗器用セラミック基板1
2の分割方向は、後述するが、最初に一次分割溝1を抵
抗形成面側から、後で二次分割溝2を裏面側から押圧力
を加え分割する。
With respect to the depth of the resistance forming surface and the dividing groove 6 on the back surface, the surface for applying the pressing force at the time of dividing both the primary dividing groove 1 and the secondary dividing groove 2 is made deep. In order for the breaking direction to be perpendicular to the thickness direction of the substrate, it is sufficient that the breaking direction is deep enough to guide the breaking direction. Ceramic substrate 1 for chip resistor of the present invention
As will be described later, the pressing direction of the secondary division groove 2 is divided by applying a pressing force to the primary division groove 1 from the resistance forming surface side and then to the secondary division groove 2 from the back surface side.

【0023】この二次分割溝2の深さを抵抗形成面は浅
くし裏面を深く形成する理由は、セラミック基板12に
抵抗13、保護膜15を印刷し焼成すると、図4に示す
ように、セラミック基板12は抵抗13、保護膜15の
形成物による収縮力で谷型に反りやすい傾向があり、こ
の場合、一次分割溝1の分割の際にセラミック基板12
を押圧すると、谷型状の基板の両端に荷重がかかり二次
分割溝2が割れるバー折れ不良が発生しやすい。これを
防止するためである。
The reason why the depth of the secondary division groove 2 is such that the resistance forming surface is shallow and the back surface is formed deep is that when the resistor 13 and the protective film 15 are printed on the ceramic substrate 12 and fired, as shown in FIG. The ceramic substrate 12 tends to warp into a valley shape due to the contraction force generated by the formation of the resistor 13 and the protective film 15. In this case, the ceramic substrate 12 is divided when the primary division groove 1 is divided.
When a pressure is applied, a load is applied to both ends of the valley-shaped substrate, and a bar breaking defect in which the secondary division groove 2 is broken easily occurs. This is to prevent this.

【0024】また、抵抗形成面側一次分割溝1aと裏面
側二次分割溝2bの開き角θを、裏面側一次分割溝1b
並びに抵抗形成面側二次分割溝2aより狭く形成する理
由は、図5(a)に示すように分割溝6の開き角θが狭
いと、図5(b)に示す開き角θが広い場合に比べ分割
溝6形成時のグリーンシート5への引き裂き応力が大き
く、その結果、図5(c)に示すように、分割溝6の直
下にマイクロクラック7が発生し易い。このマイクロク
ラック7の発生は無い方が好ましいが、発生する場合
は、分割する面側にある方が好ましく、その反対側にマ
イクロクラック7が発生するとバー折れ不良の原因にな
るためである。また開き角θの狭い分割溝6を深くする
理由は、図6に示すように、金型に備えられた刃8をグ
リーンシート5へ押し当てることによるグリーンシート
5の表面への盛り上がりを防ぐために、深く侵入する刃
8の体積を少なくするためである。一方の浅く形成する
分割溝6は、金型の刃8の加工技術上並びにセラミック
基板12の量産成型に適した刃8の強度上ある程度の刃
幅を必要とするために開き角θの広い分割溝6とする。
The opening angle θ between the resistance forming surface side primary dividing groove 1a and the back side secondary dividing groove 2b is determined by changing the back side primary dividing groove 1b.
The reason why the opening angle θ of the dividing groove 6 is small as shown in FIG. 5A is that the opening angle θ shown in FIG. The tearing stress on the green sheet 5 when forming the dividing grooves 6 is larger than that of the dividing grooves 6, and as a result, microcracks 7 are likely to be generated immediately below the dividing grooves 6, as shown in FIG. It is preferable that the microcracks 7 do not occur, but if they do occur, it is preferable that the microcracks 7 be located on the surface to be divided. If the microcracks 7 occur on the opposite side, it may cause bar breakage failure. Further, the reason why the division groove 6 having the narrow opening angle θ is made deep is to prevent the blade 8 provided in the mold from being pressed against the green sheet 5 to prevent the green sheet 5 from rising on the surface as shown in FIG. This is to reduce the volume of the blade 8 that penetrates deeply. On the other hand, the shallow dividing groove 6 is required to have a certain blade width in terms of the processing technology of the blade 8 of the mold and the strength of the blade 8 suitable for mass production molding of the ceramic substrate 12. Groove 6.

【0025】本発明のチップ抵抗器用セラミック基板1
2を用いてチップ抵抗器11を製造する方法を説明す
る。前述した図11の製造工程と同じで、まずセラミッ
ク基板12の両主面に電極14を印刷、焼成し、次に上
記セラミック基板12の厚み方向に対して対応する一次
分割溝1の深く形成されている主面に抵抗13を印刷、
焼成する。次に抵抗13をレーザートリミングにより所
定の抵抗値に設定した後この抵抗13上に保護膜15を
印刷、焼成する。この後、二次分割溝2より浅く形成さ
れた一次分割溝1を先に分割し、分割された端面に電極
14を印刷、焼成した後、二次分割溝2を分割する。
The ceramic substrate 1 for a chip resistor according to the present invention.
A method for manufacturing the chip resistor 11 using the second embodiment will be described. As in the manufacturing process of FIG. 11 described above, first, electrodes 14 are printed and fired on both main surfaces of the ceramic substrate 12, and then the primary division grooves 1 corresponding to the thickness direction of the ceramic substrate 12 are formed deeply. Printing the resistor 13 on the main surface
Bake. Next, after setting the resistance 13 to a predetermined resistance value by laser trimming, a protective film 15 is printed and fired on the resistance 13. Then, the primary division groove 1 formed shallower than the secondary division groove 2 is divided first, the electrodes 14 are printed and fired on the divided end faces, and then the secondary division groove 2 is divided.

【0026】上記一次分割溝1の深さは極端に浅く形成
してあり、前述のグリーンシート5の焼成時のクラック
発生を防止し、かつ、後述する分割方法で良好な分割が
出来る深さとしている。
The depth of the primary division groove 1 is extremely small, so that cracks can be prevented from occurring at the time of firing the green sheet 5 described above, and the primary division groove 1 has a depth at which good division can be performed by a division method described later. I have.

【0027】次にその分割方法を説明する。図7(a)
に分割装置の分割原理を示しているが、まずセラミック
基板12の抵抗形成面を上にし一次分割溝1の分割箇所
が分割装置の割部19と押さえ部18の間に位置するよ
うに下シート20にセラミック基板12を載置し搬送す
る。次に、図7(b)に示すように、クランク機構21
が回転し上下動可能な駆動軸22により、上記割部19
と上記押さえ部18を下動させ、ストッパー機構24で
押さえ部18の下動を規制し上記セラミック基板12と
当接させる。図7(c)に示すように、さらに、駆動軸
22が下動することにより連結部23のシーソー機構に
よって割部19を押さえ部18よりさらに下動させて基
板を押圧することにより上記一次分割溝1を分割する。
Next, the dividing method will be described. FIG. 7 (a)
The dividing principle of the dividing device is shown in the drawing. First, the lower sheet is formed so that the resistance forming surface of the ceramic substrate 12 is turned up and the dividing portion of the primary dividing groove 1 is located between the dividing portion 19 and the pressing portion 18 of the dividing device. The ceramic substrate 12 is placed on the substrate 20 and transported. Next, as shown in FIG.
Is driven by the drive shaft 22 which can rotate and move up and down.
Then, the pressing portion 18 is moved downward, and the stopper mechanism 24 regulates the downward movement of the pressing portion 18 so as to make contact with the ceramic substrate 12. As shown in FIG. 7 (c), when the drive shaft 22 further moves down, the split portion 19 is further moved down from the holding portion 18 by the seesaw mechanism of the connecting portion 23, and the substrate is pressed. Divide groove 1.

【0028】この方法による一次分割は、二次分割溝2
の両主面の合計深さより浅く形成された一次分割溝1の
分割が精度良く出来、また二次分割溝2に余計な押圧力
が掛からず、また更に二次分割溝2は押圧力の加わる抵
抗形成面の分割溝6の深さが浅いために、セラミック基
板12が谷型を呈していてもバー折れ不良が発生しな
い。
The primary division by this method is performed by the secondary division groove 2
The primary divisional groove 1 formed shallower than the total depth of the two main surfaces can be accurately divided, no additional pressing force is applied to the secondary divisional groove 2, and furthermore, the secondary divisional groove 2 receives a pressing force. Since the depth of the dividing groove 6 on the resistance forming surface is shallow, even if the ceramic substrate 12 has a valley shape, a bar break defect does not occur.

【0029】二次分割は、前述の分割方法或いは従来の
ローラー方式でも良く、バー状基板4の抵抗形成面を下
にし、裏面より押圧力を加え分割する。
The secondary division may be performed by the above-described division method or a conventional roller method, in which the resistance-forming surface of the bar-shaped substrate 4 is turned downward, and a pressing force is applied from the back surface to perform division.

【0030】[0030]

【実施例】Al23含有率96.0重量%のセラミック
スグリーンシート5をドクターブレード法で成形し、該
グリーンシート5に金型に備えられた刃8を所定の深さ
まで押し当てて分割溝6を形成し、その後所定の温度で
焼成することにより外辺寸法が60.0mm×49.5
mm、厚みTが200μm、格子内領域3の長辺側3b
寸法が580μm、格子内領域3の短辺側3a寸法が2
90μmでチップ抵抗器11となる格子内領域3の数が
2880個からなるセラミック基板12を、本発明のチ
ップ抵抗器用セラミック基板12並びに比較例である従
来のチップ抵抗器用セラミック基板12の各々作製し
た。
EXAMPLE A ceramic green sheet 5 having an Al 2 O 3 content of 96.0% by weight was formed by a doctor blade method, and a blade 8 provided in a mold was pressed against the green sheet 5 to a predetermined depth to divide it. A groove 6 is formed and then baked at a predetermined temperature so that the outer dimension is 60.0 mm × 49.5.
mm, the thickness T is 200 μm, and the long side 3b in the lattice area 3
The dimension is 580 μm, and the dimension of the short side 3a of the in-grating region 3 is 2
A ceramic substrate 12 having a size of 90 μm and having 2880 in-grid regions 3 serving as chip resistors 11 was prepared for each of the chip resistor ceramic substrate 12 of the present invention and the conventional chip resistor ceramic substrate 12 of the comparative example. .

【0031】本発明のチップ抵抗器用セラミック基板1
2は、表1に示すように、抵抗形成面側一次分割溝1a
の深さを、試料A=8μm、試料B=10μm,試料C
=20μm,試料D=30μm,試料E=32μmと
し、裏面側一次分割溝1bの深さをいずれも10μm、
抵抗形成面側二次分割溝2aの深さはいずれも10μ
m、裏面側二次分割溝2bの深さはいずれも40μmと
した。また、抵抗形成面側一次分割溝1a並びに裏面側
二次分割溝2bの分割溝6の開き角θを30゜、裏面側
一次分割溝1b並びに抵抗形成面側二次分割溝2aの分
割溝6の開き角θを40゜とした。
Ceramic substrate 1 for chip resistor of the present invention
As shown in Table 1, reference numeral 2 denotes a primary division groove 1a on the resistance forming surface side.
Of the sample A = 8 μm, sample B = 10 μm, sample C
= 20 μm, sample D = 30 μm, sample E = 32 μm, the depth of the back side primary division groove 1 b was 10 μm,
The depth of each of the resistance forming surface side secondary division grooves 2a is 10 μm.
m and the depth of the back side secondary division groove 2b were all 40 μm. Further, the opening angle θ of the dividing groove 6 of the resistance forming surface side primary dividing groove 1a and the back side secondary dividing groove 2b is 30 °, and the dividing groove 6 of the back side primary dividing groove 1b and the resistance forming surface side secondary dividing groove 2a. Was set to 40 °.

【0032】比較例も同一形状のセラミック基板12で
あって、抵抗形成面側一次分割溝1aの深さは90μ
m、抵抗形成面側二次分割溝2aの深さは50μmと
し、裏面側一次分割溝1b並びに裏面側二次分割溝2b
の深さはいずれも10μmとした。また、一次分割溝1
並びに二次分割溝2とも分割溝6の開き角θは、抵抗形
成面側を30゜、裏面側を40゜とした。
The ceramic substrate 12 of the comparative example also has the same shape, and the depth of the resistance forming surface side primary dividing groove 1a is 90 μm.
m, the depth of the resistance forming surface side secondary division groove 2a is 50 μm, the back side primary division groove 1b and the back side secondary division groove 2b
Was 10 μm. Also, the primary dividing groove 1
In addition, the opening angle θ of the dividing grooves 6 in both the secondary dividing grooves 2 was 30 ° on the resistance forming surface side and 40 ° on the back surface side.

【0033】尚、分割溝6の形成方法は、順送プレス方
式により最初に二次分割溝2を分割溝6形成用の刃8を
備えた金型を、グリーンシート5の両主面に押し当てて
同時に形成し、次に同様にして一次分割溝1を両主面に
同時形成した。その後所定の温度で焼成することにより
本発明実施例並びに比較例のセラミック基板12を作製
した。
The method of forming the dividing groove 6 is as follows. First, a mold provided with a blade 8 for forming the dividing groove 6 is pressed against both main surfaces of the green sheet 5 by a progressive press method. The primary division grooves 1 were simultaneously formed on both main surfaces in the same manner. Thereafter, firing was performed at a predetermined temperature to produce the ceramic substrates 12 of the examples of the present invention and the comparative examples.

【0034】チップ抵抗器11の製造方法は、前述の図
11に示すチップ抵抗器11の製造工程に同じで、本発
明実施例は、まず両主面に電極14と、格子内領域3の
短辺側3aに形成された一次分割溝1の基板厚み方向に
対応する分割溝6の深い方の主面に抵抗13、保護膜1
5を形成した。次に分割しようとする上記一次分割溝1
に、前述の図7(a)に示す分割装置の押さえ部18と
割り部19を連結部23のシーソー機構を介し駆動軸2
2で押圧力を加え分割した。そのあとに、この分割され
たバー状基板4の端面に電極14を形成し、最後の二次
分割は、抵抗形成面を下にし従来のローラー方式により
裏面から押圧力を加え分割した。
The manufacturing method of the chip resistor 11 is the same as the manufacturing process of the chip resistor 11 shown in FIG. 11 described above. In the embodiment of the present invention, first, the electrodes 14 and the short The resistance 13 and the protective film 1 are provided on the deeper main surface of the divisional groove 6 corresponding to the thickness direction of the substrate of the primary divisional groove 1 formed on the side 3a.
5 was formed. Next, the primary dividing groove 1 to be divided
In addition, the pressing portion 18 and the split portion 19 of the splitting device shown in FIG.
The pressing force was applied at 2 to divide. After that, the electrode 14 was formed on the end face of the divided bar-shaped substrate 4, and the final secondary division was performed by applying a pressing force from the back side by the conventional roller method with the resistance forming side down.

【0035】また、比較例のセラミック基板12並びに
チップ抵抗器11の製造工程や一次分割溝1、二次分割
溝2の分割装置も、本発明実施例と同じであるが、分割
方向は一次分割溝1、二次分割溝2とも抵抗形成面から
押圧力を加え分割する方法とした。
The manufacturing process of the ceramic substrate 12 and the chip resistor 11 of the comparative example and the dividing device for the primary dividing groove 1 and the secondary dividing groove 2 are the same as those of the embodiment of the present invention, but the dividing direction is the primary dividing. Both the groove 1 and the secondary division groove 2 were divided by applying a pressing force from the resistance forming surface.

【0036】本発明実施例並びに比較例について、グリ
ーンシート5への分割溝6の形成からチップ抵抗器11
の製造工程である二次分割溝2の分割時点までの、グリ
ーンシート5の破れやセラミック基板12の割れ不良、
バー折れ不良、分割バリ不良の発生率について表1に示
した。尚、分割バリについては、その大きさが15μm
以上のものをバリ不良とした。
With respect to the examples of the present invention and the comparative example, the formation of the dividing groove 6 in the green sheet 5 and the formation of the chip resistor 11
The green sheet 5 is broken or the ceramic substrate 12 is not cracked until the secondary dividing groove 2 is divided, which is the manufacturing process of
Table 1 shows the occurrence rates of bar break failure and split burr failure. The size of the divided burrs is 15 μm.
The above was regarded as a burr defect.

【0037】また、マイクロクラック7の発生について
は、印刷等を施していないセラミック基板12につい
て、本発明実施例、比較例とも各々5シートずつ分割溝
6へ油性赤色マジックインクで着色した後、分割し各シ
ート任意の5点について、その分割断面を工具顕微鏡で
観察し基板厚み方向へのマイクロクラック7の深さを測
定しその平均値を表1に記載した。
Regarding the occurrence of the microcracks 7, the ceramic substrate 12 on which no printing or the like was applied was colored with oily red magic ink into the dividing grooves 6 by 5 sheets each in each of the examples and comparative examples of the present invention, and then divided. At any five points on each sheet, the divided cross section was observed with a tool microscope, the depth of the microcracks 7 in the substrate thickness direction was measured, and the average value was shown in Table 1.

【0038】[0038]

【表1】 [Table 1]

【0039】この結果から、比較例は、一次分割溝1の
両主面の合計深さを基板厚みTの50%とし、二次分割
溝2の両主面の合計深さは基板厚みTの30%、また一
次分割溝1並びに二次分割溝2ともに抵抗形成面をその
裏面側より深く、かつ抵抗形成面の分割溝6の開き角θ
を30゜と狭くしているため、抵抗形成面側一次分割溝
1aに18.5μm、抵抗形成面側二次分割溝2aに
8.2μmの深さのマイクロクラック7が発生してい
て、グリーンシート5の分割溝6の形成時の破れ、セラ
ミック基板12の焼成時の割れ、チップ抵抗器11の製
造工程の印刷、焼成時の割れ、並びにローラー方式によ
る一次分割溝1の二次分割溝2が割れるバー折れ不良並
びに分割バリ不良と二次分割溝2の分割バリ不良のいず
れも多発し、不良率の合計は52.7%と高かった。
From these results, in the comparative example, the total depth of both main surfaces of the primary division groove 1 was set to 50% of the substrate thickness T, and the total depth of both main surfaces of the secondary division groove 2 was set to the substrate thickness T. 30%, the resistance forming surface of each of the primary division groove 1 and the secondary division groove 2 is deeper than the back surface side, and the opening angle θ of the division groove 6 of the resistance formation surface.
Is reduced to 30 °, microcracks 7 having a depth of 18.5 μm are formed in the primary divisional groove 1a on the resistance forming surface side and 8.2 μm in the secondary divisional groove 2a on the resistance formation surface side, and green is formed. Breakage during the formation of the dividing groove 6 of the sheet 5, cracking during firing of the ceramic substrate 12, printing during the manufacturing process of the chip resistor 11, cracking during firing, and the secondary dividing groove 2 of the primary dividing groove 1 by the roller method. In addition, cracking failure of the bar, cracking failure of the divided burrs, and failure of the divided burrs of the secondary dividing groove 2 occurred frequently, and the total failure rate was as high as 52.7%.

【0040】これに対し、本発明のチップ抵抗器用セラ
ミック基板12は、不良率の合計が高いものでも4.5
%であり、歩留まりを高くできることがわかる。
On the other hand, the ceramic substrate 12 for a chip resistor of the present invention has a high total defective rate of 4.5 even if the total defective rate is high.
%, Which indicates that the yield can be increased.

【0041】本発明実施例の中でも、一次分割溝1の基
板の厚みTに対する両主面の合計深さが9%である試料
Aは、一次分割溝1の分割バリ不良が0.4%と高く、
また、一次分割溝1の基板の厚みTに対する両主面の合
計深さが21%の試料Eは、グリーンシート5への分割
溝6形成時の破れが2.8%と多発した。従って、一次
分割溝1の両主面の合計深さの好適な範囲は、基板の厚
みTに対し、10〜20%である試料B、C、Dであっ
た。二次分割溝2の両主面の合計深さは試料A〜Eま
で、基板の厚みTに対し25%であったが、特に問題は
なかった。
Among the embodiments of the present invention, in the sample A in which the total depth of both the main surfaces with respect to the thickness T of the substrate of the primary division groove 1 is 9%, the split burr defect of the primary division groove 1 is 0.4%. high,
Further, in the sample E in which the total depth of both the main surfaces of the primary division groove 1 with respect to the thickness T of the substrate was 21%, the breakage when the division groove 6 was formed in the green sheet 5 was frequently 2.8%. Therefore, the preferable range of the total depth of both the main surfaces of the primary division groove 1 was Samples B, C, and D which were 10 to 20% of the thickness T of the substrate. The total depth of both main surfaces of the secondary dividing groove 2 was 25% of the thickness T of the substrate for the samples A to E, but there was no particular problem.

【0042】本発明実施例の不良率が比較例より著しく
低下出来た理由として、前述の分割溝6の合計深さの設
定に加え、二次分割溝2の抵抗形成面を浅くしその裏面
を深くすることによって、抵抗13、保護膜15が形成
されセラミック基板12が谷型に反っても、一次分割の
際に二次分割溝2が割れるバー折れ不良の発生が抑えら
れたことと、また、さらに分割溝6直下へのマイクロク
ラック7の発生は、分割溝6の深さが浅いために全体的
に少なく、いずれの試料も開き角θが30゜と狭い抵抗
形成面側一次分割溝1a、裏面側二次分割溝2bに4.
7μm以下、おのおのその反対側の開き角θを40゜と
広くした分割溝6には0.7μm以下程度のマイクロク
ラック7の発生であり、前述の各不良率のアップに影響
しなかったためである。
The reason why the defect rate of the embodiment of the present invention was significantly lower than that of the comparative example is that, in addition to the above-mentioned setting of the total depth of the division grooves 6, the resistance forming surface of the secondary division groove 2 was made shallow and its back surface was made By increasing the depth, even if the resistor 13 and the protective film 15 are formed and the ceramic substrate 12 warps into a valley shape, the occurrence of a bar break defect in which the secondary division groove 2 is broken at the time of primary division is suppressed. Further, the occurrence of microcracks 7 immediately below the dividing groove 6 is generally small because the depth of the dividing groove 6 is shallow, and in all the samples, the opening angle θ is as small as 30 ° and the primary dividing groove 1a on the resistance forming surface side is narrow. 3. In the back side secondary dividing groove 2b.
This is because micro-cracks 7 of about 0.7 μm or less were generated in the divided groove 6 having an opening angle θ of 7 μm or less and the opening angle θ on the opposite side being widened to 40 °, and did not affect the increase in the above-described respective defective rates. .

【0043】以上の結果より、厚みか200±30μm
で、格子内領域3の寸法が600μm×300μm以下
のセラミック基板12の抵抗形成面側一次分割溝1aの
深さを20±10μm、裏面側一次分割溝1bの深さは
10±5μm、抵抗形成面側二次分割溝2aの深さは1
0±5μm、裏面側二次分割溝2bの深さは40±10
μmとし、分割溝6の開き角θを、抵抗形成面側一次分
割溝1a並びに裏面側二次分割溝2bを30゜、裏面側
一次分割溝1b並びに抵抗形成面側二次分割溝2aを4
0゜とすることにより、薄板で小型のチップ抵抗器11
を歩留まりを落とさずに、また、効率の高い自動機ライ
ンで製造することが出来る。
According to the above results, the thickness was 200 ± 30 μm
In the ceramic substrate 12 in which the size of the in-grating region 3 is not more than 600 μm × 300 μm, the depth of the resistance forming surface side primary division groove 1a of the ceramic substrate 12 is 20 ± 10 μm, and the depth of the back surface side primary division groove 1b is 10 ± 5 μm. The depth of the surface side secondary division groove 2a is 1
0 ± 5 μm, the depth of the back side secondary division groove 2 b is 40 ± 10
μm, the opening angle θ of the dividing groove 6 is 30 ° for the resistance forming surface side primary dividing groove 1a and the back side secondary dividing groove 2b, and 4 degrees for the back side primary dividing groove 1b and the resistance forming surface side secondary dividing groove 2a.
By setting 0 °, a thin and small chip resistor 11 is formed.
Can be manufactured with a highly efficient automatic machine line without lowering the yield.

【0044】[0044]

【発明の効果】以上のように、本発明のチップ抵抗器用
セラミック基板は、一次分割溝の両主面の合計深さを二
次分割溝の両主面の合計深さより浅く、また抵抗形成面
を裏面より深く形成し、かつ後述する分割方法で良好に
分割出来る深さとし、上記二次分割溝の深さはセラミッ
ク基板並びにチップ抵抗器の製造工程において割れの発
生率が低く抑えられる範囲の深さで、かつ抵抗形成面を
裏面より浅く形成するもので、一次分割溝の分割はシー
ソー機構をもつ連結部を介し基板の押さえ部と割部を駆
動軸で下動させ抵抗形成面から押圧する方法で行い、二
次分割溝の分割は抵抗形成面の裏面から上記の方式或い
は従来のローラー方式で押圧することにより、厚みが2
30μm、格子内領域が600×300μm以下のセラ
ミック基板においても、セラミック基板の製造工程並び
にチップ抵抗器の製造工程での割れや一次分割溝の分割
時のバー折れ不良、分割バリ不良の発生を抑え、また、
効率の高い自動機ラインで製造することが出来る。
As described above, according to the ceramic substrate for a chip resistor of the present invention, the total depth of both main surfaces of the primary division groove is smaller than the total depth of both main surfaces of the secondary division groove, and the resistance forming surface is formed. Is formed deeper than the back surface, and a depth that can be satisfactorily divided by a dividing method described later. By the way, the resistance forming surface is formed shallower than the back surface, and the division of the primary division groove is performed by lowering the holding portion and the split portion of the substrate with the drive shaft via the connecting portion having the seesaw mechanism and pressing from the resistance forming surface. The secondary division groove is divided by the above-mentioned method or the conventional roller method by pressing from the back surface of the resistance forming surface to have a thickness of 2%.
Even in the case of a ceramic substrate having a size of 30 μm and a lattice area of 600 × 300 μm or less, the occurrence of cracks in the ceramic substrate manufacturing process and chip resistor manufacturing process, bar breakage when dividing the primary division groove, and division burr defect is suppressed. ,Also,
It can be manufactured with a highly efficient automatic machine line.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のチップ抵抗器用セラミック基板の斜視
図である。
FIG. 1 is a perspective view of a ceramic substrate for a chip resistor according to the present invention.

【図2】抵抗が形成された本発明のチップ抵抗器用セラ
ミック基板の斜視図である。
FIG. 2 is a perspective view of a ceramic substrate for a chip resistor of the present invention on which a resistor is formed.

【図3】(a)はチップ抵抗器用セラミック基板の平面
図で、(b)は焼成時の引っ張り応力を示すグリーンシ
ートの平面図である。
FIG. 3A is a plan view of a ceramic substrate for a chip resistor, and FIG. 3B is a plan view of a green sheet showing a tensile stress during firing.

【図4】抵抗、保護膜形成後のセラミック基板の断面図
である。
FIG. 4 is a cross-sectional view of the ceramic substrate after forming a resistor and a protective film.

【図5】(a)(b)は引き裂き応力の大きさを示すグ
リーンシートの断面図で、(c)はマイクロクラックの
発生を示すグリーンシートの断面図である。
FIGS. 5A and 5B are cross-sectional views of a green sheet showing the magnitude of a tearing stress, and FIG. 5C is a cross-sectional view of a green sheet showing the occurrence of microcracks.

【図6】グリーンシートの断面図である。FIG. 6 is a sectional view of a green sheet.

【図7】(a)(b)(c)は本発明のチップ抵抗器用
セラミック基板の分割装置の分割原理を示す断面図であ
る。
FIGS. 7A, 7B and 7C are cross-sectional views showing the principle of division of the device for dividing a ceramic substrate for a chip resistor according to the present invention.

【図8】チップ抵抗器の断面図である。FIG. 8 is a sectional view of a chip resistor.

【図9】チップ抵抗器用セラミック基板の斜視図であ
る。
FIG. 9 is a perspective view of a ceramic substrate for a chip resistor.

【図10】グリーンシートへ金型により分割溝を形成す
る一例を示す断面図である。
FIG. 10 is a cross-sectional view showing an example of forming a dividing groove in a green sheet by using a mold.

【図11】チップ抵抗器の製造工程図である。FIG. 11 is a manufacturing process diagram of the chip resistor.

【図12】(a)(b)は従来の分割装置の分割原理の
一例を示す断面図である。
FIGS. 12A and 12B are cross-sectional views illustrating an example of a dividing principle of a conventional dividing device.

【図13】(a)(b)はチップ抵抗器用セラミック基
板の分割例を示す平面図である。
13A and 13B are plan views showing examples of dividing a ceramic substrate for a chip resistor.

【符号の説明】[Explanation of symbols]

1:一次分割溝 1a:抵抗形成面側一次分割溝 1
b:裏面側一次分割溝 2:二次分割溝 2a:抵抗形成面側二次分割溝 2
b:裏面側二次分割溝 3:格子内領域 3a:格子内領域の短辺側 3b:格
子内領域の長辺側 4:バー状基板 5:グリーンシート 6:分割溝
7:マイクロクラック 8,8a,8b:刃 11:チップ抵抗器 12:セラミック基板 13:抵抗 14:電極 1
5:保護膜 16:大径ローラー 17:小径ローラー 18:押さ
え部 19:割部 20:下シート 21:クランク機構 22:駆動部
23:連結部 24:ストッパー機構 P1:一次分割溝のピッチ P
2:二次分割溝のピッチ T:厚み θ:開き角
1: primary division groove 1a: primary division groove 1 on the resistance forming surface side
b: back side primary division groove 2: secondary division groove 2a: resistance forming surface side secondary division groove 2
b: back side secondary division groove 3: area within lattice 3a: short side of area within lattice 3b: long side of area within lattice 4: bar-shaped substrate 5: green sheet 6: division groove
7: Micro crack 8, 8a, 8b: Blade 11: Chip resistor 12: Ceramic substrate 13: Resistance 14: Electrode 1
5: Protective film 16: Large-diameter roller 17: Small-diameter roller 18: Holding section 19: Split section 20: Lower sheet 21: Crank mechanism 22: Drive section
23: Connecting part 24: Stopper mechanism P1: Pitch of primary division groove P
2: Pitch of secondary division groove T: Thickness θ: Open angle

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】格子状の分割溝を両主面に対応して配列
し、長方形状とした格子内領域の短辺側に形成された一
次分割溝の両主面の合計深さが、上記格子内領域の長辺
側に形成された二次分割溝の両主面の合計深さよりも浅
く、かつ上記一次分割溝は抵抗形成面が裏面より深く、
上記二次分割溝は裏面が抵抗形成面より深いことを特徴
とするチップ抵抗器用セラミック基板。
1. A grid-shaped dividing groove is arranged corresponding to both main surfaces, and the total depth of both main surfaces of a primary dividing groove formed on the short side of a rectangular in-grating region is as described above. The shallower than the total depth of the two main surfaces of the secondary division groove formed on the long side of the region in the lattice, and the primary division groove has a resistance forming surface deeper than the back surface,
The ceramic substrate for a chip resistor, wherein the secondary division groove has a back surface deeper than a resistance forming surface.
【請求項2】上記セラミック基板の厚みが200±30
μm、上記格子内領域が600μm×300μm以下で
あって、上記一次分割溝の抵抗形成面の深さが20±1
0μm、裏面の深さが10±5μm、上記二次分割溝の
抵抗形成面の深さが10±5μm、裏面の深さが40±
10μmであることを特徴とする請求項1記載のチップ
抵抗器用セラミック基板。
2. The thickness of said ceramic substrate is 200 ± 30.
μm, the area in the lattice is 600 μm × 300 μm or less, and the depth of the resistance forming surface of the primary division groove is 20 ± 1.
0 μm, the depth of the back surface is 10 ± 5 μm, the depth of the resistance forming surface of the secondary division groove is 10 ± 5 μm, and the depth of the back surface is 40 ±
2. The ceramic substrate for a chip resistor according to claim 1, wherein the thickness is 10 [mu] m.
【請求項3】上記一次分割溝の抵抗形成面および上記二
次分割溝の裏面の開き角が30±10゜、上記一次分割
溝の裏面および上記二次分割溝の抵抗形成面の開き角が
40±5゜であることを特徴とする請求項2記載のチッ
プ抵抗器用セラミック基板。
3. An opening angle between the resistance forming surface of the primary dividing groove and the back surface of the secondary dividing groove is 30 ± 10 °, and an opening angle of the back surface of the primary dividing groove and the resistance forming surface of the secondary dividing groove is 30 °. 3. The ceramic substrate for a chip resistor according to claim 2, wherein the angle is 40 ± 5 °.
JP2000158829A 2000-05-23 2000-05-29 Ceramic plate board for chip resistor Pending JP2001338806A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000158829A JP2001338806A (en) 2000-05-29 2000-05-29 Ceramic plate board for chip resistor
CN 01118979 CN1201342C (en) 2000-05-23 2001-05-23 Porcelain base-plate for formation of chip resistance and mfg. method of chip-resistance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000158829A JP2001338806A (en) 2000-05-29 2000-05-29 Ceramic plate board for chip resistor

Publications (1)

Publication Number Publication Date
JP2001338806A true JP2001338806A (en) 2001-12-07

Family

ID=18663242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000158829A Pending JP2001338806A (en) 2000-05-23 2000-05-29 Ceramic plate board for chip resistor

Country Status (1)

Country Link
JP (1) JP2001338806A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010225910A (en) * 2009-03-24 2010-10-07 Ngk Spark Plug Co Ltd Multiple patterning ceramic wiring board
JP2010272713A (en) * 2009-05-22 2010-12-02 Panasonic Corp Method of manufacturing thin-film chip resistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010225910A (en) * 2009-03-24 2010-10-07 Ngk Spark Plug Co Ltd Multiple patterning ceramic wiring board
JP2010272713A (en) * 2009-05-22 2010-12-02 Panasonic Corp Method of manufacturing thin-film chip resistor

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