JP2001332440A - Method of manufacturing laminated electronic component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a laminated electronic component which has electrodes connected together inside and outer electrodes formed on its one surface increased in effective area and decreased in area which is required for mounting. SOLUTION: A first through-hole connected electrically to inner electrodes and a second through-hole insulated from the inner electrodes are provided on a ceramic sheet, a conductive paint is applied onto the ceramic sheet to form the inner electrodes, and connecting electrodes are provided to the first and second through-holes. Each time a ceramic sheet is laminated, this process is carried out repeatedly. The connection structure of the inner electrodes of the laminated ceramic sheets is determined based, for instance, on parallel connection used in a laminated ceramic capacitor, in which each of odd- numbered and even-numbered inner electrodes is connected together, in parallel respectively or in a series connection used in a laminated coil in which inner electrodes are connected in series.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a multilayer electronic component such as a multilayer ceramic capacitor and a multilayer coil.

[0002]

2. Description of the Related Art A conventional method for manufacturing a multilayer electronic component will be described by taking a multilayer ceramic capacitor as an example. Conventionally, this type of capacitor is generally manufactured by first forming internal electrode layers B1, B2 on the surfaces of a plurality of unfired ceramic sheets (green sheets) A1, A2, A3, A4 as shown in FIG. , B3, B4 are alternately shifted and formed by printing, and then these ceramic sheets A1, A2, A3,
As shown in FIG. 7, A4 is overlaid and laminated, and an unfired ceramic sheet cover C for covering the internal electrode layer B1 on the uppermost ceramic sheet A1 is overlaid and laminated. The body is cut along the vertical and horizontal lattice cutting lines D1 and D2 to divide the laminated chip pieces 1 into pieces, and each of the laminated chip pieces 1 is fired, and
As shown in FIG. 8, this is performed by forming end face electrode layers 2 on both left and right end faces 1a and 1b of each laminated chip piece 1.

[0003]

As described above, in a conventional multilayer electronic device such as a multilayer ceramic capacitor, opposing internal electrodes are laminated and connected in the same direction. The external electrode 2 coated with a thick film was used.

For this reason, as shown in FIG. 9, it is necessary to provide an internal / external electrode connection portion d2 in order to prevent displacement of the internal electrode pattern. This inner / outer electrode connection portion d
No. 2 is a waste of expensive internal electrodes (for example, palladium or the like) irrespective of the capacity acquisition. In addition, due to the inner and outer electrode connection portions d2, there is a limitation in increasing the area of the capacitance acquisition portion d1. Length of laminated chip piece 1 (d1 + 2
D2) is, for example, about 0.8 to 1.0 mm, and the inner and outer electrode connection parts d2 are about 0.1 to 0.2 mm, so that the influence on the capacity acquisition part d1 is large. In addition, since it is necessary to form the external electrode 2 coated with a thick film, the size of the laminated chip piece 1 is limited in consideration of the need.

Further, when the electronic component chip is mounted on a printed circuit board or the like, since the fillet portion 3 is formed by soldering, the mounting area becomes large.

In view of the above, the present invention increases the effective area of the electronic component chip by connecting the electrodes inside the chip of the multilayer electronic component and forming the external electrodes only on one surface. An object of the present invention is to provide a method for manufacturing a multilayer electronic component, which requires a small area during mounting.

[0007]

According to a first aspect of the present invention, there is provided a method of manufacturing a laminated electronic component, comprising the steps of: laminating an unfired ceramic sheet; and electrically connecting the ceramic sheet to an internal electrode on the ceramic sheet. A second step of forming a first through hole to be formed, and a second through hole to be insulated from the internal electrode on the ceramic sheet, wherein the first and second through holes are formed. Applying a conductive paint on the formed ceramic sheet to form the internal electrode, and forming a connection electrode in the first and second through-holes. When the first to third steps are repeated each time and the internal electrodes on the ceramic sheets to be laminated are connected in series,
Is connected to the internal electrode of the ceramic sheet immediately below, and the connection electrode of the second through hole is connected to the connection electrode of the second through hole of the ceramic sheet immediately below. When the internal electrodes on the ceramic sheets to be laminated are connected in parallel for each odd number and even number, the connection electrode of the first through hole is connected to the connection electrode of the second through hole of the ceramic sheet immediately below. The connection electrode of the second through hole is configured to be connected to the connection electrode of the first through hole of the ceramic sheet immediately below.

In the method for manufacturing a multilayer electronic component according to the first aspect of the present invention, the first through hole that is to be conductively connected to the internal electrode and the first through hole that is to be insulated from the internal electrode are formed in the ceramic sheet. Then, a conductive paint is applied on the ceramic sheet to form internal electrodes, and connection electrodes are formed in the first and second through holes. Such a process is repeated each time a ceramic sheet is laminated. The connection configuration between the internal electrodes of the ceramic sheets to be laminated is determined in accordance with whether the connection configuration is parallel connection for every odd number and even number, for example, as in a multilayer ceramic capacitor, or in series connection, for example, as in a multilayer coil. Determine the connection configuration between the ceramic sheets.

That is, when the internal electrodes on the respective ceramic sheets to be laminated are connected in series, the connection electrode of the first through hole is connected to the internal electrode of the ceramic sheet immediately below, and the second through hole is connected to the internal electrode of the ceramic sheet immediately below. Is connected to the connection electrode of the second through hole of the ceramic sheet immediately below. Further, when the internal electrodes on each of the laminated ceramic sheets are connected in parallel for each odd and even number, the connection electrodes of the first through holes are connected to the second through holes of the ceramic sheet immediately below, Second
The connection electrode of the through hole is connected to the connection electrode of the first through hole of the ceramic sheet immediately below.

Thus, according to the manufacturing method of the present invention,
Connection between electrodes can be established inside the chip of a multilayer electronic component such as a multilayer ceramic capacitor and a multilayer coil, and external electrodes can be formed on only one surface. Therefore, the effective area of the electronic component chip can be increased, and the required area for mounting can be reduced.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a method for manufacturing a multilayer electronic component according to the present invention will be described with reference to the drawings.

First, FIGS. 1 to 3 are views showing a method for manufacturing a multilayer ceramic capacitor according to a first embodiment of the present invention. In the present invention, a large number of capacitor chips are simultaneously formed in a matrix in a vertical and horizontal manner per one ceramic sheet (green sheet). However, in each of the following drawings, a single capacitor is used for easy understanding. As shown.

In FIG. 1, A and B are lower cover layers, C to F are electrode layers, and G and H are upper cover layers. FIG. 1A shows a top view of each of the layers A to H, and FIG. 2B shows a cross-sectional view along the center line of each of the layers A to H. This figure is shown by way of example, and the lower cover layer,
The number of the electrode layers and the upper cover layer is an arbitrary number. In particular, the number of the electrode layers is determined according to a required capacitance value.

The lower cover layer A is formed as follows. First, an unfired ceramic sheet (green sheet) 11A is prepared. This ceramic sheet 11A
Will be the dielectric part of the capacitor, but in its predetermined position,
Two through holes are formed by laser processing or the like. Next, a conductive paint is applied to the ceramic sheet 11A in which two through holes are formed, with the mask being covered.
As a result, the conductive paint enters the two through holes,
Connection electrodes 12A and 13A are formed. This connection electrode 1
2A and 13A electrically connect the upper surface side and the lower surface side of the ceramic sheet 11A.

The predetermined positions at which the through holes are formed are determined by all the cover layers A, B, G, H and the electrode layers C.
To F are the same position.

Next, as for the lower cover layer B, the unsintered ceramic sheet 11B is aligned and stacked on the lower cover layer A. In this state, as in the case of the lower cover layer A, two through holes are formed, a conductive paint is applied in a state where the mask is covered, and the conductive paint enters the two through holes and the connection electrodes 12B and 13B are formed. Is formed. In this state, the connection electrode 12A and the connection electrode 12B are conductively connected, and the connection electrode 13A and the connection electrode 13B are conductively connected.

Next, the electrode layer C is formed as follows. First, the unsintered ceramic sheet 11C is aligned and stacked on the lower cover layer B. In this state, two through holes are formed in the ceramic sheet 11C. One of the two through holes is a first through hole to be conductively connected to the internal electrode of the electrode layer C itself, and the other through hole is insulated from the internal electrode of the electrode layer C itself. This is the second through hole to be formed.

A conductive paint is applied to the ceramic sheet 11C in which the first and second two through holes are formed while the mask is covered. In this mask, the connection electrode 13C and the internal electrode 14C formed in the first through hole (the left through hole in the figure in the electrode layer C) are integrally conductively connected, and the second through hole (the electrode layer C C has such a shape as to insulate the connection electrode 12C and the internal electrode 14C formed in the through hole on the right side in the figure).

Therefore, by applying a conductive paint to the ceramic sheet 11C with the mask covered, the internal electrode 14C is formed and the first and second electrodes 14C are formed.
The conductive paint penetrates into the two through holes, and the connection electrode 12
C and 13C are formed. At this time, the connection electrode 13C of the first through hole is conductively connected integrally with the internal electrode 14C, and the connection electrode 12C of the second through hole is connected to the internal electrode 1C.
4C and insulated. The connection electrode 12B and the connection electrode 12C are conductively connected, and the connection electrode 13B and the connection electrode 13C are conductively connected.

Next, the electrode layer D is formed as follows. First, the unsintered ceramic sheet 11D is aligned and stacked on the electrode layer C. In this state, two through holes are formed in the ceramic sheet 11D. One of the two through holes is a first through hole to be conductively connected to the internal electrode of the electrode layer D itself, and the other through hole is insulated from the internal electrode of the electrode layer D itself. This is the second through hole to be formed.

A conductive paint is applied to the ceramic sheet 11D in which the first and second two through holes are formed while the mask is covered. In this mask, the connection electrode 12D and the internal electrode 14D formed in the first through-hole (the right through-hole in the figure in this electrode layer D) are integrally conductively connected, and the second through-hole (this electrode layer D). D has a shape such that the connection electrode 13D formed in the through hole on the left side in the figure) and the internal electrode 14D are insulated.

Therefore, by applying a conductive paint to the ceramic sheet 11D with the mask covered, the internal electrode 14D is formed, and the first and second electrodes 14D are formed.
The conductive paint penetrates into the two through holes, and the connection electrode 12
D and 13D are formed. At this time, the connection electrode 12D of the first through hole is conductively connected integrally with the internal electrode 14D, and the connection electrode 13D of the second through hole is connected to the internal electrode 1D.
Insulated from 4D. The connection electrode 12C and the connection electrode 12D are conductively connected, and the connection electrode 13B (that is, the internal electrode 14C) and the connection electrode 13D are conductively connected.

Next, the electrode layer E is formed in the same manner as the formation of the electrode layer C. That is, as a result, by applying the conductive paint to the ceramic sheet 11E in a state where the mask is covered, the internal electrode 14E is formed, and the conductive paint enters the first and second two through-holes, and the connection is established. Electrodes 13E and 12E are formed. At this time, the connection electrode 13E of the first through hole is conductively connected integrally with the internal electrode 14E, and the connection electrode 12E of the second through hole is insulated from the internal electrode 14E. In addition, the connection electrode 12D
(Ie, the internal electrode 14D) and the connection electrode 12E are conductively connected, and the connection electrode 13D and the connection electrode 13E are conductively connected.

Next, the electrode layer F is formed in the same manner as the formation of the electrode layer D. That is, as a result, the conductive paint is applied to the ceramic sheet 11F in a state where the mask is covered, thereby forming the internal electrode 14F, and at the same time, the conductive paint penetrates into the first and second through holes, and the connection is established. Electrodes 12F and 13F are formed. At this time, the connection electrode 12F of the first through hole is conductively connected integrally with the internal electrode 14F, and the connection electrode 13F of the second through hole is insulated from the internal electrode 14F. Further, the connection electrode 12E and the connection electrode 12F are conductively connected, and the connection electrode 13E
(Ie, the internal electrode 14E) and the connection electrode 13F are conductively connected.

Next, as for the upper cover layer G, an unsintered ceramic sheet 11G is aligned and stacked on the electrode layer F. In this state, two through-holes are formed, a conductive paint is applied in a state where the mask is covered, and the conductive paint enters the two through-holes and the connection electrodes 12G, 13
G is formed. In this state, the connection electrode 12F (that is, the internal electrode 14F) and the connection electrode 12G are conductively connected,
The connection electrode 13F and the connection electrode 13G are conductively connected.

Next, as the last layer, the upper cover layer H, the unsintered ceramic sheet 11H is aligned and stacked on the upper cover layer G. In this state, two through holes are formed, a conductive paint is applied in a state where the mask is covered, and the conductive paint enters the two through holes to form connection electrodes 12H and 13H. In this state, the connection electrode 12G and the connection electrode 12H are conductively connected, and the connection electrode 13G and the connection electrode 13H are conductively connected.

As described above, the cover layers A, B, G, H
Are unfired ceramic sheets 11A, 11b, 11
G and 11H are prepared or stacked, two through holes serving as connection electrodes are formed in this ceramic sheet, and a conductive paint is applied thereon via a mask to form connection electrodes 12H.
A, 12B, 12G, 12H, 13A, 13B, 13
G and 13H are formed.

The electrode layers C to F are formed by stacking unfired ceramic sheets 11C to 11F. The ceramic sheets have first through holes to be electrically connected to internal electrodes on the ceramic sheets. A second through hole to be insulated from the internal electrode on the ceramic sheet is formed. A conductive paint is applied on the ceramic sheet on which the first and second through holes are formed to form internal electrodes 14C to 14F, and connection electrodes 12C to 12F are formed in the first and second through holes.
13C to 13F are formed. Such a process is repeated each time an unfired ceramic sheet to be an electrode layer is laminated. The connection configuration between these electrode layers is such that the internal electrodes on each ceramic sheet to be laminated are connected in parallel for each odd and even number in order to form a multilayer capacitor. Example, 12F)
Is connected to the connection electrode (eg, 12E) of the second through hole of the ceramic sheet immediately below, and the connection electrode (eg, 13F) of the second through hole is connected to the connection electrode of the first through hole of the ceramic sheet immediately below. Connected to a connection electrode (eg, 13E).

Thereafter, the laminated body laminated as shown in FIG. 1 is cut along, for example, vertical and horizontal lattice-shaped cutting lines and divided into laminated ceramic capacitor chip pieces, and each of the laminated chip pieces is fired. Then, external electrodes are formed on the upper and lower surfaces (upper cover side, lower cover side) of each of the laminated chip pieces to obtain a laminated ceramic capacitor.

FIGS. 2 (a) and 2 (b) are an external view of the multilayer ceramic capacitor 10 manufactured as described above, and a diagram showing the internal connection structure. As shown in FIG. 2, the connecting electrodes 1 are vertically arranged on the multilayer ceramic capacitor 10.
2 (comprising connection electrodes 12A to 12H) and connection electrode 1
3 (comprising the connection electrodes 13A to 13H). The connection electrodes 12 are connected to the even-numbered internal electrodes 14D, 14D.
F is conductively connected, and the internal electrodes 14C and 14E on the odd-numbered side are conductively connected to the connection electrode 12. An external electrode 15 connected to the connection electrode 12 and an external electrode 16 connected to the connection electrode 13 are formed on the upper surface side and the lower surface side.

FIG. 3 shows another multilayer ceramic capacitor 2.
0 is a diagram showing an external view of FIG. In FIG. 3, the external electrodes 25,
26 is formed only on the upper surface side (or the lower surface side). When the external electrodes 25 and 26 are formed on one surface side of the multilayer ceramic capacitor 20 as shown in FIG. 3, the through holes of the upper covers G and H (or the lower covers A and B) are not formed in FIG. Therefore, it is not necessary to form the internal electrode.

According to the manufacturing method of the multilayer ceramic capacitor according to the first embodiment, the internal electrode portions (capable of connecting the internal and external electrodes d2 in the conventional example) unnecessary for obtaining the capacitance can be reduced, so that the cost can be reduced. Can be planned.

On the other hand, since the internal electrode portions not required for obtaining the capacitance can also be used for obtaining the capacitance, a multilayer ceramic capacitor having a high capacitance (per size) can be formed.

Further, since it is not necessary to form the external electrodes 2 on both sides of the multilayer ceramic capacitor, the capacitor body can be enlarged by the reduction of the external electrodes, and a multilayer ceramic capacitor having a high capacity can be formed. .

Further, when the multilayer ceramic capacitor is mounted on a printed circuit board or the like, no fillet portion is formed by soldering, so that the mounting area can be reduced.

As shown in FIG. 2, since external terminals can be formed on both the upper surface and the lower surface of the multilayer ceramic capacitor, the capacitor can be mounted in any direction. Further, the same type of electronic component chips (eg, capacitors, coils, resistors, etc.) can be mounted and connected to the multilayer ceramic capacitor.

FIGS. 4 and 5 are views showing a method of manufacturing a laminated coil according to a second embodiment of the present invention. In this embodiment, a large number of coil chips are simultaneously formed in a matrix in a vertical and horizontal manner per one ceramic sheet (green sheet). However, in each of the following drawings, a single coil is used for easy understanding. As shown.

In FIG. 4, A and B are lower cover layers, C to F are electrode layers, and G and H are upper cover layers. FIG. 1A shows a top view of each of the layers A to H, and FIG. 2B shows a cross-sectional view along the center line of each of the layers A to H. This figure is shown by way of example, and the lower cover layer,
The number of the electrode layers and the upper cover layer is an arbitrary number, and in particular, the number of the electrode layers is determined according to a required inductance value.

The lower cover layer A and the lower cover layer B are made of unfired ceramic sheets (green sheets) 31A,
1B is prepared and stacked.

Next, the electrode layer C is formed as follows. First, the unsintered ceramic sheet 31C is aligned and stacked on the lower cover layer B. In this state, the internal electrode 34 of the coil is placed on the ceramic sheet 31C.
A conductive paint is applied with a mask for forming C covered.

Accordingly, by applying a conductive paint to the ceramic sheet 31C with the mask covered, the internal electrode 34C of the coil is formed. This internal electrode 34
C has a point T1 as a starting point and a point U1 as an end point.

Next, the electrode layer D is formed as follows. First, the unsintered ceramic sheet 31D is aligned and stacked on the electrode layer C. In this state, two through holes are formed in the ceramic sheet 31D. Of the two through holes, the second through hole is provided at a position corresponding to the point T1 which is the starting point of the internal electrode 34C of the lower electrode layer C. Note that a second through hole is formed in each of the electrode layers and the cover layer stacked above this corresponding to the point T1, and finally an external electrode is formed. The other first through hole is provided at a point U2 which is a position corresponding to a point U1 which is an end point of the internal electrode 34C of the lower electrode layer C.

The conductive paint is applied to the ceramic sheet 31D in which the first and second through holes are formed while the mask is covered. This mask is shaped such that the connection electrode 32D is formed in the second through hole (point T2), and the first through hole (point U2) and the internal electrode 34D are integrally conductively connected. I have.

Accordingly, by applying a conductive paint to the ceramic sheet 31D with the mask covered, an internal electrode 34D having the starting point at point U2 and the ending point at point V1 is formed, and the first through electrode at point U2 is formed. The conductive paint enters the holes, and the connection electrodes 33D are formed. Further, the conductive paint enters the second through hole at the point T2, and the connection electrode 32D is formed. At this time, the connection electrode 32D of the second through hole is conductively connected to the point T1 which is the starting point of the internal electrode 34C of the electrode layer C. In addition, the connection electrode 33D of the first through hole
Represents a point U which is the end point of the internal electrode 34C of the electrode layer C.
1 is electrically conductively connected.

Next, the electrode layer E is formed as follows. First, the unsintered ceramic sheet 31E is positioned and stacked on the electrode layer D. In this state, two through holes are formed in the ceramic sheet 31E. One of the two through holes is provided at a position (point T2) corresponding to the connection electrode 32D of the lower electrode layer D. The other first through hole is provided at a point V2 which is a position corresponding to a point V1 which is an end point of the internal electrode 34D of the lower electrode layer D.

The conductive paint is applied to the ceramic sheet 31E in which the first and second two through holes are formed while the mask is covered. This mask is shaped so that the connection electrode 32E is formed in the second through hole (point T3) and the first through hole (point V2) and the internal electrode 34E are integrally and conductively connected. I have.

Accordingly, by applying a conductive paint to the ceramic sheet 31E with the mask covered, the internal electrode 34E having the starting point at the point V2 and the ending point at the point W1 is formed, and the first through electrode at the point V2 is formed. The conductive paint enters the holes, and the connection electrodes 33E are formed. Further, the conductive paint enters the second through hole at the point T3, and the connection electrode 32E is formed. At this time, the connection electrode 32E of the second through hole is conductively connected to the connection electrode 32D (point T2) of the electrode layer D. Further, the connection electrode 33E of the first through hole is conductively connected to a point V1 which is an end point of the internal electrode 34D of the electrode layer D.

Next, the electrode layer F is formed as follows. First, the unsintered ceramic sheet 31F is aligned and stacked on the electrode layer E. In this state, two through holes are formed in the ceramic sheet 31F. One of the two through holes is provided at a position (point T4) corresponding to the connection electrode 32E of the lower electrode layer E. The other first through hole is provided at a point W2 which is a position corresponding to a point W1 which is an end point of the internal electrode 34E of the lower electrode layer E.

The conductive paint is applied to the ceramic sheet 31F in which the first and second two through holes are formed while the mask is covered. This mask is shaped such that the connection electrode 32F is formed in the second through hole (point T4) and the first through hole (point W2) and the internal electrode 34F are integrally and conductively connected. I have.

Accordingly, by applying a conductive paint to the ceramic sheet 31F with the mask covered, an internal electrode 34F having a starting point at point W2 and an ending point at point X1 is formed, and the first through electrode at point W2 is formed. The conductive paint enters the holes, and the connection electrodes 33F are formed. Further, the conductive paint enters the second through hole at the point T4, and the connection electrode 32F is formed. At this time, the connection electrode 32F of the second through hole is conductively connected to the connection electrode 32E (point T3) of the electrode layer E. Further, the connection electrode 33F of the first through hole is conductively connected to a point W1 which is an end point of the internal electrode 34E of the electrode layer E.

Next, the upper cover layer G is formed as follows. First, the unsintered ceramic sheet 31G is positioned and stacked on the electrode layer F. In this state, two through holes are formed in the ceramic sheet 31G. One of the two through holes is provided at a position (point T5) corresponding to the connection electrode 32F of the lower electrode layer F. The other through hole is provided at a point X2 which is a position corresponding to a point X1 which is an end point of the internal electrode 34F of the lower electrode layer F.

A conductive paint is applied to the ceramic sheet 31G in which the first and second two through holes are formed while the mask is covered. This mask has a connection electrode 32G formed in a second through hole (point T5) and a connection electrode 33 in a first through hole (point X2).
The shape is such that G is formed.

Accordingly, by applying the conductive paint to the ceramic sheet 31G with the mask covered, the conductive paint enters the second through hole at the point T5, the connection electrode 32G is formed, and the first electrode at the point X2 is formed. The conductive paint penetrates into the through holes, and the connection electrodes 33G are formed. At this time, the connection electrode 32G of the second through hole is
It is conductively connected to the connection electrode 32F (point T4) of the electrode layer F. In addition, the connection electrode 33G of the first through hole
Is the point X which is the end point of the internal electrode 34F of the electrode layer F.
1 is electrically conductively connected.

Next, as the last layer, the upper cover layer H, the unsintered ceramic sheet 31H is aligned and stacked on the upper cover layer G. In this state, two through holes are formed, and a conductive paint is applied in a state where the mask is covered, and the conductive paint enters the two through holes to form connection electrodes 32H and 33H. In this state, the connection electrode 32G and the connection electrode 32H are conductively connected, and the connection electrode 33G and the connection electrode 33H are conductively connected.

FIG. 5 is a diagram schematically showing only the connection configuration of the laminated coil manufactured as shown in FIG.

In FIG. 5, the internal electrode 34C of the electrode layer C
Starting point T1 of the upper cover layer H through points T2 to T5
Is drawn out to the connection electrode 32H at the point T6.
This is one external terminal.

The end point U of the internal electrode 34C of the electrode layer C
1 is a connection electrode 33D (points U1-U2) -an internal electrode 34D of the electrode layer D-a connection electrode 33E (point V1-
V2) -Internal electrode 34E of electrode layer E-Connection electrode 33F
(Point W1-W2)-Internal electrode 34F of electrode layer F-
Connection electrode 33G (points X1-X2) -Connection electrode 33
H (points X2 to X3) are drawn out through a series path, and this is another external terminal. A series connection of these internal electrodes and connection electrodes functions as a coil.

As described above, the connection electrode of the first through hole is connected to the internal electrode of the ceramic sheet immediately below so that the internal electrodes on each of the stacked ceramic sheets are connected in series, and the second electrode is connected to the second electrode. By configuring so that the connection electrode of the through hole is connected to the connection electrode of the second through hole of the ceramic sheet immediately below, the internal electrodes on each stacked ceramic sheet are connected in series via the connection electrode. A multilayer capacitor is formed.

Thereafter, the laminated body laminated as shown in FIG. 4 is cut along, for example, a vertical and horizontal lattice-shaped cutting line to be divided into laminated coil chip pieces, and the laminated chip pieces are fired. Then, an external electrode is formed on one surface of each of the laminated chip pieces to form a laminated coil.

The laminated coil manufactured in this manner is
The appearance is similar to that shown in FIG. 3 as the multilayer ceramic capacitor 20.

According to the method of manufacturing the laminated coil according to the second embodiment, since the laminated coil is formed, the area required for obtaining the required inductance can be reduced.

Further, since it is not necessary to form external electrodes on both sides of the laminated coil, the coil element can be made larger by the reduction of the external electrodes, and a laminated coil having a large inductance can be formed.

Further, when the laminated coil is mounted on a printed circuit board or the like, no fillet portion is formed by soldering, so that the mounting area can be reduced.

[0064]

According to the first aspect of the present invention, in the method for manufacturing a multilayer electronic component, the first through hole to be conductively connected to the internal electrode is insulated from the ceramic sheet. And a conductive paint is applied to the ceramic sheet to form an internal electrode, and a connection electrode is formed in the first and second through holes. Such a process is repeated each time a ceramic sheet is laminated. The connection configuration between the internal electrodes of the ceramic sheets to be laminated is determined in accordance with whether the connection configuration is parallel connection for every odd number and even number, for example, as in a multilayer ceramic capacitor, or in series connection, for example, as in a multilayer coil. Determine the connection configuration between the ceramic sheets.

That is, when the internal electrodes on the respective ceramic sheets to be laminated are connected in series, the connection electrode of the first through hole is connected to the internal electrode of the ceramic sheet immediately below and the second through hole is connected. Is connected to the connection electrode of the second through hole of the ceramic sheet immediately below. Further, when the internal electrodes on each of the laminated ceramic sheets are connected in parallel for each odd and even number, the connection electrodes of the first through holes are connected to the second through holes of the ceramic sheet immediately below, Second
The connection electrode of the through hole is connected to the connection electrode of the first through hole of the ceramic sheet immediately below.

As described above, according to the production method of the present invention,
Connection between electrodes can be established inside the chip of a multilayer electronic component such as a multilayer ceramic capacitor and a multilayer coil, and external electrodes can be formed on only one surface. Therefore, the effective area of the electronic component chip can be increased, and the required area for mounting can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a method for manufacturing a multilayer ceramic capacitor according to a first embodiment of the present invention.

FIG. 2 is an external view of a multilayer ceramic capacitor according to the present invention and a diagram showing a connection configuration inside the multilayer ceramic capacitor.

FIG. 3 is another external view of the multilayer ceramic capacitor according to the present invention.

FIG. 4 is a diagram showing a method for manufacturing a laminated coil according to a second embodiment of the present invention.

FIG. 5 is a diagram showing an internal connection configuration of a laminated coil according to the present invention.

FIG. 6 is a diagram illustrating a method for manufacturing a conventional multilayer ceramic capacitor.

FIG. 7 is a diagram illustrating a method for manufacturing a conventional multilayer ceramic capacitor.

FIG. 8 is a structural diagram of a conventional multilayer ceramic capacitor.

FIG. 9 is a mounting state diagram of a conventional multilayer ceramic capacitor.

[Explanation of symbols]

 A, B Lower cover layer CF electrode layer G, H Upper cover layer 11A-11H Ceramic sheet 12A-12H, 13A-13H Connection electrode 14C-14F Internal electrode 31C-31H Ceramic sheet 32D-32H, 33D-33H Connection electrode 34C-34F internal electrode

Claims (1)

[Claims] A first step of laminating an unfired ceramic sheet; a first through hole in the ceramic sheet that is to be electrically connected to an internal electrode on the ceramic sheet; A second step of forming a second through hole that is to be insulated from the internal electrode; and applying a conductive paint on the ceramic sheet on which the first and second through holes are formed; And a third step of forming a connection electrode in the first and second through-holes. The first to third steps are repeated each time an unfired ceramic sheet is laminated, and When the internal electrodes on each of the laminated ceramic sheets are connected in series, the connection electrode of the first through hole is connected to the internal electrode of the ceramic sheet immediately below. It is, the second
Is connected to the connection electrode of the second through hole of the ceramic sheet immediately below, and the internal electrodes on each of the stacked ceramic sheets are connected in parallel for every odd number and even number. In this case, the connection electrode of the first through-hole is located just below the second electrode of the ceramic sheet.
Wherein the connection electrode of the second through hole is connected to the connection electrode of the first through hole of the ceramic sheet immediately below. Manufacturing method of electronic components.