JP2001308659A - Differential amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent wrong inversion of the output from the output terminal with respect to the negative input that is made into the positive input terminal or into the negative input terminal. SOLUTION: When negative input is made into a new positive input terminal 1', a parasitic NPN transistor 16 is actuated which consists of the base comprised of an N-type epitaxial layer 24 of the lateral PNP transistor 2 whose collector is a P-type diffusion layer 23 separated at a P-type separation layer 21 and whose emitter is a P-type diffusion layer 23', and an N-type diffusion layer 22; a grounded P-type semiconductor substrate 20; and the base of a lateral PNP transistor 6. Then NPN transistor 27 is set up, whose collector is a resistor 26 consistor of a P-type diffusion layer 31 in the N-type epitaxial layer 24, a resistor 25 and the N-type epitaxial layer 24; whose base is the P-type diffusion layer 31 in the N-type eptiaxial layer 24; and whose emitter is an N-type diffusion layer 32 in the P-type diffusion layer 31. Thus, the voltage between the base of an NPN transistor 27 and emitter that is current- limited at the resistor 26 and actuated, is impressed between the base of the parasitic NPN transistor 16 and the emitter. At the same, time the current of the parasitic NPN transistor 16 is limited by the resistor 26. This can suppress actuation of the parasitic NPN transistor 16 and wrong inversion of the output will not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit in which an N-type epitaxial layer serving as a base of a lateral PNP transistor is used as an input terminal and an output terminal is not erroneously inverted with respect to a negative input at the input terminal.

[0002]

2. Description of the Related Art A conventional differential amplifying circuit formed as a bipolar semiconductor integrated circuit of this kind is configured as shown in FIG. In FIG. 7, 1 is a positive input terminal,
2, 4, 6, 8 are lateral PNP transistors, 3,
7, 10, 11 and 12 are NPN transistors, 5 is a current source, 9 is a negative input terminal, 13 is a resistor, 14 is an internal reference voltage, 15 is an output terminal, and 16 and 17 are parasitic NPN transistors.

FIG. 8A shows a lateral P shown in FIG.
8B is a cross-sectional view showing a schematic configuration of the lateral PNP transistors 4 and 8 shown in FIG. 8, 1 is a positive input terminal, 9 is a negative input terminal, 16 and 17 are parasitic NPN transistors, 20 is a P-type semiconductor substrate, 21 is a P-type isolation layer, 22 is an N-type diffusion layer, 2
3, 23 'are P-type diffusion layers, and 24 is an N-type epitaxial layer.

[0004] The circuit operation of the differential amplifier circuit configured as described above will be described. First, the voltage applied to the positive input terminal 1 is determined by the lateral PNP transistor 2 and the NP
The voltage is applied to the base of a lateral PNP transistor 4 via a level shift circuit composed of an N transistor 3. Further, the voltage applied to the negative input terminal 9 is a lateral P
The voltage is applied to the base of the lateral PNP transistor 6 via a level shift circuit composed of an NP transistor 8 and an NPN transistor 7. In addition, lateral PNP
The comparison is made by a differential circuit composed of the transistor 4 and the lateral PNP transistor 6.

Now, the voltage of the positive input terminal 1 is changed to the negative input terminal 9
Under the conditions higher than the voltage, the lateral PNP transistor 6 is in the operating state, the lateral PNP transistor 4 is in the inactive state, the current mirror circuit composed of the NPN transistors 10 and 11 is in the operating state, and the NPN transistor 12 is in the inactive state. As a result, the voltage of the output terminal 15 becomes the internal reference voltage 14.

Next, the voltage of the positive input terminal 1 is
Under the conditions lower than the voltage, the lateral PNP transistor 6 is inactive, the lateral PNP transistor 4 is active, the current mirror circuit composed of the NPN transistors 10 and 11 is inactive, and the NPN transistor 12 operates. In this state, the voltage at the output terminal 15 becomes the saturation voltage of the NPN transistor 12.

[0007]

However, a part of the differential amplifier circuit in the bipolar semiconductor integrated circuit having such a configuration is separated by a P-type separation layer 21 shown on the right side of FIG. Lateral PNP transistor 2 based on N type diffusion layer 23 as a collector, P type diffusion layer 23 'as an emitter, N type epitaxial layer 24 and N type diffusion layer 22, and a P type isolation layer shown on the left side of FIG. The lateral PNP transistor 6 includes a P-type diffusion layer 23 as a collector, a P-type diffusion layer 23 ′ as an emitter, and an N-type epitaxial layer 24 and an N-type diffusion layer 22 as bases.

Further, the P-type diffusion layer 23 is separated by a P-type separation layer 21 shown in the left side of FIG. 8B, the P-type diffusion layer 23 is a collector, the P-type diffusion layer 23 'is an emitter, the N-type epitaxial layer 24 and the N-type diffusion layer The P-type diffusion layer 23 is separated from the lateral PNP transistor 8 based on the P-type diffusion layer 2 by a P-type separation layer 21 shown on the right side of FIG.
3 'as an emitter, a lateral PNP transistor 4 based on an N-type epitaxial layer 24 and an N-type diffusion layer 22.
It is composed of

An N-type epitaxial layer 24 and an N-type diffusion layer 22, which are bases of the lateral PNP transistor 2, a grounded P-type semiconductor substrate 20, and a lateral PNP
N-type epitaxial layer 2 which is the base of transistor 6
4 and the N-type diffusion layer 22 make the parasitic NPN transistor 1
6 and N which is the base of the lateral PNP transistor 8.
-Type epitaxial layer 24, N-type diffusion layer 22, grounded P-type semiconductor substrate 20, lateral PNP transistor 4
The parasitic NPN transistor 17 is constituted by the N-type epitaxial layer 24 and the N-type diffusion layer 22 which are the bases of the transistors.

Here, when a negative voltage is applied to the negative input terminal 9 under the condition that the voltage of the positive input terminal 1 is higher than the voltage of the negative input terminal 9, the parasitic NPN transistor 17 operates and the lateral PNP transistor 4 When the base current is pulled, the lateral PNP transistor 4 is activated, and the lateral PNP
The transistor 6 becomes inactive, the current mirror circuit composed of the NPN transistor 10 and the NPN transistor 11 becomes inactive, the NPN transistor 12 becomes active, and the voltage of the output terminal 15 becomes the saturation voltage of the NPN transistor 12. The output is incorrectly inverted.

The voltage at the positive input terminal 1 is
When the negative voltage is applied to the positive input terminal 1 under the condition higher than the voltage of the negative PNP transistor 1, the parasitic NPN transistor 16 operates, the base current of the lateral PNP transistor 6 is pulled, the lateral PNP transistor 4 is in the non-operation state, and the lateral PNP
The transistor 6 is turned on, the current mirror circuit composed of the NPN transistor 10 and the NPN transistor 11 is turned on, the NPN transistor 12 is turned off, and the voltage of the output terminal 15 is changed to the internal reference voltage 14.
And the output is erroneously inverted.

SUMMARY OF THE INVENTION The present invention is directed to solving the above-mentioned problem of the prior art, and is directed to a differential which does not erroneously invert an output from an output terminal with respect to a negative input input to a positive input terminal or a negative input terminal. It is an object to provide an amplifier circuit.

[0013]

In order to achieve this object, a differential amplifier circuit according to the present invention comprises a bipolar semiconductor integrated circuit in which a transistor at an input portion is a lateral PNP transistor.
A differential amplifying circuit formed by transistors, a terminal connected to a base of a lateral PNP transistor;
One end is connected to this terminal and the other end is connected to a positive input terminal or a negative input terminal to which a negative input signal is input. A transistor having an emitter connected thereto and a collector and a base grounded.

In the bipolar semiconductor integrated circuit, a first lateral PNP transistor having a positive input terminal connected to the base and a collector grounded, and a first lateral PNP transistor having an emitter connected to the first lateral PNP transistor. An NPN transistor, a second lateral PNP transistor having a base connected to a connection point between the base and the collector of the first NPN transistor, and an emitter connected to a connection point between the emitter of the second lateral PNP transistor and the current source A third lateral PNP transistor, a second NPN transistor having a base connected to the collector-base connection point of the third lateral PNP transistor, an emitter and an emitter of the second NPN transistor, and a negative input terminal. Connect the base and connect the fourth A third PNP transistor, a collector and a collector of a third lateral PNP transistor are connected to each other, and a third NPN transistor whose emitter is grounded; a connection point of a collector and a base of the third NPN transistor is connected to a base; Is the fourth N grounded
A PN transistor, a connection point and a base between a collector of the fourth NPN transistor and a collector of the second lateral PNP transistor, and a collector connected to the internal reference voltage via the first resistor; NP
An N-channel transistor, and an output terminal provided between the collector of the fifth NPN transistor and the first resistor;
A second resistor formed of a P-type diffusion layer in an N-type epitaxial layer separated by a P-type isolation layer, on a P-type semiconductor substrate on which a first lateral NPN transistor is formed before a positive input terminal; A third resistor composed of a P-type diffusion layer in the N-type epitaxial layer separated by the separation layer; a collector of the N-type epitaxial layer separated by the P-type separation layer; and a P-type diffusion layer in the N-type epitaxial layer. Base, P
NPN having an N-type diffusion layer in the N-type diffusion layer as an emitter
A transistor, and one of a positive input terminal and a third resistor;
The emitter of a sixth NPN transistor whose collector and base are grounded is connected to the other connection point of the third resistor and the other of the second resistor and the other connection point of the third resistor and the other of the second resistor, One of the second resistors is a new positive input terminal.

On a P-type semiconductor substrate on which a fourth lateral NPN transistor is formed before the negative input terminal, a fourth P-type diffusion layer formed of an N-type epitaxial layer separated by a P-type separation layer is formed. , A fifth resistor composed of a P-type diffusion layer in the N-type epitaxial layer separated by the P-type separation layer, and a collector formed by the N-type epitaxial layer separated by the P-type separation layer. A seventh NPN transistor having a P-type diffusion layer as a base and an N-type diffusion layer in the P-type diffusion layer as an emitter is provided, and one of the positive input terminal and the fifth resistor, the other of the fifth resistor and the fourth And the other connection point of the fifth resistor and the other connection point of the fourth resistor are connected to the emitter of a seventh NPN transistor whose collector and base are grounded, and one of the fourth resistors is connected to a new one. Negative input terminal Are those that you configured.

According to the above configuration, the differential amplifier circuit of the present invention comprises two serially connected ones or both between the positive input terminal and the base of the lateral PNP transistor or between the negative input terminal and the base of the lateral PNP transistor. A parasitic NPN transistor that is generated when a negative input is applied to a new positive input terminal or a negative input terminal by connecting a resistor and connecting the emitter of an NPN transistor whose collector and base are grounded to the connection point of the resistor. Between the base and the emitter of the NPN is operated with current limited by a resistor directly connected to the positive input terminal or the negative input terminal.
The voltage between the base and the emitter of the transistor is applied, and the current flowing through the parasitic NPN transistor is limited by a resistor connected between the emitter of the NPN transistor and the base of the lateral PNP transistor, whereby the operation of the parasitic NPN transistor is suppressed and the output terminal Erroneous inversion of the output from the device can be eliminated.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing a differential amplifier circuit according to the first embodiment of the present invention. Here, components having substantially the same functions as those described in FIG. 7 showing the conventional example and having substantially the same functions are denoted by the same reference numerals, and the same applies hereinafter. In FIG. 1, 1 'is a new positive input terminal, 2, 4, 6, and 8 are lateral PNP transistors,
3, 7, 10, 11, 12 are NPN transistors, 5 is a current source, 9 is a negative input terminal, 13 is a resistor, 14 is an internal reference voltage, 15 is an output terminal, 16 and 17 are parasitic NPN transistors, 25 and 26. Is a resistor, and 27 is an NPN transistor.

FIG. 2 shows the lateral PNP shown in FIG.
FIG. 3 is a sectional view showing a schematic configuration of transistors 2 and 6, resistors 25 and 26, and an NPN transistor 27. In FIG. 2, 1 'is a new positive input terminal, 16 is a parasitic NPN transistor, 20 is a P-type semiconductor substrate, 21 Is a P-type separation layer, 2
2 is an N-type diffusion layer; 23 and 23 'are P-type diffusion layers;
Type epitaxial layer, 31 is a P-type diffusion layer, and 32 is an N-type diffusion layer.

Next, the operation of the first embodiment configured as described above will be described. When a negative input is made to the new positive input terminal 1 ', the N-type epitaxial layer 2 of the lateral PNP transistor 2 is separated by the P-type separation layer 21 and has the P-type diffusion layer 23 as a collector and the P-type diffusion layer 23' as an emitter.
4 and an N-type diffusion layer 22 and a grounded P
Separated by a P-type semiconductor substrate 20 and a P-type separation layer 21.
The parasitic NPN transistor 16 is constituted by the base composed of the N-type epitaxial layer 24 and the N-type diffusion layer 22 of the lateral PNP transistor 5 using the type diffusion layer 23 as a collector and the P-type diffusion layer 23 ′ as an emitter.

Further, as shown in FIG.
The resistor 26 is formed by the P-type diffusion layer 31 formed in the N-type epitaxial layer 24 and separated by the P-type diffusion layer 31 formed in the N-type epitaxial layer 24 separated by the P-type separation layer 21. And a collector, which is an N-type epitaxial layer 24 separated by the P-type separation layer 21, a base, which is a P-type diffusion layer 31 formed in the N-type epitaxial layer 24, and N formed in the P-type diffusion layer 31. An NPN transistor 27 including an emitter serving as the type diffusion layer 32 is formed.

A voltage is applied between the base and the emitter of the parasitic NPN transistor 16, the voltage between the base and the emitter of the NPN transistor 27, which operates while being current-limited by the resistor 26, and flows through the parasitic NPN transistor 16. Is limited by the resistor 26, the operation of the parasitic NPN transistor 16 can be suppressed.

As described above, the operation of the parasitic NPN transistor 16 is suppressed, and the output from the output terminal 15 is not erroneously inverted, but is erroneously inverted even when a negative input is made to the new positive input terminal 1 '. A differential amplifier circuit that does not perform the above operation is obtained.

FIG. 3 is a diagram showing a differential amplifier circuit according to the second embodiment of the present invention. In FIG. 3, 1 is a positive input terminal, 2, 4, 6, and 8 are lateral PNP transistors,
3, 7, 10, 11, 12 are NPN transistors, 5 is a current source, 9 'is a new negative input terminal, 13 is a resistor, 14 is an internal reference voltage, 15 is an output terminal, and 16 and 17 are parasitic NPs.
N transistors, 28 and 29 are resistors, and 30 is an NPN transistor.

FIG. 4 shows the lateral PNP shown in FIG.
FIG. 5 is a sectional view showing a schematic configuration of transistors 4 and 8, resistors 28 and 29, and an NPN transistor 30. In FIG. 4, 9 'is a new negative input terminal, 17 is a parasitic NPN transistor, 20 is a P-type semiconductor substrate, 21 is a P-type separation layer,
22 is an N-type diffusion layer, 23 and 23 'are P-type diffusion layers, 24 is an N-type epitaxial layer, 31 is a P-type diffusion layer, and 32 is an N-type diffusion layer.

The operation of the second embodiment configured as described above will be described. When a negative input is made to the new negative input terminal 9 ', the N-type epitaxial layer 24 of the lateral PNP transistor 8 is separated by the P-type separation layer 21 and has the P-type diffusion layer 23 as a collector and the P-type diffusion layer 23' as an emitter. A lateral PNP transistor separated by a P-type semiconductor substrate 20 and a P-type isolation layer 21 and having a P-type diffusion layer 23 as a collector and a P-type diffusion layer 23 'as an emitter. The parasitic NPN transistor 17 is constituted by the base composed of the four N-type epitaxial layers 24 and the N-type diffusion layers 22.

Further, as shown in FIG.
The resistor 29 is formed by the P-type diffusion layer 31 formed in the N-type epitaxial layer 24 and separated by the P-type diffusion layer 31 formed in the N-type epitaxial layer 24 similarly separated by the P-type separation layer 21. And a collector, which is an N-type epitaxial layer 24 separated by the P-type separation layer 21, a base, which is a P-type diffusion layer 31 formed in the N-type epitaxial layer 24, and N formed in the P-type diffusion layer 31. An NPN transistor 30 including an emitter, which is the type diffusion layer 32, is configured.

Between the base and the emitter of the parasitic NPN transistor 17, a voltage between the base and the emitter of the NPN transistor 30 which operates while being current-limited by the resistor 29 is applied, and the current flowing through the parasitic NPN transistor 17 is applied. Is limited by the resistor 29, the operation of the parasitic NPN transistor 17 can be suppressed.

As described above, the operation of the parasitic NPN transistor 17 is suppressed, and the output from the output terminal 15 is not erroneously inverted, and the erroneous inversion is performed even when a negative input is made to the new negative input terminal 9 '. A differential amplifier circuit that does not perform the above operation is obtained.

FIG. 5 is a diagram showing a differential amplifier circuit according to the third embodiment of the present invention. FIG. 6A is a diagram showing the lateral PNP transistors 2, 6 and resistors 25, 2 shown in FIG.
6 and the NPN transistor 27, FIG.
Lateral PNP transistors 4, 8 and resistor 28,
29 is a cross-sectional view illustrating a schematic configuration of an NPN transistor 30.

In the third embodiment, since the differential amplifier circuit is a combination of the configurations described in the first and second embodiments, the description of the overlapping components will be omitted. The operation of the third embodiment will be described below. First, when a negative input is made to the new positive input terminal 1 ', as shown in the cross-sectional view of FIG. 6A, the base composed of the N-type epitaxial layer 24 and the N-type diffusion layer 22 of the lateral PNP transistor 2 is formed. , A grounded P-type semiconductor substrate 20 and a lateral PN
The parasitic NPN transistor 16 is formed by the base of the P transistor 6 including the N-type epitaxial layer 24 and the N-type diffusion layer 22.

An NPN transistor operates between the base and the emitter of the parasitic NPN transistor 16 with current being limited by a resistor 26.
When a voltage is applied between the base (P-type diffusion layer 31) and the emitter (N-type diffusion layer 32) of the transistor 27 and the parasitic N
Since the current flowing through the PN transistor 16 is limited by the resistor 26, the operation of the parasitic NPN transistor 16 is suppressed.

When a negative voltage is input to a new negative input terminal 9 ', as shown in the sectional view of FIG.
The base composed of the N-type epitaxial layer 24 and the N-type diffusion layer 22 of the lateral PNP transistor 8, the grounded P-type semiconductor substrate 20, and the lateral PNP transistor 4
The parasitic NPN transistor 17 is constituted by the base composed of the N-type epitaxial layer 24 and the N-type diffusion layer 22.

The current between the base and the emitter of the parasitic NPN transistor 17 is limited by a resistor 29 composed of a P-type diffusion layer 31 separated by a P-type isolation layer 21 and formed in an N-type epitaxial layer 24. NPN to do
A voltage is applied between the base (P-type diffusion layer 31) and the emitter (N-type diffusion layer 32) of the transistor 30 and the parasitic N
Since the current flowing through the PN transistor 17 is limited by the resistor 29, the operation of the parasitic NPN transistor 17 is suppressed.

As described above, the operations of the parasitic NPN transistors 16 and 17 are suppressed, and the output from the output terminal 15 is not erroneously inverted, and the negative input terminal 1 'and the new negative input terminal 9' are not negatively inverted. A differential amplifier circuit that does not erroneously invert even when input is obtained.

[0036]

As described above, according to the present invention,
Two resistors are connected in series between one or both of the positive input terminal and the base of the lateral PNP transistor, or between the negative input terminal and the base of the lateral PNP transistor,
By providing a circuit in which the emitter of the NPN transistor is connected to the connection point and the collector and the base are grounded, when a negative voltage is input to a new positive input terminal or a new negative input terminal, any circuit in the integrated circuit can be used. Collector of N-type epitaxial layer, base of semiconductor substrate, base of lateral PNP transistor (N-type epitaxial layer)
Is formed as a parasitic NPN transistor. A voltage is applied between the base and the emitter of the parasitic NPN transistor, and the voltage between the base and the emitter of the NPN transistor that operates with the current limited by a resistor directly connected to the positive input terminal or the negative input terminal is applied, and the parasitic NP
Since the current flowing through the N-transistor is limited by the resistor, the operation of the parasitic NPN transistor is suppressed, and an excellent differential amplifier circuit in which the output from the output terminal is not erroneously inverted can be obtained. .

[Brief description of the drawings]

FIG. 1 is a diagram showing a differential amplifier circuit according to a first embodiment of the present invention.

FIG. 2 shows a lateral PNP transistor 2 shown in FIG.
6, sectional view showing a schematic configuration of the resistors 25 and 26 and the NPN transistor 27

FIG. 3 is a diagram showing a differential amplifier circuit according to a second embodiment of the present invention.

FIG. 4 shows a lateral PNP transistor 4 shown in FIG.
8, a cross-sectional view showing a schematic configuration of the resistors 28 and 29 and the NPN transistor 30

FIG. 5 is a diagram showing a differential amplifier circuit according to a third embodiment of the present invention.

FIG. 6A is a diagram illustrating the lateral PNP transistors 2 and 6, the resistors 25 and 26, and the NPN transistor 2 illustrated in FIG. 5;
7, (b) shows lateral PNP transistors 4 and 8, resistors 28 and 29, and NPN transistor 30 shown in FIG.
Sectional view showing the schematic configuration of

FIG. 7 is a diagram showing a conventional differential amplifier circuit.

8A is a cross-sectional view showing a schematic configuration of the lateral PNP transistors 2 and 6 shown in FIG. 7, and FIG. 8B is a cross-sectional view showing a schematic configuration of the lateral PNP transistors 4 and 8 shown in FIG.

[Explanation of symbols]

1 Positive input terminal 1 'New positive input terminal 2, 4, 6, 8, Lateral PNP transistor 3, 7, 10, 11, 12, 27, 30 NPN transistor 5 Current source 9 Negative input terminal 9' New negative input Terminals 13, 25, 26, 28, 29 Resistance 14 Internal reference voltage 15 Output terminal 16, 17 Parasitic NPN transistor 20 P-type semiconductor substrate 21 P-type separation layer 22, 32 N-type diffusion layer 23, 23 ', 31 P-type diffusion Layer 24 N-type epitaxial layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/73 F term (Reference) 5F003 AP04 BB05 BJ20 BJ99 BN01 BZ05 5F082 AA26 BA02 BC03 BC04 BC16 FA03 GA04 5J066 AA01 AA12 CA00 FA04 HA03 HA08 HA25 KA05 KA09 KA18 MA04 MA21 ND01 ND14 ND22 ND23 PD01 QA02

Claims (4)

[Claims] 1. A differential amplifier circuit in which a transistor at an input portion of a bipolar semiconductor integrated circuit is formed by a lateral PNP transistor, wherein a terminal connected to a base of the lateral PNP transistor and one end is connected to the terminal. A series connection column of a plurality of resistors connected to a positive input terminal or a negative input terminal to which a negative signal is input at the other end, an emitter is connected to one connection point of the series connection column, and a collector and a base are connected. A differential amplifier circuit comprising: a grounded transistor. 2. A bipolar semiconductor integrated circuit, comprising: a first input terminal connected to a positive input terminal and a base; and a collector grounded.
Lateral PNP transistor, a first NPN transistor having an emitter-emitter connected to the first lateral PNP transistor, and a second NPN transistor having a base connected to a connection point between a base and a collector of the first NPN transistor. A lateral PNP transistor, a third lateral PNP transistor having an emitter connected to a connection point between an emitter of the second lateral PNP transistor and a current source, and a collector-base connection of the base of the third lateral PNP transistor The second N connected to the point
A PN transistor, a fourth lateral PNP transistor having an emitter and an emitter, a negative input terminal and a base connected to each other and a collector grounded, and a collector and a collector of the third lateral PNP transistor connected to each other. Third, with the emitter grounded
NPN transistor, a fourth NPN transistor having a collector connected to the base of the third NPN transistor and a base connected to the base and having an emitter grounded, a collector of the fourth NPN transistor and the second lateral A fifth connection point of the collector of the PNP transistor and the base, and a collector connected to the internal reference voltage via the first resistor, and a fifth NPN transistor having an emitter grounded; a collector of the fifth NPN transistor; And an output terminal provided between the first input terminal and the positive input terminal, and an N-type separated by a P-type separation layer on a P-type semiconductor substrate on which the first lateral NPN transistor is formed in a stage preceding the positive input terminal. A second resistor composed of a P-type diffusion layer in the epitaxial layer and a P-type diffusion layer in the N-type epitaxial layer separated by the P-type separation layer; A third resistor composed of a diffused layer, an N-type epitaxial layer separated by a P-type isolation layer as a collector, a P-type diffusion layer in the N-type epitaxial layer as a base, and an N-type diffusion layer in the P-type diffusion layer A sixth NPN transistor having a positive input terminal and one of the third resistor, the other of the third resistor, the other of the second resistor, and the other of the third resistor. An emitter of the sixth NPN transistor whose collector and base are grounded is connected to a connection point of the second resistor with the other, and one of the second resistors is used as a new positive input terminal. Differential amplifier circuit. 3. A bipolar semiconductor integrated circuit, wherein a first input terminal is connected to a base, and a collector is grounded.
Lateral PNP transistor, a first NPN transistor having an emitter-emitter connected to the first lateral PNP transistor, and a second NPN transistor having a base connected to a connection point between a base and a collector of the first NPN transistor. A lateral PNP transistor, a third lateral PNP transistor having an emitter connected to a connection point between the emitter of the second lateral PNP transistor and a current source, and a collector-base connection of the base of the third lateral PNP transistor The second N connected to the point
A PN transistor, a fourth lateral PNP transistor having an emitter and an emitter, a negative input terminal and a base connected to each other and a collector grounded, and a collector and a collector of the third lateral PNP transistor connected to each other. Third, with the emitter grounded
NPN transistor, a fourth NPN transistor having a collector connected to the base of the third NPN transistor and a base connected to the base and having an emitter grounded, a collector of the fourth NPN transistor and the second lateral A fifth connection point of the collector of the PNP transistor and the base, and a collector connected to the internal reference voltage via the first resistor, and a fifth NPN transistor having an emitter grounded; a collector of the fifth NPN transistor; And an output terminal provided between the P-type semiconductor substrate and the P-type semiconductor substrate forming the fourth lateral NPN transistor in front of the negative input terminal. A fourth resistor formed of a P-type diffusion layer in the epitaxial layer and a P-type diffusion layer in the N-type epitaxial layer separated by the P-type separation layer; A fifth resistor composed of a diffused layer, an N-type epitaxial layer separated by a P-type isolation layer as a collector, a P-type diffusion layer in the N-type epitaxial layer as a base, and an N-type diffusion layer in the P-type diffusion layer A seventh NPN transistor having an emitter as the emitter, and one of the positive input terminal and the fifth resistor, the other of the fifth resistor, the other of the fourth resistor, and the other of the fifth resistor. A connection point with the other of the fourth resistors is connected to an emitter of the seventh NPN transistor whose collector and base are grounded, and one of the fourth resistors is used as a new negative input terminal. Differential amplifier circuit. 4. In a bipolar semiconductor integrated circuit, a first input terminal is connected to a base and a collector is grounded.
Lateral PNP transistor, a first NPN transistor having an emitter-emitter connected to the first lateral PNP transistor, and a second NPN transistor having a base connected to a connection point between a base and a collector of the first NPN transistor. A lateral PNP transistor, a third lateral PNP transistor having an emitter connected to a connection point between an emitter of the second lateral PNP transistor and a current source, and a collector-base connection of the base of the third lateral PNP transistor The second N connected to the point
A PN transistor, a fourth lateral PNP transistor having an emitter and an emitter, a negative input terminal and a base connected to each other and a collector grounded, and a collector and a collector of the third lateral PNP transistor connected to each other. Third, with the emitter grounded
NPN transistor, a fourth NPN transistor having a collector connected to the base of the third NPN transistor and a base connected to the base and having an emitter grounded, a collector of the fourth NPN transistor and the second lateral A fifth connection point of the collector of the PNP transistor and the base, and a collector connected to the internal reference voltage via the first resistor, and a fifth NPN transistor having an emitter grounded; a collector of the fifth NPN transistor; And an output terminal provided between the first input terminal and the positive input terminal, and an N-type separated by a P-type separation layer on a P-type semiconductor substrate on which the first lateral NPN transistor is formed in a stage preceding the positive input terminal. A second resistor composed of a P-type diffusion layer in the epitaxial layer and a P-type diffusion layer in the N-type epitaxial layer separated by the P-type separation layer; A third resistor composed of a diffused layer, an N-type epitaxial layer separated by a P-type isolation layer as a collector, a P-type diffusion layer in the N-type epitaxial layer as a base, and an N-type diffusion layer in the P-type diffusion layer A sixth NPN transistor having a positive input terminal and one of the third resistor, the other of the third resistor, the other of the second resistor, and the other of the third resistor. An emitter of the sixth NPN transistor having a collector and a base grounded is connected to a connection point with the other of the second resistors, and one of the second resistors is used as a new positive input terminal; A fourth resistor formed of a P-type diffusion layer in an N-type epitaxial layer separated by a P-type separation layer, on a P-type semiconductor substrate on which the fourth lateral NPN transistor is formed in a stage preceding the above, and a P-type separation layer Separated by A fifth resistor composed of a P-type diffusion layer in the N-type epitaxial layer, an N-type epitaxial layer separated by a P-type separation layer as a collector, a P-type diffusion layer in the N-type epitaxial layer as a base, A seventh NPN transistor having an N-type diffusion layer in the diffusion layer as an emitter is provided, one of the positive input terminal and the fifth resistance, the other of the fifth resistance and the other of the fourth resistance, and A connection point between the other of the fifth resistors and the other of the fourth resistors is connected to the emitter of the seventh NPN transistor whose collector and base are grounded, and one of the fourth resistors is connected to a new negative electrode. A differential amplifier circuit characterized as an input terminal.